lib/Target/AArch64/AArch64Subtarget.h

   1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file declares the AArch64 specific subclass of TargetSubtarget.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
  14 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
  15
  16 #include "AArch64FrameLowering.h"
  17 #include "AArch64ISelLowering.h"
  18 #include "AArch64InstrInfo.h"
  19 #include "AArch64RegisterInfo.h"
  20 #include "AArch64SelectionDAGInfo.h"
  21 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
  22 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
  23 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
  24 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
  25 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  26 #include "llvm/IR/DataLayout.h"
  27 #include <string>
  28
  29 #define GET_SUBTARGETINFO_HEADER
  30 #include "AArch64GenSubtargetInfo.inc"
  31
  32 namespace llvm {
  33 class GlobalValue;
  34 class StringRef;
  35 class Triple;
  36
  37 class AArch64Subtarget final : public AArch64GenSubtargetInfo {
  38 public:
  39   enum ARMProcFamilyEnum : uint8_t {
  40     Others,
  41     CortexA35,
  42     CortexA53,
  43     CortexA55,
  44     CortexA57,
  45     CortexA65,
  46     CortexA72,
  47     CortexA73,
  48     CortexA75,
  49     CortexA76,
  50     Cyclone,
  51     ExynosM1,
  52     ExynosM3,
  53     Falkor,
  54     Kryo,
  55     NeoverseE1,
  56     NeoverseN1,
  57     Saphira,
  58     ThunderX2T99,
  59     ThunderX,
  60     ThunderXT81,
  61     ThunderXT83,
  62     ThunderXT88,
  63     TSV110
  64   };
  65
  66 protected:
  67   /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
  68   ARMProcFamilyEnum ARMProcFamily = Others;
  69
  70   bool HasV8_1aOps = false;
  71   bool HasV8_2aOps = false;
  72   bool HasV8_3aOps = false;
  73   bool HasV8_4aOps = false;
  74   bool HasV8_5aOps = false;
  75
  76   bool HasFPARMv8 = false;
  77   bool HasNEON = false;
  78   bool HasCrypto = false;
  79   bool HasDotProd = false;
  80   bool HasCRC = false;
  81   bool HasLSE = false;
  82   bool HasRAS = false;
  83   bool HasRDM = false;
  84   bool HasPerfMon = false;
  85   bool HasFullFP16 = false;
  86   bool HasFP16FML = false;
  87   bool HasSPE = false;
  88
  89   // ARMv8.1 extensions
  90   bool HasVH = false;
  91   bool HasPAN = false;
  92   bool HasLOR = false;
  93
  94   // ARMv8.2 extensions
  95   bool HasPsUAO = false;
  96   bool HasPAN_RWV = false;
  97   bool HasCCPP = false;
  98
  99   // Armv8.2 Crypto extensions
 100   bool HasSM4 = false;
 101   bool HasSHA3 = false;
 102   bool HasSHA2 = false;
 103   bool HasAES = false;
 104
 105   // ARMv8.3 extensions
 106   bool HasPA = false;
 107   bool HasJS = false;
 108   bool HasCCIDX = false;
 109   bool HasComplxNum = false;
 110
 111   // ARMv8.4 extensions
 112   bool HasNV = false;
 113   bool HasRASv8_4 = false;
 114   bool HasMPAM = false;
 115   bool HasDIT = false;
 116   bool HasTRACEV8_4 = false;
 117   bool HasAM = false;
 118   bool HasSEL2 = false;
 119   bool HasTLB_RMI = false;
 120   bool HasFMI = false;
 121   bool HasRCPC_IMMO = false;
 122
 123   bool HasLSLFast = false;
 124   bool HasSVE = false;
 125   bool HasSVE2 = false;
 126   bool HasRCPC = false;
 127   bool HasAggressiveFMA = false;
 128
 129   // Armv8.5-A Extensions
 130   bool HasAlternativeNZCV = false;
 131   bool HasFRInt3264 = false;
 132   bool HasSpecRestrict = false;
 133   bool HasSSBS = false;
 134   bool HasSB = false;
 135   bool HasPredRes = false;
 136   bool HasCCDP = false;
 137   bool HasBTI = false;
 138   bool HasRandGen = false;
 139   bool HasMTE = false;
 140
 141   // Arm SVE2 extensions
 142   bool HasSVE2AES = false;
 143   bool HasSVE2SM4 = false;
 144   bool HasSVE2SHA3 = false;
 145   bool HasSVE2BitPerm = false;
 146
 147   // Future architecture extensions.
 148   bool HasETE = false;
 149   bool HasTRBE = false;
 150
 151   // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
 152   bool HasZeroCycleRegMove = false;
 153
 154   // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
 155   bool HasZeroCycleZeroing = false;
 156   bool HasZeroCycleZeroingGP = false;
 157   bool HasZeroCycleZeroingFP = false;
 158   bool HasZeroCycleZeroingFPWorkaround = false;
 159
 160   // StrictAlign - Disallow unaligned memory accesses.
 161   bool StrictAlign = false;
 162
 163   // NegativeImmediates - transform instructions with negative immediates
 164   bool NegativeImmediates = true;
 165
 166   // Enable 64-bit vectorization in SLP.
 167   unsigned MinVectorRegisterBitWidth = 64;
 168
 169   bool UseAA = false;
 170   bool PredictableSelectIsExpensive = false;
 171   bool BalanceFPOps = false;
 172   bool CustomAsCheapAsMove = false;
 173   bool ExynosAsCheapAsMove = false;
 174   bool UsePostRAScheduler = false;
 175   bool Misaligned128StoreIsSlow = false;
 176   bool Paired128IsSlow = false;
 177   bool STRQroIsSlow = false;
 178   bool UseAlternateSExtLoadCVTF32Pattern = false;
 179   bool HasArithmeticBccFusion = false;
 180   bool HasArithmeticCbzFusion = false;
 181   bool HasFuseAddress = false;
 182   bool HasFuseAES = false;
 183   bool HasFuseArithmeticLogic = false;
 184   bool HasFuseCCSelect = false;
 185   bool HasFuseCryptoEOR = false;
 186   bool HasFuseLiterals = false;
 187   bool DisableLatencySchedHeuristic = false;
 188   bool UseRSqrt = false;
 189   bool Force32BitJumpTables = false;
 190   bool UseEL1ForTP = false;
 191   bool UseEL2ForTP = false;
 192   bool UseEL3ForTP = false;
 193   uint8_t MaxInterleaveFactor = 2;
 194   uint8_t VectorInsertExtractBaseCost = 3;
 195   uint16_t CacheLineSize = 0;
 196   uint16_t PrefetchDistance = 0;
 197   uint16_t MinPrefetchStride = 1;
 198   unsigned MaxPrefetchIterationsAhead = UINT_MAX;
 199   unsigned PrefFunctionAlignment = 0;
 200   unsigned PrefLoopAlignment = 0;
 201   unsigned MaxJumpTableSize = 0;
 202   unsigned WideningBaseCost = 0;
 203
 204   // ReserveXRegister[i] - X#i is not available as a general purpose register.
 205   BitVector ReserveXRegister;
 206
 207   // CustomCallUsedXRegister[i] - X#i call saved.
 208   BitVector CustomCallSavedXRegs;
 209
 210   bool IsLittle;
 211
 212   /// TargetTriple - What processor and OS we're targeting.
 213   Triple TargetTriple;
 214
 215   AArch64FrameLowering FrameLowering;
 216   AArch64InstrInfo InstrInfo;
 217   AArch64SelectionDAGInfo TSInfo;
 218   AArch64TargetLowering TLInfo;
 219
 220   /// GlobalISel related APIs.
 221   std::unique_ptr<CallLowering> CallLoweringInfo;
 222   std::unique_ptr<InstructionSelector> InstSelector;
 223   std::unique_ptr<LegalizerInfo> Legalizer;
 224   std::unique_ptr<RegisterBankInfo> RegBankInfo;
 225
 226 private:
 227   /// initializeSubtargetDependencies - Initializes using CPUString and the
 228   /// passed in feature string so that we can use initializer lists for
 229   /// subtarget initialization.
 230   AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
 231                                                     StringRef CPUString);
 232
 233   /// Initialize properties based on the selected processor family.
 234   void initializeProperties();
 235
 236 public:
 237   /// This constructor initializes the data members to match that
 238   /// of the specified triple.
 239   AArch64Subtarget(const Triple &TT, const std::string &CPU,
 240                    const std::string &FS, const TargetMachine &TM,
 241                    bool LittleEndian);
 242
 243   const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
 244     return &TSInfo;
 245   }
 246   const AArch64FrameLowering *getFrameLowering() const override {
 247     return &FrameLowering;
 248   }
 249   const AArch64TargetLowering *getTargetLowering() const override {
 250     return &TLInfo;
 251   }
 252   const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
 253   const AArch64RegisterInfo *getRegisterInfo() const override {
 254     return &getInstrInfo()->getRegisterInfo();
 255   }
 256   const CallLowering *getCallLowering() const override;
 257   const InstructionSelector *getInstructionSelector() const override;
 258   const LegalizerInfo *getLegalizerInfo() const override;
 259   const RegisterBankInfo *getRegBankInfo() const override;
 260   const Triple &getTargetTriple() const { return TargetTriple; }
 261   bool enableMachineScheduler() const override { return true; }
 262   bool enablePostRAScheduler() const override {
 263     return UsePostRAScheduler;
 264   }
 265
 266   /// Returns ARM processor family.
 267   /// Avoid this function! CPU specifics should be kept local to this class
 268   /// and preferably modeled with SubtargetFeatures or properties in
 269   /// initializeProperties().
 270   ARMProcFamilyEnum getProcFamily() const {
 271     return ARMProcFamily;
 272   }
 273
 274   bool hasV8_1aOps() const { return HasV8_1aOps; }
 275   bool hasV8_2aOps() const { return HasV8_2aOps; }
 276   bool hasV8_3aOps() const { return HasV8_3aOps; }
 277   bool hasV8_4aOps() const { return HasV8_4aOps; }
 278   bool hasV8_5aOps() const { return HasV8_5aOps; }
 279
 280   bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
 281
 282   bool hasZeroCycleZeroingGP() const { return HasZeroCycleZeroingGP; }
 283
 284   bool hasZeroCycleZeroingFP() const { return HasZeroCycleZeroingFP; }
 285
 286   bool hasZeroCycleZeroingFPWorkaround() const {
 287     return HasZeroCycleZeroingFPWorkaround;
 288   }
 289
 290   bool requiresStrictAlign() const { return StrictAlign; }
 291
 292   bool isXRaySupported() const override { return true; }
 293
 294   unsigned getMinVectorRegisterBitWidth() const {
 295     return MinVectorRegisterBitWidth;
 296   }
 297
 298   bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
 299   unsigned getNumXRegisterReserved() const { return ReserveXRegister.count(); }
 300   bool isXRegCustomCalleeSaved(size_t i) const {
 301     return CustomCallSavedXRegs[i];
 302   }
 303   bool hasCustomCallingConv() const { return CustomCallSavedXRegs.any(); }
 304   bool hasFPARMv8() const { return HasFPARMv8; }
 305   bool hasNEON() const { return HasNEON; }
 306   bool hasCrypto() const { return HasCrypto; }
 307   bool hasDotProd() const { return HasDotProd; }
 308   bool hasCRC() const { return HasCRC; }
 309   bool hasLSE() const { return HasLSE; }
 310   bool hasRAS() const { return HasRAS; }
 311   bool hasRDM() const { return HasRDM; }
 312   bool hasSM4() const { return HasSM4; }
 313   bool hasSHA3() const { return HasSHA3; }
 314   bool hasSHA2() const { return HasSHA2; }
 315   bool hasAES() const { return HasAES; }
 316   bool balanceFPOps() const { return BalanceFPOps; }
 317   bool predictableSelectIsExpensive() const {
 318     return PredictableSelectIsExpensive;
 319   }
 320   bool hasCustomCheapAsMoveHandling() const { return CustomAsCheapAsMove; }
 321   bool hasExynosCheapAsMoveHandling() const { return ExynosAsCheapAsMove; }
 322   bool isMisaligned128StoreSlow() const { return Misaligned128StoreIsSlow; }
 323   bool isPaired128Slow() const { return Paired128IsSlow; }
 324   bool isSTRQroSlow() const { return STRQroIsSlow; }
 325   bool useAlternateSExtLoadCVTF32Pattern() const {
 326     return UseAlternateSExtLoadCVTF32Pattern;
 327   }
 328   bool hasArithmeticBccFusion() const { return HasArithmeticBccFusion; }
 329   bool hasArithmeticCbzFusion() const { return HasArithmeticCbzFusion; }
 330   bool hasFuseAddress() const { return HasFuseAddress; }
 331   bool hasFuseAES() const { return HasFuseAES; }
 332   bool hasFuseArithmeticLogic() const { return HasFuseArithmeticLogic; }
 333   bool hasFuseCCSelect() const { return HasFuseCCSelect; }
 334   bool hasFuseCryptoEOR() const { return HasFuseCryptoEOR; }
 335   bool hasFuseLiterals() const { return HasFuseLiterals; }
 336
 337   /// Return true if the CPU supports any kind of instruction fusion.
 338   bool hasFusion() const {
 339     return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||
 340            hasFuseAES() || hasFuseArithmeticLogic() ||
 341            hasFuseCCSelect() || hasFuseLiterals();
 342   }
 343
 344   bool useEL1ForTP() const { return UseEL1ForTP; }
 345   bool useEL2ForTP() const { return UseEL2ForTP; }
 346   bool useEL3ForTP() const { return UseEL3ForTP; }
 347
 348   bool useRSqrt() const { return UseRSqrt; }
 349   bool force32BitJumpTables() const { return Force32BitJumpTables; }
 350   unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
 351   unsigned getVectorInsertExtractBaseCost() const {
 352     return VectorInsertExtractBaseCost;
 353   }
 354   unsigned getCacheLineSize() const { return CacheLineSize; }
 355   unsigned getPrefetchDistance() const { return PrefetchDistance; }
 356   unsigned getMinPrefetchStride() const { return MinPrefetchStride; }
 357   unsigned getMaxPrefetchIterationsAhead() const {
 358     return MaxPrefetchIterationsAhead;
 359   }
 360   unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
 361   unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; }
 362
 363   unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
 364
 365   unsigned getWideningBaseCost() const { return WideningBaseCost; }
 366
 367   /// CPU has TBI (top byte of addresses is ignored during HW address
 368   /// translation) and OS enables it.
 369   bool supportsAddressTopByteIgnored() const;
 370
 371   bool hasPerfMon() const { return HasPerfMon; }
 372   bool hasFullFP16() const { return HasFullFP16; }
 373   bool hasFP16FML() const { return HasFP16FML; }
 374   bool hasSPE() const { return HasSPE; }
 375   bool hasLSLFast() const { return HasLSLFast; }
 376   bool hasSVE() const { return HasSVE; }
 377   bool hasSVE2() const { return HasSVE2; }
 378   bool hasRCPC() const { return HasRCPC; }
 379   bool hasAggressiveFMA() const { return HasAggressiveFMA; }
 380   bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
 381   bool hasFRInt3264() const { return HasFRInt3264; }
 382   bool hasSpecRestrict() const { return HasSpecRestrict; }
 383   bool hasSSBS() const { return HasSSBS; }
 384   bool hasSB() const { return HasSB; }
 385   bool hasPredRes() const { return HasPredRes; }
 386   bool hasCCDP() const { return HasCCDP; }
 387   bool hasBTI() const { return HasBTI; }
 388   bool hasRandGen() const { return HasRandGen; }
 389   bool hasMTE() const { return HasMTE; }
 390   // Arm SVE2 extensions
 391   bool hasSVE2AES() const { return HasSVE2AES; }
 392   bool hasSVE2SM4() const { return HasSVE2SM4; }
 393   bool hasSVE2SHA3() const { return HasSVE2SHA3; }
 394   bool hasSVE2BitPerm() const { return HasSVE2BitPerm; }
 395
 396   bool isLittleEndian() const { return IsLittle; }
 397
 398   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
 399   bool isTargetIOS() const { return TargetTriple.isiOS(); }
 400   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
 401   bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
 402   bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
 403   bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
 404
 405   bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
 406   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
 407   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
 408
 409   bool useAA() const override { return UseAA; }
 410
 411   bool hasVH() const { return HasVH; }
 412   bool hasPAN() const { return HasPAN; }
 413   bool hasLOR() const { return HasLOR; }
 414
 415   bool hasPsUAO() const { return HasPsUAO; }
 416   bool hasPAN_RWV() const { return HasPAN_RWV; }
 417   bool hasCCPP() const { return HasCCPP; }
 418
 419   bool hasPA() const { return HasPA; }
 420   bool hasJS() const { return HasJS; }
 421   bool hasCCIDX() const { return HasCCIDX; }
 422   bool hasComplxNum() const { return HasComplxNum; }
 423
 424   bool hasNV() const { return HasNV; }
 425   bool hasRASv8_4() const { return HasRASv8_4; }
 426   bool hasMPAM() const { return HasMPAM; }
 427   bool hasDIT() const { return HasDIT; }
 428   bool hasTRACEV8_4() const { return HasTRACEV8_4; }
 429   bool hasAM() const { return HasAM; }
 430   bool hasSEL2() const { return HasSEL2; }
 431   bool hasTLB_RMI() const { return HasTLB_RMI; }
 432   bool hasFMI() const { return HasFMI; }
 433   bool hasRCPC_IMMO() const { return HasRCPC_IMMO; }
 434
 435   bool useSmallAddressing() const {
 436     switch (TLInfo.getTargetMachine().getCodeModel()) {
 437       case CodeModel::Kernel:
 438         // Kernel is currently allowed only for Fuchsia targets,
 439         // where it is the same as Small for almost all purposes.
 440       case CodeModel::Small:
 441         return true;
 442       default:
 443         return false;
 444     }
 445   }
 446
 447   /// ParseSubtargetFeatures - Parses features string setting specified
 448   /// subtarget options.  Definition of function is auto generated by tblgen.
 449   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 450
 451   /// ClassifyGlobalReference - Find the target operand flags that describe
 452   /// how a global value should be referenced for the current subtarget.
 453   unsigned char ClassifyGlobalReference(const GlobalValue *GV,
 454                                         const TargetMachine &TM) const;
 455
 456   unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
 457                                                 const TargetMachine &TM) const;
 458
 459   void overrideSchedPolicy(MachineSchedPolicy &Policy,
 460                            unsigned NumRegionInstrs) const override;
 461
 462   bool enableEarlyIfConversion() const override;
 463
 464   std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
 465
 466   bool isCallingConvWin64(CallingConv::ID CC) const {
 467     switch (CC) {
 468     case CallingConv::C:
 469     case CallingConv::Fast:
 470     case CallingConv::Swift:
 471       return isTargetWindows();
 472     case CallingConv::Win64:
 473       return true;
 474     default:
 475       return false;
 476     }
 477   }
 478
 479   void mirFileLoaded(MachineFunction &MF) const override;
 480 };
 481 } // End llvm namespace
 482
 483 #endif