lib/Target/AArch64/AArch64TargetMachine.cpp

   1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 //
  10 //===----------------------------------------------------------------------===//
  11
  12 #include "AArch64TargetMachine.h"
  13 #include "AArch64.h"
  14 #include "AArch64MacroFusion.h"
  15 #include "AArch64Subtarget.h"
  16 #include "AArch64TargetObjectFile.h"
  17 #include "AArch64TargetTransformInfo.h"
  18 #include "MCTargetDesc/AArch64MCTargetDesc.h"
  19 #include "TargetInfo/AArch64TargetInfo.h"
  20 #include "llvm/ADT/STLExtras.h"
  21 #include "llvm/ADT/Triple.h"
  22 #include "llvm/Analysis/TargetTransformInfo.h"
  23 #include "llvm/CodeGen/CSEConfigBase.h"
  24 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
  25 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
  26 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
  27 #include "llvm/CodeGen/GlobalISel/Localizer.h"
  28 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
  29 #include "llvm/CodeGen/MachineScheduler.h"
  30 #include "llvm/CodeGen/Passes.h"
  31 #include "llvm/CodeGen/TargetPassConfig.h"
  32 #include "llvm/IR/Attributes.h"
  33 #include "llvm/IR/Function.h"
  34 #include "llvm/MC/MCAsmInfo.h"
  35 #include "llvm/MC/MCTargetOptions.h"
  36 #include "llvm/Pass.h"
  37 #include "llvm/Support/CodeGen.h"
  38 #include "llvm/Support/CommandLine.h"
  39 #include "llvm/Support/TargetRegistry.h"
  40 #include "llvm/Target/TargetLoweringObjectFile.h"
  41 #include "llvm/Target/TargetOptions.h"
  42 #include "llvm/Transforms/Scalar.h"
  43 #include <memory>
  44 #include <string>
  45
  46 using namespace llvm;
  47
  48 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
  49                                 cl::desc("Enable the CCMP formation pass"),
  50                                 cl::init(true), cl::Hidden);
  51
  52 static cl::opt<bool>
  53     EnableCondBrTuning("aarch64-enable-cond-br-tune",
  54                        cl::desc("Enable the conditional branch tuning pass"),
  55                        cl::init(true), cl::Hidden);
  56
  57 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
  58                                cl::desc("Enable the machine combiner pass"),
  59                                cl::init(true), cl::Hidden);
  60
  61 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
  62                                           cl::desc("Suppress STP for AArch64"),
  63                                           cl::init(true), cl::Hidden);
  64
  65 static cl::opt<bool> EnableAdvSIMDScalar(
  66     "aarch64-enable-simd-scalar",
  67     cl::desc("Enable use of AdvSIMD scalar integer instructions"),
  68     cl::init(false), cl::Hidden);
  69
  70 static cl::opt<bool>
  71     EnablePromoteConstant("aarch64-enable-promote-const",
  72                           cl::desc("Enable the promote constant pass"),
  73                           cl::init(true), cl::Hidden);
  74
  75 static cl::opt<bool> EnableCollectLOH(
  76     "aarch64-enable-collect-loh",
  77     cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
  78     cl::init(true), cl::Hidden);
  79
  80 static cl::opt<bool>
  81     EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
  82                                   cl::desc("Enable the pass that removes dead"
  83                                            " definitons and replaces stores to"
  84                                            " them with stores to the zero"
  85                                            " register"),
  86                                   cl::init(true));
  87
  88 static cl::opt<bool> EnableRedundantCopyElimination(
  89     "aarch64-enable-copyelim",
  90     cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
  91     cl::Hidden);
  92
  93 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
  94                                         cl::desc("Enable the load/store pair"
  95                                                  " optimization pass"),
  96                                         cl::init(true), cl::Hidden);
  97
  98 static cl::opt<bool> EnableAtomicTidy(
  99     "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
 100     cl::desc("Run SimplifyCFG after expanding atomic operations"
 101              " to make use of cmpxchg flow-based information"),
 102     cl::init(true));
 103
 104 static cl::opt<bool>
 105 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
 106                         cl::desc("Run early if-conversion"),
 107                         cl::init(true));
 108
 109 static cl::opt<bool>
 110     EnableCondOpt("aarch64-enable-condopt",
 111                   cl::desc("Enable the condition optimizer pass"),
 112                   cl::init(true), cl::Hidden);
 113
 114 static cl::opt<bool>
 115 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
 116                 cl::desc("Work around Cortex-A53 erratum 835769"),
 117                 cl::init(false));
 118
 119 static cl::opt<bool>
 120     EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
 121                  cl::desc("Enable optimizations on complex GEPs"),
 122                  cl::init(false));
 123
 124 static cl::opt<bool>
 125     BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
 126                      cl::desc("Relax out of range conditional branches"));
 127
 128 static cl::opt<bool> EnableCompressJumpTables(
 129     "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
 130     cl::desc("Use smallest entry possible for jump tables"));
 131
 132 // FIXME: Unify control over GlobalMerge.
 133 static cl::opt<cl::boolOrDefault>
 134     EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
 135                       cl::desc("Enable the global merge pass"));
 136
 137 static cl::opt<bool>
 138     EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
 139                            cl::desc("Enable the loop data prefetch pass"),
 140                            cl::init(true));
 141
 142 static cl::opt<int> EnableGlobalISelAtO(
 143     "aarch64-enable-global-isel-at-O", cl::Hidden,
 144     cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
 145     cl::init(0));
 146
 147 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
 148                                          cl::init(true), cl::Hidden);
 149
 150 static cl::opt<bool>
 151     EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
 152                         cl::desc("Enable the AAcrh64 branch target pass"),
 153                         cl::init(true));
 154
 155 extern "C" void LLVMInitializeAArch64Target() {
 156   // Register the target.
 157   RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());
 158   RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());
 159   RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
 160   auto PR = PassRegistry::getPassRegistry();
 161   initializeGlobalISel(*PR);
 162   initializeAArch64A53Fix835769Pass(*PR);
 163   initializeAArch64A57FPLoadBalancingPass(*PR);
 164   initializeAArch64AdvSIMDScalarPass(*PR);
 165   initializeAArch64BranchTargetsPass(*PR);
 166   initializeAArch64CollectLOHPass(*PR);
 167   initializeAArch64CompressJumpTablesPass(*PR);
 168   initializeAArch64ConditionalComparesPass(*PR);
 169   initializeAArch64ConditionOptimizerPass(*PR);
 170   initializeAArch64DeadRegisterDefinitionsPass(*PR);
 171   initializeAArch64ExpandPseudoPass(*PR);
 172   initializeAArch64LoadStoreOptPass(*PR);
 173   initializeAArch64SIMDInstrOptPass(*PR);
 174   initializeAArch64PreLegalizerCombinerPass(*PR);
 175   initializeAArch64PromoteConstantPass(*PR);
 176   initializeAArch64RedundantCopyEliminationPass(*PR);
 177   initializeAArch64StorePairSuppressPass(*PR);
 178   initializeFalkorHWPFFixPass(*PR);
 179   initializeFalkorMarkStridedAccessesLegacyPass(*PR);
 180   initializeLDTLSCleanupPass(*PR);
 181   initializeAArch64SpeculationHardeningPass(*PR);
 182   initializeAArch64StackTaggingPass(*PR);
 183 }
 184
 185 //===----------------------------------------------------------------------===//
 186 // AArch64 Lowering public interface.
 187 //===----------------------------------------------------------------------===//
 188 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
 189   if (TT.isOSBinFormatMachO())
 190     return llvm::make_unique<AArch64_MachoTargetObjectFile>();
 191   if (TT.isOSBinFormatCOFF())
 192     return llvm::make_unique<AArch64_COFFTargetObjectFile>();
 193
 194   return llvm::make_unique<AArch64_ELFTargetObjectFile>();
 195 }
 196
 197 // Helper function to build a DataLayout string
 198 static std::string computeDataLayout(const Triple &TT,
 199                                      const MCTargetOptions &Options,
 200                                      bool LittleEndian) {
 201   if (Options.getABIName() == "ilp32")
 202     return "e-m:e-p:32:32-i8:8-i16:16-i64:64-S128";
 203   if (TT.isOSBinFormatMachO())
 204     return "e-m:o-i64:64-i128:128-n32:64-S128";
 205   if (TT.isOSBinFormatCOFF())
 206     return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
 207   if (LittleEndian)
 208     return "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
 209   return "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
 210 }
 211
 212 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
 213                                            Optional<Reloc::Model> RM) {
 214   // AArch64 Darwin and Windows are always PIC.
 215   if (TT.isOSDarwin() || TT.isOSWindows())
 216     return Reloc::PIC_;
 217   // On ELF platforms the default static relocation model has a smart enough
 218   // linker to cope with referencing external symbols defined in a shared
 219   // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
 220   if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
 221     return Reloc::Static;
 222   return *RM;
 223 }
 224
 225 static CodeModel::Model
 226 getEffectiveAArch64CodeModel(const Triple &TT, Optional<CodeModel::Model> CM,
 227                              bool JIT) {
 228   if (CM) {
 229     if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
 230         *CM != CodeModel::Large) {
 231       if (!TT.isOSFuchsia())
 232         report_fatal_error(
 233             "Only small, tiny and large code models are allowed on AArch64");
 234       else if (*CM != CodeModel::Kernel)
 235         report_fatal_error("Only small, tiny, kernel, and large code models "
 236                            "are allowed on AArch64");
 237     } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
 238       report_fatal_error("tiny code model is only supported on ELF");
 239     return *CM;
 240   }
 241   // The default MCJIT memory managers make no guarantees about where they can
 242   // find an executable page; JITed code needs to be able to refer to globals
 243   // no matter how far away they are.
 244   if (JIT)
 245     return CodeModel::Large;
 246   return CodeModel::Small;
 247 }
 248
 249 /// Create an AArch64 architecture model.
 250 ///
 251 AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
 252                                            StringRef CPU, StringRef FS,
 253                                            const TargetOptions &Options,
 254                                            Optional<Reloc::Model> RM,
 255                                            Optional<CodeModel::Model> CM,
 256                                            CodeGenOpt::Level OL, bool JIT,
 257                                            bool LittleEndian)
 258     : LLVMTargetMachine(T,
 259                         computeDataLayout(TT, Options.MCOptions, LittleEndian),
 260                         TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM),
 261                         getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
 262       TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
 263   initAsmInfo();
 264
 265   if (TT.isOSBinFormatMachO()) {
 266     this->Options.TrapUnreachable = true;
 267     this->Options.NoTrapAfterNoreturn = true;
 268   }
 269
 270   if (getMCAsmInfo()->usesWindowsCFI()) {
 271     // Unwinding can get confused if the last instruction in an
 272     // exception-handling region (function, funclet, try block, etc.)
 273     // is a call.
 274     //
 275     // FIXME: We could elide the trap if the next instruction would be in
 276     // the same region anyway.
 277     this->Options.TrapUnreachable = true;
 278   }
 279
 280   // Enable GlobalISel at or below EnableGlobalISelAt0.
 281   if (getOptLevel() <= EnableGlobalISelAtO) {
 282     setGlobalISel(true);
 283     setGlobalISelAbort(GlobalISelAbortMode::Disable);
 284   }
 285
 286   // AArch64 supports the MachineOutliner.
 287   setMachineOutliner(true);
 288
 289   // AArch64 supports default outlining behaviour.
 290   setSupportsDefaultOutlining(true);
 291 }
 292
 293 AArch64TargetMachine::~AArch64TargetMachine() = default;
 294
 295 const AArch64Subtarget *
 296 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
 297   Attribute CPUAttr = F.getFnAttribute("target-cpu");
 298   Attribute FSAttr = F.getFnAttribute("target-features");
 299
 300   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
 301                         ? CPUAttr.getValueAsString().str()
 302                         : TargetCPU;
 303   std::string FS = !FSAttr.hasAttribute(Attribute::None)
 304                        ? FSAttr.getValueAsString().str()
 305                        : TargetFS;
 306
 307   auto &I = SubtargetMap[CPU + FS];
 308   if (!I) {
 309     // This needs to be done before we create a new subtarget since any
 310     // creation will depend on the TM and the code generation flags on the
 311     // function that reside in TargetOptions.
 312     resetTargetOptions(F);
 313     I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
 314                                             isLittle);
 315   }
 316   return I.get();
 317 }
 318
 319 void AArch64leTargetMachine::anchor() { }
 320
 321 AArch64leTargetMachine::AArch64leTargetMachine(
 322     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
 323     const TargetOptions &Options, Optional<Reloc::Model> RM,
 324     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
 325     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
 326
 327 void AArch64beTargetMachine::anchor() { }
 328
 329 AArch64beTargetMachine::AArch64beTargetMachine(
 330     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
 331     const TargetOptions &Options, Optional<Reloc::Model> RM,
 332     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
 333     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
 334
 335 namespace {
 336
 337 /// AArch64 Code Generator Pass Configuration Options.
 338 class AArch64PassConfig : public TargetPassConfig {
 339 public:
 340   AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
 341       : TargetPassConfig(TM, PM) {
 342     if (TM.getOptLevel() != CodeGenOpt::None)
 343       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
 344   }
 345
 346   AArch64TargetMachine &getAArch64TargetMachine() const {
 347     return getTM<AArch64TargetMachine>();
 348   }
 349
 350   ScheduleDAGInstrs *
 351   createMachineScheduler(MachineSchedContext *C) const override {
 352     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
 353     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
 354     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
 355     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
 356     if (ST.hasFusion())
 357       DAG->addMutation(createAArch64MacroFusionDAGMutation());
 358     return DAG;
 359   }
 360
 361   ScheduleDAGInstrs *
 362   createPostMachineScheduler(MachineSchedContext *C) const override {
 363     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
 364     if (ST.hasFusion()) {
 365       // Run the Macro Fusion after RA again since literals are expanded from
 366       // pseudos then (v. addPreSched2()).
 367       ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
 368       DAG->addMutation(createAArch64MacroFusionDAGMutation());
 369       return DAG;
 370     }
 371
 372     return nullptr;
 373   }
 374
 375   void addIRPasses()  override;
 376   bool addPreISel() override;
 377   bool addInstSelector() override;
 378   bool addIRTranslator() override;
 379   void addPreLegalizeMachineIR() override;
 380   bool addLegalizeMachineIR() override;
 381   bool addRegBankSelect() override;
 382   void addPreGlobalInstructionSelect() override;
 383   bool addGlobalInstructionSelect() override;
 384   bool addILPOpts() override;
 385   void addPreRegAlloc() override;
 386   void addPostRegAlloc() override;
 387   void addPreSched2() override;
 388   void addPreEmitPass() override;
 389
 390   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
 391 };
 392
 393 } // end anonymous namespace
 394
 395 TargetTransformInfo
 396 AArch64TargetMachine::getTargetTransformInfo(const Function &F) {
 397   return TargetTransformInfo(AArch64TTIImpl(this, F));
 398 }
 399
 400 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
 401   return new AArch64PassConfig(*this, PM);
 402 }
 403
 404 std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const {
 405   return getStandardCSEConfigForOpt(TM->getOptLevel());
 406 }
 407
 408 void AArch64PassConfig::addIRPasses() {
 409   // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
 410   // ourselves.
 411   addPass(createAtomicExpandPass());
 412
 413   // Cmpxchg instructions are often used with a subsequent comparison to
 414   // determine whether it succeeded. We can exploit existing control-flow in
 415   // ldrex/strex loops to simplify this, but it needs tidying up.
 416   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
 417     addPass(createCFGSimplificationPass(1, true, true, false, true));
 418
 419   // Run LoopDataPrefetch
 420   //
 421   // Run this before LSR to remove the multiplies involved in computing the
 422   // pointer values N iterations ahead.
 423   if (TM->getOptLevel() != CodeGenOpt::None) {
 424     if (EnableLoopDataPrefetch)
 425       addPass(createLoopDataPrefetchPass());
 426     if (EnableFalkorHWPFFix)
 427       addPass(createFalkorMarkStridedAccessesPass());
 428   }
 429
 430   TargetPassConfig::addIRPasses();
 431
 432   // Match interleaved memory accesses to ldN/stN intrinsics.
 433   if (TM->getOptLevel() != CodeGenOpt::None) {
 434     addPass(createInterleavedLoadCombinePass());
 435     addPass(createInterleavedAccessPass());
 436   }
 437
 438   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
 439     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
 440     // and lower a GEP with multiple indices to either arithmetic operations or
 441     // multiple GEPs with single index.
 442     addPass(createSeparateConstOffsetFromGEPPass(true));
 443     // Call EarlyCSE pass to find and remove subexpressions in the lowered
 444     // result.
 445     addPass(createEarlyCSEPass());
 446     // Do loop invariant code motion in case part of the lowered result is
 447     // invariant.
 448     addPass(createLICMPass());
 449   }
 450
 451   addPass(createAArch64StackTaggingPass());
 452 }
 453
 454 // Pass Pipeline Configuration
 455 bool AArch64PassConfig::addPreISel() {
 456   // Run promote constant before global merge, so that the promoted constants
 457   // get a chance to be merged
 458   if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
 459     addPass(createAArch64PromoteConstantPass());
 460   // FIXME: On AArch64, this depends on the type.
 461   // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
 462   // and the offset has to be a multiple of the related size in bytes.
 463   if ((TM->getOptLevel() != CodeGenOpt::None &&
 464        EnableGlobalMerge == cl::BOU_UNSET) ||
 465       EnableGlobalMerge == cl::BOU_TRUE) {
 466     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
 467                                (EnableGlobalMerge == cl::BOU_UNSET);
 468
 469     // Merging of extern globals is enabled by default on non-Mach-O as we
 470     // expect it to be generally either beneficial or harmless. On Mach-O it
 471     // is disabled as we emit the .subsections_via_symbols directive which
 472     // means that merging extern globals is not safe.
 473     bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
 474
 475     // FIXME: extern global merging is only enabled when we optimise for size
 476     // because there are some regressions with it also enabled for performance.
 477     if (!OnlyOptimizeForSize)
 478       MergeExternalByDefault = false;
 479
 480     addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize,
 481                                   MergeExternalByDefault));
 482   }
 483
 484   return false;
 485 }
 486
 487 bool AArch64PassConfig::addInstSelector() {
 488   addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
 489
 490   // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
 491   // references to _TLS_MODULE_BASE_ as possible.
 492   if (TM->getTargetTriple().isOSBinFormatELF() &&
 493       getOptLevel() != CodeGenOpt::None)
 494     addPass(createAArch64CleanupLocalDynamicTLSPass());
 495
 496   return false;
 497 }
 498
 499 bool AArch64PassConfig::addIRTranslator() {
 500   addPass(new IRTranslator());
 501   return false;
 502 }
 503
 504 void AArch64PassConfig::addPreLegalizeMachineIR() {
 505   addPass(createAArch64PreLegalizeCombiner());
 506 }
 507
 508 bool AArch64PassConfig::addLegalizeMachineIR() {
 509   addPass(new Legalizer());
 510   return false;
 511 }
 512
 513 bool AArch64PassConfig::addRegBankSelect() {
 514   addPass(new RegBankSelect());
 515   return false;
 516 }
 517
 518 void AArch64PassConfig::addPreGlobalInstructionSelect() {
 519   // Workaround the deficiency of the fast register allocator.
 520   if (TM->getOptLevel() == CodeGenOpt::None)
 521     addPass(new Localizer());
 522 }
 523
 524 bool AArch64PassConfig::addGlobalInstructionSelect() {
 525   addPass(new InstructionSelect());
 526   return false;
 527 }
 528
 529 bool AArch64PassConfig::addILPOpts() {
 530   if (EnableCondOpt)
 531     addPass(createAArch64ConditionOptimizerPass());
 532   if (EnableCCMP)
 533     addPass(createAArch64ConditionalCompares());
 534   if (EnableMCR)
 535     addPass(&MachineCombinerID);
 536   if (EnableCondBrTuning)
 537     addPass(createAArch64CondBrTuning());
 538   if (EnableEarlyIfConversion)
 539     addPass(&EarlyIfConverterID);
 540   if (EnableStPairSuppress)
 541     addPass(createAArch64StorePairSuppressPass());
 542   addPass(createAArch64SIMDInstrOptPass());
 543   return true;
 544 }
 545
 546 void AArch64PassConfig::addPreRegAlloc() {
 547   // Change dead register definitions to refer to the zero register.
 548   if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
 549     addPass(createAArch64DeadRegisterDefinitions());
 550
 551   // Use AdvSIMD scalar instructions whenever profitable.
 552   if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
 553     addPass(createAArch64AdvSIMDScalar());
 554     // The AdvSIMD pass may produce copies that can be rewritten to
 555     // be register coaleascer friendly.
 556     addPass(&PeepholeOptimizerID);
 557   }
 558 }
 559
 560 void AArch64PassConfig::addPostRegAlloc() {
 561   // Remove redundant copy instructions.
 562   if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
 563     addPass(createAArch64RedundantCopyEliminationPass());
 564
 565   if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
 566     // Improve performance for some FP/SIMD code for A57.
 567     addPass(createAArch64A57FPLoadBalancing());
 568 }
 569
 570 void AArch64PassConfig::addPreSched2() {
 571   // Expand some pseudo instructions to allow proper scheduling.
 572   addPass(createAArch64ExpandPseudoPass());
 573   // Use load/store pair instructions when possible.
 574   if (TM->getOptLevel() != CodeGenOpt::None) {
 575     if (EnableLoadStoreOpt)
 576       addPass(createAArch64LoadStoreOptimizationPass());
 577   }
 578
 579   // The AArch64SpeculationHardeningPass destroys dominator tree and natural
 580   // loop info, which is needed for the FalkorHWPFFixPass and also later on.
 581   // Therefore, run the AArch64SpeculationHardeningPass before the
 582   // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop
 583   // info.
 584   addPass(createAArch64SpeculationHardeningPass());
 585
 586   if (TM->getOptLevel() != CodeGenOpt::None) {
 587     if (EnableFalkorHWPFFix)
 588       addPass(createFalkorHWPFFixPass());
 589   }
 590 }
 591
 592 void AArch64PassConfig::addPreEmitPass() {
 593   // Machine Block Placement might have created new opportunities when run
 594   // at O3, where the Tail Duplication Threshold is set to 4 instructions.
 595   // Run the load/store optimizer once more.
 596   if (TM->getOptLevel() >= CodeGenOpt::Aggressive && EnableLoadStoreOpt)
 597     addPass(createAArch64LoadStoreOptimizationPass());
 598
 599   if (EnableA53Fix835769)
 600     addPass(createAArch64A53Fix835769());
 601   // Relax conditional branch instructions if they're otherwise out of
 602   // range of their destination.
 603   if (BranchRelaxation)
 604     addPass(&BranchRelaxationPassID);
 605
 606   if (EnableBranchTargets)
 607     addPass(createAArch64BranchTargetsPass());
 608
 609   if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables)
 610     addPass(createAArch64CompressJumpTablesPass());
 611
 612   if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
 613       TM->getTargetTriple().isOSBinFormatMachO())
 614     addPass(createAArch64CollectLOHPass());
 615 }