lib/Target/AMDGPU/SILowerControlFlow.cpp

   1 //===-- SILowerControlFlow.cpp - Use predicates for control flow ----------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 /// \file
  10 /// This pass lowers the pseudo control flow instructions to real
  11 /// machine instructions.
  12 ///
  13 /// All control flow is handled using predicated instructions and
  14 /// a predicate stack.  Each Scalar ALU controls the operations of 64 Vector
  15 /// ALUs.  The Scalar ALU can update the predicate for any of the Vector ALUs
  16 /// by writting to the 64-bit EXEC register (each bit corresponds to a
  17 /// single vector ALU).  Typically, for predicates, a vector ALU will write
  18 /// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each
  19 /// Vector ALU) and then the ScalarALU will AND the VCC register with the
  20 /// EXEC to update the predicates.
  21 ///
  22 /// For example:
  23 /// %vcc = V_CMP_GT_F32 %vgpr1, %vgpr2
  24 /// %sgpr0 = SI_IF %vcc
  25 ///   %vgpr0 = V_ADD_F32 %vgpr0, %vgpr0
  26 /// %sgpr0 = SI_ELSE %sgpr0
  27 ///   %vgpr0 = V_SUB_F32 %vgpr0, %vgpr0
  28 /// SI_END_CF %sgpr0
  29 ///
  30 /// becomes:
  31 ///
  32 /// %sgpr0 = S_AND_SAVEEXEC_B64 %vcc  // Save and update the exec mask
  33 /// %sgpr0 = S_XOR_B64 %sgpr0, %exec  // Clear live bits from saved exec mask
  34 /// S_CBRANCH_EXECZ label0            // This instruction is an optional
  35 ///                                   // optimization which allows us to
  36 ///                                   // branch if all the bits of
  37 ///                                   // EXEC are zero.
  38 /// %vgpr0 = V_ADD_F32 %vgpr0, %vgpr0 // Do the IF block of the branch
  39 ///
  40 /// label0:
  41 /// %sgpr0 = S_OR_SAVEEXEC_B64 %exec   // Restore the exec mask for the Then block
  42 /// %exec = S_XOR_B64 %sgpr0, %exec    // Clear live bits from saved exec mask
  43 /// S_BRANCH_EXECZ label1              // Use our branch optimization
  44 ///                                    // instruction again.
  45 /// %vgpr0 = V_SUB_F32 %vgpr0, %vgpr   // Do the THEN block
  46 /// label1:
  47 /// %exec = S_OR_B64 %exec, %sgpr0     // Re-enable saved exec mask bits
  48 //===----------------------------------------------------------------------===//
  49
  50 #include "AMDGPU.h"
  51 #include "AMDGPUSubtarget.h"
  52 #include "SIInstrInfo.h"
  53 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
  54 #include "llvm/ADT/SmallVector.h"
  55 #include "llvm/ADT/StringRef.h"
  56 #include "llvm/CodeGen/LiveIntervals.h"
  57 #include "llvm/CodeGen/MachineBasicBlock.h"
  58 #include "llvm/CodeGen/MachineFunction.h"
  59 #include "llvm/CodeGen/MachineFunctionPass.h"
  60 #include "llvm/CodeGen/MachineInstr.h"
  61 #include "llvm/CodeGen/MachineInstrBuilder.h"
  62 #include "llvm/CodeGen/MachineOperand.h"
  63 #include "llvm/CodeGen/MachineRegisterInfo.h"
  64 #include "llvm/CodeGen/Passes.h"
  65 #include "llvm/CodeGen/SlotIndexes.h"
  66 #include "llvm/CodeGen/TargetRegisterInfo.h"
  67 #include "llvm/MC/MCRegisterInfo.h"
  68 #include "llvm/Pass.h"
  69 #include <cassert>
  70 #include <iterator>
  71
  72 using namespace llvm;
  73
  74 #define DEBUG_TYPE "si-lower-control-flow"
  75
  76 namespace {
  77
  78 class SILowerControlFlow : public MachineFunctionPass {
  79 private:
  80   const SIRegisterInfo *TRI = nullptr;
  81   const SIInstrInfo *TII = nullptr;
  82   LiveIntervals *LIS = nullptr;
  83   MachineRegisterInfo *MRI = nullptr;
  84
  85   const TargetRegisterClass *BoolRC = nullptr;
  86   unsigned AndOpc;
  87   unsigned OrOpc;
  88   unsigned XorOpc;
  89   unsigned MovTermOpc;
  90   unsigned Andn2TermOpc;
  91   unsigned XorTermrOpc;
  92   unsigned OrSaveExecOpc;
  93   unsigned Exec;
  94
  95   void emitIf(MachineInstr &MI);
  96   void emitElse(MachineInstr &MI);
  97   void emitIfBreak(MachineInstr &MI);
  98   void emitLoop(MachineInstr &MI);
  99   void emitEndCf(MachineInstr &MI);
 100
 101   void findMaskOperands(MachineInstr &MI, unsigned OpNo,
 102                         SmallVectorImpl<MachineOperand> &Src) const;
 103
 104   void combineMasks(MachineInstr &MI);
 105
 106 public:
 107   static char ID;
 108
 109   SILowerControlFlow() : MachineFunctionPass(ID) {}
 110
 111   bool runOnMachineFunction(MachineFunction &MF) override;
 112
 113   StringRef getPassName() const override {
 114     return "SI Lower control flow pseudo instructions";
 115   }
 116
 117   void getAnalysisUsage(AnalysisUsage &AU) const override {
 118     // Should preserve the same set that TwoAddressInstructions does.
 119     AU.addPreserved<SlotIndexes>();
 120     AU.addPreserved<LiveIntervals>();
 121     AU.addPreservedID(LiveVariablesID);
 122     AU.addPreservedID(MachineLoopInfoID);
 123     AU.addPreservedID(MachineDominatorsID);
 124     AU.setPreservesCFG();
 125     MachineFunctionPass::getAnalysisUsage(AU);
 126   }
 127 };
 128
 129 } // end anonymous namespace
 130
 131 char SILowerControlFlow::ID = 0;
 132
 133 INITIALIZE_PASS(SILowerControlFlow, DEBUG_TYPE,
 134                "SI lower control flow", false, false)
 135
 136 static void setImpSCCDefDead(MachineInstr &MI, bool IsDead) {
 137   MachineOperand &ImpDefSCC = MI.getOperand(3);
 138   assert(ImpDefSCC.getReg() == AMDGPU::SCC && ImpDefSCC.isDef());
 139
 140   ImpDefSCC.setIsDead(IsDead);
 141 }
 142
 143 char &llvm::SILowerControlFlowID = SILowerControlFlow::ID;
 144
 145 static bool isSimpleIf(const MachineInstr &MI, const MachineRegisterInfo *MRI,
 146                        const SIInstrInfo *TII) {
 147   unsigned SaveExecReg = MI.getOperand(0).getReg();
 148   auto U = MRI->use_instr_nodbg_begin(SaveExecReg);
 149
 150   if (U == MRI->use_instr_nodbg_end() ||
 151       std::next(U) != MRI->use_instr_nodbg_end() ||
 152       U->getOpcode() != AMDGPU::SI_END_CF)
 153     return false;
 154
 155   // Check for SI_KILL_*_TERMINATOR on path from if to endif.
 156   // if there is any such terminator simplififcations are not safe.
 157   auto SMBB = MI.getParent();
 158   auto EMBB = U->getParent();
 159   DenseSet<const MachineBasicBlock*> Visited;
 160   SmallVector<MachineBasicBlock*, 4> Worklist(SMBB->succ_begin(),
 161                                               SMBB->succ_end());
 162
 163   while (!Worklist.empty()) {
 164     MachineBasicBlock *MBB = Worklist.pop_back_val();
 165
 166     if (MBB == EMBB || !Visited.insert(MBB).second)
 167       continue;
 168     for(auto &Term : MBB->terminators())
 169       if (TII->isKillTerminator(Term.getOpcode()))
 170         return false;
 171
 172     Worklist.append(MBB->succ_begin(), MBB->succ_end());
 173   }
 174
 175   return true;
 176 }
 177
 178 void SILowerControlFlow::emitIf(MachineInstr &MI) {
 179   MachineBasicBlock &MBB = *MI.getParent();
 180   const DebugLoc &DL = MI.getDebugLoc();
 181   MachineBasicBlock::iterator I(&MI);
 182
 183   MachineOperand &SaveExec = MI.getOperand(0);
 184   MachineOperand &Cond = MI.getOperand(1);
 185   assert(SaveExec.getSubReg() == AMDGPU::NoSubRegister &&
 186          Cond.getSubReg() == AMDGPU::NoSubRegister);
 187
 188   Register SaveExecReg = SaveExec.getReg();
 189
 190   MachineOperand &ImpDefSCC = MI.getOperand(4);
 191   assert(ImpDefSCC.getReg() == AMDGPU::SCC && ImpDefSCC.isDef());
 192
 193   // If there is only one use of save exec register and that use is SI_END_CF,
 194   // we can optimize SI_IF by returning the full saved exec mask instead of
 195   // just cleared bits.
 196   bool SimpleIf = isSimpleIf(MI, MRI, TII);
 197
 198   // Add an implicit def of exec to discourage scheduling VALU after this which
 199   // will interfere with trying to form s_and_saveexec_b64 later.
 200   Register CopyReg = SimpleIf ? SaveExecReg
 201                        : MRI->createVirtualRegister(BoolRC);
 202   MachineInstr *CopyExec =
 203     BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), CopyReg)
 204     .addReg(Exec)
 205     .addReg(Exec, RegState::ImplicitDefine);
 206
 207   unsigned Tmp = MRI->createVirtualRegister(BoolRC);
 208
 209   MachineInstr *And =
 210     BuildMI(MBB, I, DL, TII->get(AndOpc), Tmp)
 211     .addReg(CopyReg)
 212     .add(Cond);
 213
 214   setImpSCCDefDead(*And, true);
 215
 216   MachineInstr *Xor = nullptr;
 217   if (!SimpleIf) {
 218     Xor =
 219       BuildMI(MBB, I, DL, TII->get(XorOpc), SaveExecReg)
 220       .addReg(Tmp)
 221       .addReg(CopyReg);
 222     setImpSCCDefDead(*Xor, ImpDefSCC.isDead());
 223   }
 224
 225   // Use a copy that is a terminator to get correct spill code placement it with
 226   // fast regalloc.
 227   MachineInstr *SetExec =
 228     BuildMI(MBB, I, DL, TII->get(MovTermOpc), Exec)
 229     .addReg(Tmp, RegState::Kill);
 230
 231   // Insert a pseudo terminator to help keep the verifier happy. This will also
 232   // be used later when inserting skips.
 233   MachineInstr *NewBr = BuildMI(MBB, I, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
 234                             .add(MI.getOperand(2));
 235
 236   if (!LIS) {
 237     MI.eraseFromParent();
 238     return;
 239   }
 240
 241   LIS->InsertMachineInstrInMaps(*CopyExec);
 242
 243   // Replace with and so we don't need to fix the live interval for condition
 244   // register.
 245   LIS->ReplaceMachineInstrInMaps(MI, *And);
 246
 247   if (!SimpleIf)
 248     LIS->InsertMachineInstrInMaps(*Xor);
 249   LIS->InsertMachineInstrInMaps(*SetExec);
 250   LIS->InsertMachineInstrInMaps(*NewBr);
 251
 252   LIS->removeAllRegUnitsForPhysReg(AMDGPU::EXEC);
 253   MI.eraseFromParent();
 254
 255   // FIXME: Is there a better way of adjusting the liveness? It shouldn't be
 256   // hard to add another def here but I'm not sure how to correctly update the
 257   // valno.
 258   LIS->removeInterval(SaveExecReg);
 259   LIS->createAndComputeVirtRegInterval(SaveExecReg);
 260   LIS->createAndComputeVirtRegInterval(Tmp);
 261   if (!SimpleIf)
 262     LIS->createAndComputeVirtRegInterval(CopyReg);
 263 }
 264
 265 void SILowerControlFlow::emitElse(MachineInstr &MI) {
 266   MachineBasicBlock &MBB = *MI.getParent();
 267   const DebugLoc &DL = MI.getDebugLoc();
 268
 269   Register DstReg = MI.getOperand(0).getReg();
 270   assert(MI.getOperand(0).getSubReg() == AMDGPU::NoSubRegister);
 271
 272   bool ExecModified = MI.getOperand(3).getImm() != 0;
 273   MachineBasicBlock::iterator Start = MBB.begin();
 274
 275   // We are running before TwoAddressInstructions, and si_else's operands are
 276   // tied. In order to correctly tie the registers, split this into a copy of
 277   // the src like it does.
 278   Register CopyReg = MRI->createVirtualRegister(BoolRC);
 279   MachineInstr *CopyExec =
 280     BuildMI(MBB, Start, DL, TII->get(AMDGPU::COPY), CopyReg)
 281       .add(MI.getOperand(1)); // Saved EXEC
 282
 283   // This must be inserted before phis and any spill code inserted before the
 284   // else.
 285   Register SaveReg = ExecModified ?
 286     MRI->createVirtualRegister(BoolRC) : DstReg;
 287   MachineInstr *OrSaveExec =
 288     BuildMI(MBB, Start, DL, TII->get(OrSaveExecOpc), SaveReg)
 289     .addReg(CopyReg);
 290
 291   MachineBasicBlock *DestBB = MI.getOperand(2).getMBB();
 292
 293   MachineBasicBlock::iterator ElsePt(MI);
 294
 295   if (ExecModified) {
 296     MachineInstr *And =
 297       BuildMI(MBB, ElsePt, DL, TII->get(AndOpc), DstReg)
 298       .addReg(Exec)
 299       .addReg(SaveReg);
 300
 301     if (LIS)
 302       LIS->InsertMachineInstrInMaps(*And);
 303   }
 304
 305   MachineInstr *Xor =
 306     BuildMI(MBB, ElsePt, DL, TII->get(XorTermrOpc), Exec)
 307     .addReg(Exec)
 308     .addReg(DstReg);
 309
 310   MachineInstr *Branch =
 311     BuildMI(MBB, ElsePt, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
 312     .addMBB(DestBB);
 313
 314   if (!LIS) {
 315     MI.eraseFromParent();
 316     return;
 317   }
 318
 319   LIS->RemoveMachineInstrFromMaps(MI);
 320   MI.eraseFromParent();
 321
 322   LIS->InsertMachineInstrInMaps(*CopyExec);
 323   LIS->InsertMachineInstrInMaps(*OrSaveExec);
 324
 325   LIS->InsertMachineInstrInMaps(*Xor);
 326   LIS->InsertMachineInstrInMaps(*Branch);
 327
 328   // src reg is tied to dst reg.
 329   LIS->removeInterval(DstReg);
 330   LIS->createAndComputeVirtRegInterval(DstReg);
 331   LIS->createAndComputeVirtRegInterval(CopyReg);
 332   if (ExecModified)
 333     LIS->createAndComputeVirtRegInterval(SaveReg);
 334
 335   // Let this be recomputed.
 336   LIS->removeAllRegUnitsForPhysReg(AMDGPU::EXEC);
 337 }
 338
 339 void SILowerControlFlow::emitIfBreak(MachineInstr &MI) {
 340   MachineBasicBlock &MBB = *MI.getParent();
 341   const DebugLoc &DL = MI.getDebugLoc();
 342   auto Dst = MI.getOperand(0).getReg();
 343
 344   // Skip ANDing with exec if the break condition is already masked by exec
 345   // because it is a V_CMP in the same basic block. (We know the break
 346   // condition operand was an i1 in IR, so if it is a VALU instruction it must
 347   // be one with a carry-out.)
 348   bool SkipAnding = false;
 349   if (MI.getOperand(1).isReg()) {
 350     if (MachineInstr *Def = MRI->getUniqueVRegDef(MI.getOperand(1).getReg())) {
 351       SkipAnding = Def->getParent() == MI.getParent()
 352           && SIInstrInfo::isVALU(*Def);
 353     }
 354   }
 355
 356   // AND the break condition operand with exec, then OR that into the "loop
 357   // exit" mask.
 358   MachineInstr *And = nullptr, *Or = nullptr;
 359   if (!SkipAnding) {
 360     And = BuildMI(MBB, &MI, DL, TII->get(AndOpc), Dst)
 361              .addReg(Exec)
 362              .add(MI.getOperand(1));
 363     Or = BuildMI(MBB, &MI, DL, TII->get(OrOpc), Dst)
 364              .addReg(Dst)
 365              .add(MI.getOperand(2));
 366   } else
 367     Or = BuildMI(MBB, &MI, DL, TII->get(OrOpc), Dst)
 368              .add(MI.getOperand(1))
 369              .add(MI.getOperand(2));
 370
 371   if (LIS) {
 372     if (And)
 373       LIS->InsertMachineInstrInMaps(*And);
 374     LIS->ReplaceMachineInstrInMaps(MI, *Or);
 375   }
 376
 377   MI.eraseFromParent();
 378 }
 379
 380 void SILowerControlFlow::emitLoop(MachineInstr &MI) {
 381   MachineBasicBlock &MBB = *MI.getParent();
 382   const DebugLoc &DL = MI.getDebugLoc();
 383
 384   MachineInstr *AndN2 =
 385       BuildMI(MBB, &MI, DL, TII->get(Andn2TermOpc), Exec)
 386           .addReg(Exec)
 387           .add(MI.getOperand(0));
 388
 389   MachineInstr *Branch =
 390       BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
 391           .add(MI.getOperand(1));
 392
 393   if (LIS) {
 394     LIS->ReplaceMachineInstrInMaps(MI, *AndN2);
 395     LIS->InsertMachineInstrInMaps(*Branch);
 396   }
 397
 398   MI.eraseFromParent();
 399 }
 400
 401 void SILowerControlFlow::emitEndCf(MachineInstr &MI) {
 402   MachineBasicBlock &MBB = *MI.getParent();
 403   const DebugLoc &DL = MI.getDebugLoc();
 404
 405   MachineBasicBlock::iterator InsPt = MBB.begin();
 406   MachineInstr *NewMI =
 407       BuildMI(MBB, InsPt, DL, TII->get(OrOpc), Exec)
 408           .addReg(Exec)
 409           .add(MI.getOperand(0));
 410
 411   if (LIS)
 412     LIS->ReplaceMachineInstrInMaps(MI, *NewMI);
 413
 414   MI.eraseFromParent();
 415
 416   if (LIS)
 417     LIS->handleMove(*NewMI);
 418 }
 419
 420 // Returns replace operands for a logical operation, either single result
 421 // for exec or two operands if source was another equivalent operation.
 422 void SILowerControlFlow::findMaskOperands(MachineInstr &MI, unsigned OpNo,
 423        SmallVectorImpl<MachineOperand> &Src) const {
 424   MachineOperand &Op = MI.getOperand(OpNo);
 425   if (!Op.isReg() || !TargetRegisterInfo::isVirtualRegister(Op.getReg())) {
 426     Src.push_back(Op);
 427     return;
 428   }
 429
 430   MachineInstr *Def = MRI->getUniqueVRegDef(Op.getReg());
 431   if (!Def || Def->getParent() != MI.getParent() ||
 432       !(Def->isFullCopy() || (Def->getOpcode() == MI.getOpcode())))
 433     return;
 434
 435   // Make sure we do not modify exec between def and use.
 436   // A copy with implcitly defined exec inserted earlier is an exclusion, it
 437   // does not really modify exec.
 438   for (auto I = Def->getIterator(); I != MI.getIterator(); ++I)
 439     if (I->modifiesRegister(AMDGPU::EXEC, TRI) &&
 440         !(I->isCopy() && I->getOperand(0).getReg() != Exec))
 441       return;
 442
 443   for (const auto &SrcOp : Def->explicit_operands())
 444     if (SrcOp.isReg() && SrcOp.isUse() &&
 445         (TargetRegisterInfo::isVirtualRegister(SrcOp.getReg()) ||
 446         SrcOp.getReg() == Exec))
 447       Src.push_back(SrcOp);
 448 }
 449
 450 // Search and combine pairs of equivalent instructions, like
 451 // S_AND_B64 x, (S_AND_B64 x, y) => S_AND_B64 x, y
 452 // S_OR_B64  x, (S_OR_B64  x, y) => S_OR_B64  x, y
 453 // One of the operands is exec mask.
 454 void SILowerControlFlow::combineMasks(MachineInstr &MI) {
 455   assert(MI.getNumExplicitOperands() == 3);
 456   SmallVector<MachineOperand, 4> Ops;
 457   unsigned OpToReplace = 1;
 458   findMaskOperands(MI, 1, Ops);
 459   if (Ops.size() == 1) OpToReplace = 2; // First operand can be exec or its copy
 460   findMaskOperands(MI, 2, Ops);
 461   if (Ops.size() != 3) return;
 462
 463   unsigned UniqueOpndIdx;
 464   if (Ops[0].isIdenticalTo(Ops[1])) UniqueOpndIdx = 2;
 465   else if (Ops[0].isIdenticalTo(Ops[2])) UniqueOpndIdx = 1;
 466   else if (Ops[1].isIdenticalTo(Ops[2])) UniqueOpndIdx = 1;
 467   else return;
 468
 469   unsigned Reg = MI.getOperand(OpToReplace).getReg();
 470   MI.RemoveOperand(OpToReplace);
 471   MI.addOperand(Ops[UniqueOpndIdx]);
 472   if (MRI->use_empty(Reg))
 473     MRI->getUniqueVRegDef(Reg)->eraseFromParent();
 474 }
 475
 476 bool SILowerControlFlow::runOnMachineFunction(MachineFunction &MF) {
 477   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
 478   TII = ST.getInstrInfo();
 479   TRI = &TII->getRegisterInfo();
 480
 481   // This doesn't actually need LiveIntervals, but we can preserve them.
 482   LIS = getAnalysisIfAvailable<LiveIntervals>();
 483   MRI = &MF.getRegInfo();
 484   BoolRC = TRI->getBoolRC();
 485
 486   if (ST.isWave32()) {
 487     AndOpc = AMDGPU::S_AND_B32;
 488     OrOpc = AMDGPU::S_OR_B32;
 489     XorOpc = AMDGPU::S_XOR_B32;
 490     MovTermOpc = AMDGPU::S_MOV_B32_term;
 491     Andn2TermOpc = AMDGPU::S_ANDN2_B32_term;
 492     XorTermrOpc = AMDGPU::S_XOR_B32_term;
 493     OrSaveExecOpc = AMDGPU::S_OR_SAVEEXEC_B32;
 494     Exec = AMDGPU::EXEC_LO;
 495   } else {
 496     AndOpc = AMDGPU::S_AND_B64;
 497     OrOpc = AMDGPU::S_OR_B64;
 498     XorOpc = AMDGPU::S_XOR_B64;
 499     MovTermOpc = AMDGPU::S_MOV_B64_term;
 500     Andn2TermOpc = AMDGPU::S_ANDN2_B64_term;
 501     XorTermrOpc = AMDGPU::S_XOR_B64_term;
 502     OrSaveExecOpc = AMDGPU::S_OR_SAVEEXEC_B64;
 503     Exec = AMDGPU::EXEC;
 504   }
 505
 506   MachineFunction::iterator NextBB;
 507   for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
 508        BI != BE; BI = NextBB) {
 509     NextBB = std::next(BI);
 510     MachineBasicBlock &MBB = *BI;
 511
 512     MachineBasicBlock::iterator I, Next, Last;
 513
 514     for (I = MBB.begin(), Last = MBB.end(); I != MBB.end(); I = Next) {
 515       Next = std::next(I);
 516       MachineInstr &MI = *I;
 517
 518       switch (MI.getOpcode()) {
 519       case AMDGPU::SI_IF:
 520         emitIf(MI);
 521         break;
 522
 523       case AMDGPU::SI_ELSE:
 524         emitElse(MI);
 525         break;
 526
 527       case AMDGPU::SI_IF_BREAK:
 528         emitIfBreak(MI);
 529         break;
 530
 531       case AMDGPU::SI_LOOP:
 532         emitLoop(MI);
 533         break;
 534
 535       case AMDGPU::SI_END_CF:
 536         emitEndCf(MI);
 537         break;
 538
 539       case AMDGPU::S_AND_B64:
 540       case AMDGPU::S_OR_B64:
 541       case AMDGPU::S_AND_B32:
 542       case AMDGPU::S_OR_B32:
 543         // Cleanup bit manipulations on exec mask
 544         combineMasks(MI);
 545         Last = I;
 546         continue;
 547
 548       default:
 549         Last = I;
 550         continue;
 551       }
 552
 553       // Replay newly inserted code to combine masks
 554       Next = (Last == MBB.end()) ? MBB.begin() : Last;
 555     }
 556   }
 557
 558   return true;
 559 }