lib/Target/ARM/ARM.td

   1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 //
  10 //===----------------------------------------------------------------------===//
  11
  12 //===----------------------------------------------------------------------===//
  13 // Target-independent interfaces which we are implementing
  14 //===----------------------------------------------------------------------===//
  15
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // ARM Subtarget state.
  20 //
  21
  22 def ModeThumb             : SubtargetFeature<"thumb-mode", "InThumbMode",
  23                                              "true", "Thumb mode">;
  24
  25 def ModeSoftFloat         : SubtargetFeature<"soft-float","UseSoftFloat",
  26                                              "true", "Use software floating "
  27                                              "point features.">;
  28
  29
  30 //===----------------------------------------------------------------------===//
  31 // ARM Subtarget features.
  32 //
  33
  34 // Floating Point, HW Division and Neon Support
  35
  36 // FP loads/stores/moves, shared between VFP and MVE (even in the integer-only
  37 // version).
  38 def FeatureFPRegs         : SubtargetFeature<"fpregs", "HasFPRegs", "true",
  39                                              "Enable FP registers">;
  40
  41 // 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16
  42 // extension) and MVE (even in the integer-only version).
  43 def FeatureFPRegs16       : SubtargetFeature<"fpregs16", "HasFPRegs16", "true",
  44                                              "Enable 16-bit FP registers",
  45                                              [FeatureFPRegs]>;
  46
  47 def FeatureFPRegs64       : SubtargetFeature<"fpregs64", "HasFPRegs64", "true",
  48                                              "Enable 64-bit FP registers",
  49                                              [FeatureFPRegs]>;
  50
  51 def FeatureFP64           : SubtargetFeature<"fp64", "HasFP64", "true",
  52                                              "Floating point unit supports "
  53                                              "double precision",
  54                                              [FeatureFPRegs64]>;
  55
  56 def FeatureD32            : SubtargetFeature<"d32", "HasD32", "true",
  57                                              "Extend FP to 32 double registers">;
  58
  59 multiclass VFPver<string name, string query, string description,
  60                   list<SubtargetFeature> prev = [],
  61                   list<SubtargetFeature> otherimplies = []> {
  62   def _D16_SP: SubtargetFeature<
  63     name#"d16sp", query#"D16SP", "true",
  64     description#" with only 16 d-registers and no double precision",
  65     !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16_SP")) # otherimplies>;
  66   def _SP: SubtargetFeature<
  67     name#"sp", query#"SP", "true",
  68     description#" with no double precision",
  69     !foreach(v, prev, !cast<SubtargetFeature>(v # "_SP")) #
  70       otherimplies # [FeatureD32, !cast<SubtargetFeature>(NAME # "_D16_SP")]>;
  71   def _D16: SubtargetFeature<
  72     name#"d16", query#"D16", "true",
  73     description#" with only 16 d-registers",
  74     !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16")) #
  75       otherimplies # [FeatureFP64, !cast<SubtargetFeature>(NAME # "_D16_SP")]>;
  76   def "": SubtargetFeature<
  77     name, query, "true", description,
  78     prev # otherimplies # [
  79         !cast<SubtargetFeature>(NAME # "_D16"),
  80         !cast<SubtargetFeature>(NAME # "_SP")]>;
  81 }
  82
  83 defm FeatureVFP2: VFPver<"vfp2", "HasVFPv2", "Enable VFP2 instructions",
  84                          [], [FeatureFPRegs]>;
  85
  86 defm FeatureVFP3: VFPver<"vfp3", "HasVFPv3", "Enable VFP3 instructions",
  87                          [FeatureVFP2]>;
  88
  89 def FeatureNEON           : SubtargetFeature<"neon", "HasNEON", "true",
  90                                              "Enable NEON instructions",
  91                                              [FeatureVFP3]>;
  92
  93 def FeatureFP16           : SubtargetFeature<"fp16", "HasFP16", "true",
  94                                              "Enable half-precision "
  95                                              "floating point">;
  96
  97 defm FeatureVFP4: VFPver<"vfp4", "HasVFPv4", "Enable VFP4 instructions",
  98                          [FeatureVFP3], [FeatureFP16]>;
  99
 100 defm FeatureFPARMv8: VFPver<"fp-armv8", "HasFPARMv8", "Enable ARMv8 FP",
 101                          [FeatureVFP4]>;
 102
 103 def FeatureFullFP16       : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
 104                                              "Enable full half-precision "
 105                                              "floating point",
 106                                              [FeatureFPARMv8_D16_SP, FeatureFPRegs16]>;
 107
 108 def FeatureFP16FML        : SubtargetFeature<"fp16fml", "HasFP16FML", "true",
 109                                              "Enable full half-precision "
 110                                              "floating point fml instructions",
 111                                              [FeatureFullFP16]>;
 112
 113 def FeatureHWDivThumb     : SubtargetFeature<"hwdiv",
 114                                              "HasHardwareDivideInThumb", "true",
 115                                              "Enable divide instructions in Thumb">;
 116
 117 def FeatureHWDivARM       : SubtargetFeature<"hwdiv-arm",
 118                                              "HasHardwareDivideInARM", "true",
 119                                              "Enable divide instructions in ARM mode">;
 120
 121 // Atomic Support
 122 def FeatureDB             : SubtargetFeature<"db", "HasDataBarrier", "true",
 123                                              "Has data barrier (dmb/dsb) instructions">;
 124
 125 def FeatureV7Clrex        : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
 126                                              "Has v7 clrex instruction">;
 127
 128 def FeatureDFB  : SubtargetFeature<"dfb", "HasFullDataBarrier", "true",
 129                                    "Has full data barrier (dfb) instruction">;
 130
 131 def FeatureAcquireRelease : SubtargetFeature<"acquire-release",
 132                                              "HasAcquireRelease", "true",
 133                                              "Has v8 acquire/release (lda/ldaex "
 134                                              " etc) instructions">;
 135
 136
 137 def FeatureSlowFPBrcc     : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
 138                                              "FP compare + branch is slow">;
 139
 140 def FeaturePerfMon        : SubtargetFeature<"perfmon", "HasPerfMon", "true",
 141                                              "Enable support for Performance "
 142                                              "Monitor extensions">;
 143
 144
 145 // TrustZone Security Extensions
 146 def FeatureTrustZone      : SubtargetFeature<"trustzone", "HasTrustZone", "true",
 147                                              "Enable support for TrustZone "
 148                                              "security extensions">;
 149
 150 def Feature8MSecExt       : SubtargetFeature<"8msecext", "Has8MSecExt", "true",
 151                                              "Enable support for ARMv8-M "
 152                                              "Security Extensions">;
 153
 154 def FeatureSHA2           : SubtargetFeature<"sha2", "HasSHA2", "true",
 155                                              "Enable SHA1 and SHA256 support", [FeatureNEON]>;
 156
 157 def FeatureAES            : SubtargetFeature<"aes", "HasAES", "true",
 158                                              "Enable AES support", [FeatureNEON]>;
 159
 160 def FeatureCrypto         : SubtargetFeature<"crypto", "HasCrypto", "true",
 161                                              "Enable support for "
 162                                              "Cryptography extensions",
 163                                              [FeatureNEON, FeatureSHA2, FeatureAES]>;
 164
 165 def FeatureCRC            : SubtargetFeature<"crc", "HasCRC", "true",
 166                                              "Enable support for CRC instructions">;
 167
 168 def FeatureDotProd        : SubtargetFeature<"dotprod", "HasDotProd", "true",
 169                                              "Enable support for dot product instructions",
 170                                              [FeatureNEON]>;
 171
 172 // Not to be confused with FeatureHasRetAddrStack (return address stack)
 173 def FeatureRAS            : SubtargetFeature<"ras", "HasRAS", "true",
 174                                              "Enable Reliability, Availability "
 175                                              "and Serviceability extensions">;
 176
 177 // Fast computation of non-negative address offsets
 178 def FeatureFPAO           : SubtargetFeature<"fpao", "HasFPAO", "true",
 179                                              "Enable fast computation of "
 180                                              "positive address offsets">;
 181
 182 // Fast execution of AES crypto operations
 183 def FeatureFuseAES        : SubtargetFeature<"fuse-aes", "HasFuseAES", "true",
 184                                              "CPU fuses AES crypto operations">;
 185
 186 // Fast execution of bottom and top halves of literal generation
 187 def FeatureFuseLiterals   : SubtargetFeature<"fuse-literals", "HasFuseLiterals", "true",
 188                                              "CPU fuses literal generation operations">;
 189
 190 // The way of reading thread pointer
 191 def FeatureReadTp :  SubtargetFeature<"read-tp-hard", "ReadTPHard", "true",
 192                                       "Reading thread pointer from register">;
 193
 194 // Cyclone can zero VFP registers in 0 cycles.
 195 def FeatureZCZeroing      : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
 196                                              "Has zero-cycle zeroing instructions">;
 197
 198 // Whether it is profitable to unpredicate certain instructions during if-conversion
 199 def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr",
 200                                               "IsProfitableToUnpredicate", "true",
 201                                               "Is profitable to unpredicate">;
 202
 203 // Some targets (e.g. Swift) have microcoded VGETLNi32.
 204 def FeatureSlowVGETLNi32  : SubtargetFeature<"slow-vgetlni32",
 205                                              "HasSlowVGETLNi32", "true",
 206                                              "Has slow VGETLNi32 - prefer VMOV">;
 207
 208 // Some targets (e.g. Swift) have microcoded VDUP32.
 209 def FeatureSlowVDUP32     : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32",
 210                                              "true",
 211                                              "Has slow VDUP32 - prefer VMOV">;
 212
 213 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
 214 // for scalar FP, as this allows more effective execution domain optimization.
 215 def FeaturePreferVMOVSR   : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR",
 216                                              "true", "Prefer VMOVSR">;
 217
 218 // Swift has ISHST barriers compatible with Atomic Release semantics but weaker
 219 // than ISH
 220 def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST",
 221                                                "true", "Prefer ISHST barriers">;
 222
 223 // Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU.
 224 def FeatureMuxedUnits     : SubtargetFeature<"muxed-units", "HasMuxedUnits",
 225                                              "true",
 226                                              "Has muxed AGU and NEON/FPU">;
 227
 228 // Whether VLDM/VSTM starting with odd register number need more microops
 229 // than single VLDRS
 230 def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister",
 231                                               "true", "VLDM/VSTM starting "
 232                                               "with an odd register is slow">;
 233
 234 // Some targets have a renaming dependency when loading into D subregisters.
 235 def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg",
 236                                               "SlowLoadDSubregister", "true",
 237                                               "Loading into D subregs is slow">;
 238
 239 def FeatureUseWideStrideVFP : SubtargetFeature<"wide-stride-vfp",
 240                                                "UseWideStrideVFP", "true",
 241                                                "Use a wide stride when allocating VFP registers">;
 242
 243 // Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD.
 244 def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs",
 245                                              "DontWidenVMOVS", "true",
 246                                              "Don't widen VMOVS to VMOVD">;
 247
 248 // Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different
 249 // VFP register widths.
 250 def FeatureSplatVFPToNeon : SubtargetFeature<"splat-vfp-neon",
 251                                              "SplatVFPToNeon", "true",
 252                                              "Splat register from VFP to NEON",
 253                                              [FeatureDontWidenVMOVS]>;
 254
 255 // Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions.
 256 def FeatureExpandMLx      : SubtargetFeature<"expand-fp-mlx",
 257                                              "ExpandMLx", "true",
 258                                              "Expand VFP/NEON MLA/MLS instructions">;
 259
 260 // Some targets have special RAW hazards for VFP/NEON VMLA/VMLS.
 261 def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards",
 262                                              "true", "Has VMLx hazards">;
 263
 264 // Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
 265 // VFP to NEON, as an execution domain optimization.
 266 def FeatureNEONForFPMovs  : SubtargetFeature<"neon-fpmovs",
 267                                              "UseNEONForFPMovs", "true",
 268                                              "Convert VMOVSR, VMOVRS, "
 269                                              "VMOVS to NEON">;
 270
 271 // Some processors benefit from using NEON instructions for scalar
 272 // single-precision FP operations. This affects instruction selection and should
 273 // only be enabled if the handling of denormals is not important.
 274 def FeatureNEONForFP      : SubtargetFeature<"neonfp",
 275                                              "UseNEONForSinglePrecisionFP",
 276                                              "true",
 277                                              "Use NEON for single precision FP">;
 278
 279 // On some processors, VLDn instructions that access unaligned data take one
 280 // extra cycle. Take that into account when computing operand latencies.
 281 def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign",
 282                                              "true",
 283                                              "Check for VLDn unaligned access">;
 284
 285 // Some processors have a nonpipelined VFP coprocessor.
 286 def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp",
 287                                               "NonpipelinedVFP", "true",
 288                                               "VFP instructions are not pipelined">;
 289
 290 // Some processors have FP multiply-accumulate instructions that don't
 291 // play nicely with other VFP / NEON instructions, and it's generally better
 292 // to just not use them.
 293 def FeatureHasSlowFPVMLx  : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
 294                                              "Disable VFP / NEON MAC instructions">;
 295
 296 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
 297 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
 298                                              "HasVMLxForwarding", "true",
 299                                              "Has multiplier accumulator forwarding">;
 300
 301 // Disable 32-bit to 16-bit narrowing for experimentation.
 302 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
 303                                              "Prefer 32-bit Thumb instrs">;
 304
 305 def FeaturePrefLoopAlign32 : SubtargetFeature<"loop-align", "PrefLoopAlignment","2",
 306                                               "Prefer 32-bit alignment for loops">;
 307
 308 /// Some instructions update CPSR partially, which can add false dependency for
 309 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
 310 /// mapped to a separate physical register. Avoid partial CPSR update for these
 311 /// processors.
 312 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
 313                                                "AvoidCPSRPartialUpdate", "true",
 314                                  "Avoid CPSR partial update for OOO execution">;
 315
 316 /// Disable +1 predication cost for instructions updating CPSR.
 317 /// Enabled for Cortex-A57.
 318 def FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr",
 319                                                   "CheapPredicableCPSRDef",
 320                                                   "true",
 321                   "Disable +1 predication cost for instructions updating CPSR">;
 322
 323 def FeatureAvoidMOVsShOp  : SubtargetFeature<"avoid-movs-shop",
 324                                              "AvoidMOVsShifterOperand", "true",
 325                                              "Avoid movs instructions with "
 326                                              "shifter operand">;
 327
 328 // Some processors perform return stack prediction. CodeGen should avoid issue
 329 // "normal" call instructions to callees which do not return.
 330 def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack",
 331                                               "HasRetAddrStack", "true",
 332                                               "Has return address stack">;
 333
 334 // Some processors have no branch predictor, which changes the expected cost of
 335 // taking a branch which affects the choice of whether to use predicated
 336 // instructions.
 337 def FeatureHasNoBranchPredictor : SubtargetFeature<"no-branch-predictor",
 338                                                    "HasBranchPredictor", "false",
 339                                                    "Has no branch predictor">;
 340
 341 /// DSP extension.
 342 def FeatureDSP            : SubtargetFeature<"dsp", "HasDSP", "true",
 343                                              "Supports DSP instructions in "
 344                                              "ARM and/or Thumb2">;
 345
 346 // Multiprocessing extension.
 347 def FeatureMP             : SubtargetFeature<"mp", "HasMPExtension", "true",
 348                                         "Supports Multiprocessing extension">;
 349
 350 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
 351 def FeatureVirtualization : SubtargetFeature<"virtualization",
 352                                              "HasVirtualization", "true",
 353                                              "Supports Virtualization extension",
 354                                              [FeatureHWDivThumb, FeatureHWDivARM]>;
 355
 356 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
 357 // See ARMInstrInfo.td for details.
 358 def FeatureNaClTrap       : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
 359                                              "NaCl trap">;
 360
 361 def FeatureStrictAlign    : SubtargetFeature<"strict-align",
 362                                              "StrictAlign", "true",
 363                                              "Disallow all unaligned memory "
 364                                              "access">;
 365
 366 def FeatureLongCalls      : SubtargetFeature<"long-calls", "GenLongCalls", "true",
 367                                              "Generate calls via indirect call "
 368                                              "instructions">;
 369
 370 def FeatureExecuteOnly    : SubtargetFeature<"execute-only",
 371                                              "GenExecuteOnly", "true",
 372                                              "Enable the generation of "
 373                                              "execute only code.">;
 374
 375 def FeatureReserveR9      : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
 376                                              "Reserve R9, making it unavailable"
 377                                              " as GPR">;
 378
 379 def FeatureNoMovt         : SubtargetFeature<"no-movt", "NoMovt", "true",
 380                                              "Don't use movt/movw pairs for "
 381                                              "32-bit imms">;
 382
 383 def FeatureNoNegativeImmediates
 384                           : SubtargetFeature<"no-neg-immediates",
 385                                              "NegativeImmediates", "false",
 386                                              "Convert immediates and instructions "
 387                                              "to their negated or complemented "
 388                                              "equivalent when the immediate does "
 389                                              "not fit in the encoding.">;
 390
 391 // Use the MachineScheduler for instruction scheduling for the subtarget.
 392 def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true",
 393                                         "Use the MachineScheduler">;
 394
 395 def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler",
 396     "DisablePostRAScheduler", "true",
 397     "Don't schedule again after register allocation">;
 398
 399 // Enable use of alias analysis during code generation
 400 def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
 401                                     "Use alias analysis during codegen">;
 402
 403 // Armv8.5-A extensions
 404
 405 def FeatureSB       : SubtargetFeature<"sb", "HasSB", "true",
 406   "Enable v8.5a Speculation Barrier" >;
 407
 408 // Armv8.1-M extensions
 409
 410 def FeatureLOB            : SubtargetFeature<"lob", "HasLOB", "true",
 411                                              "Enable Low Overhead Branch "
 412                                              "extensions">;
 413
 414 //===----------------------------------------------------------------------===//
 415 // ARM architecture class
 416 //
 417
 418 // A-series ISA
 419 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
 420                                      "Is application profile ('A' series)">;
 421
 422 // R-series ISA
 423 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
 424                                      "Is realtime profile ('R' series)">;
 425
 426 // M-series ISA
 427 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
 428                                      "Is microcontroller profile ('M' series)">;
 429
 430
 431 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
 432                                      "Enable Thumb2 instructions">;
 433
 434 def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
 435                                      "Does not support ARM mode execution">;
 436
 437 //===----------------------------------------------------------------------===//
 438 // ARM ISAa.
 439 //
 440
 441 def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
 442                                    "Support ARM v4T instructions">;
 443
 444 def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
 445                                    "Support ARM v5T instructions",
 446                                    [HasV4TOps]>;
 447
 448 def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
 449                                    "Support ARM v5TE, v5TEj, and "
 450                                    "v5TExp instructions",
 451                                    [HasV5TOps]>;
 452
 453 def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
 454                                    "Support ARM v6 instructions",
 455                                    [HasV5TEOps]>;
 456
 457 def HasV6MOps   : SubtargetFeature<"v6m", "HasV6MOps", "true",
 458                                    "Support ARM v6M instructions",
 459                                    [HasV6Ops]>;
 460
 461 def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true",
 462                                          "Support ARM v8M Baseline instructions",
 463                                          [HasV6MOps]>;
 464
 465 def HasV6KOps   : SubtargetFeature<"v6k", "HasV6KOps", "true",
 466                                    "Support ARM v6k instructions",
 467                                    [HasV6Ops]>;
 468
 469 def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
 470                                    "Support ARM v6t2 instructions",
 471                                    [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>;
 472
 473 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
 474                                    "Support ARM v7 instructions",
 475                                    [HasV6T2Ops, FeaturePerfMon,
 476                                     FeatureV7Clrex]>;
 477
 478 def HasV8MMainlineOps :
 479                   SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true",
 480                                    "Support ARM v8M Mainline instructions",
 481                                    [HasV7Ops]>;
 482
 483 def HasV8Ops    : SubtargetFeature<"v8", "HasV8Ops", "true",
 484                                    "Support ARM v8 instructions",
 485                                    [HasV7Ops, FeatureAcquireRelease]>;
 486
 487 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
 488                                    "Support ARM v8.1a instructions",
 489                                    [HasV8Ops]>;
 490
 491 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
 492                                    "Support ARM v8.2a instructions",
 493                                    [HasV8_1aOps]>;
 494
 495 def HasV8_3aOps   : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
 496                                    "Support ARM v8.3a instructions",
 497                                    [HasV8_2aOps]>;
 498
 499 def HasV8_4aOps   : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
 500                                    "Support ARM v8.4a instructions",
 501                                    [HasV8_3aOps, FeatureDotProd]>;
 502
 503 def HasV8_5aOps   : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true",
 504                                    "Support ARM v8.5a instructions",
 505                                    [HasV8_4aOps, FeatureSB]>;
 506
 507 def HasV8_1MMainlineOps : SubtargetFeature<
 508                "v8.1m.main", "HasV8_1MMainlineOps", "true",
 509                "Support ARM v8-1M Mainline instructions",
 510                [HasV8MMainlineOps]>;
 511 def HasMVEIntegerOps : SubtargetFeature<
 512                "mve", "HasMVEIntegerOps", "true",
 513                "Support M-Class Vector Extension with integer ops",
 514                [HasV8_1MMainlineOps, FeatureDSP, FeatureFPRegs16, FeatureFPRegs64]>;
 515 def HasMVEFloatOps : SubtargetFeature<
 516                "mve.fp", "HasMVEFloatOps", "true",
 517                "Support M-Class Vector Extension with integer and floating ops",
 518                [HasMVEIntegerOps, FeatureFPARMv8_D16_SP, FeatureFullFP16]>;
 519
 520 //===----------------------------------------------------------------------===//
 521 // ARM Processor subtarget features.
 522 //
 523
 524 def ProcA5      : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
 525                                    "Cortex-A5 ARM processors", []>;
 526 def ProcA7      : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
 527                                    "Cortex-A7 ARM processors", []>;
 528 def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
 529                                    "Cortex-A8 ARM processors", []>;
 530 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
 531                                    "Cortex-A9 ARM processors", []>;
 532 def ProcA12     : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
 533                                    "Cortex-A12 ARM processors", []>;
 534 def ProcA15     : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
 535                                    "Cortex-A15 ARM processors", []>;
 536 def ProcA17     : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
 537                                    "Cortex-A17 ARM processors", []>;
 538 def ProcA32     : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32",
 539                                    "Cortex-A32 ARM processors", []>;
 540 def ProcA35     : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
 541                                    "Cortex-A35 ARM processors", []>;
 542 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
 543                                    "Cortex-A53 ARM processors", []>;
 544 def ProcA55     : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
 545                                    "Cortex-A55 ARM processors", []>;
 546 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
 547                                    "Cortex-A57 ARM processors", []>;
 548 def ProcA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
 549                                    "Cortex-A72 ARM processors", []>;
 550 def ProcA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
 551                                    "Cortex-A73 ARM processors", []>;
 552 def ProcA75     : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
 553                                    "Cortex-A75 ARM processors", []>;
 554 def ProcA76     : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76",
 555                                    "Cortex-A76 ARM processors", []>;
 556
 557 def ProcKrait   : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
 558                                    "Qualcomm Krait processors", []>;
 559 def ProcKryo    : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
 560                                    "Qualcomm Kryo processors", []>;
 561 def ProcSwift   : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
 562                                    "Swift ARM processors", []>;
 563
 564 def ProcExynos  : SubtargetFeature<"exynos", "ARMProcFamily", "Exynos",
 565                                    "Samsung Exynos processors",
 566                                    [FeatureZCZeroing,
 567                                     FeatureUseWideStrideVFP,
 568                                     FeatureUseAA,
 569                                     FeatureSplatVFPToNeon,
 570                                     FeatureSlowVGETLNi32,
 571                                     FeatureSlowVDUP32,
 572                                     FeatureSlowFPBrcc,
 573                                     FeatureProfUnpredicate,
 574                                     FeatureHWDivThumb,
 575                                     FeatureHWDivARM,
 576                                     FeatureHasSlowFPVMLx,
 577                                     FeatureHasRetAddrStack,
 578                                     FeatureFuseLiterals,
 579                                     FeatureFuseAES,
 580                                     FeatureExpandMLx,
 581                                     FeatureCrypto,
 582                                     FeatureCRC]>;
 583
 584 def ProcR4      : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
 585                                    "Cortex-R4 ARM processors", []>;
 586 def ProcR5      : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
 587                                    "Cortex-R5 ARM processors", []>;
 588 def ProcR7      : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
 589                                    "Cortex-R7 ARM processors", []>;
 590 def ProcR52     : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52",
 591                                    "Cortex-R52 ARM processors", []>;
 592
 593 def ProcM3      : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3",
 594                                    "Cortex-M3 ARM processors", []>;
 595
 596
 597 //===----------------------------------------------------------------------===//
 598 // ARM Helper classes.
 599 //
 600
 601 class Architecture<string fname, string aname, list<SubtargetFeature> features>
 602   : SubtargetFeature<fname, "ARMArch", aname,
 603                      !strconcat(aname, " architecture"), features>;
 604
 605 class ProcNoItin<string Name, list<SubtargetFeature> Features>
 606   : Processor<Name, NoItineraries, Features>;
 607
 608
 609 //===----------------------------------------------------------------------===//
 610 // ARM architectures
 611 //
 612
 613 def ARMv2     : Architecture<"armv2",     "ARMv2",    []>;
 614
 615 def ARMv2a    : Architecture<"armv2a",    "ARMv2a",   []>;
 616
 617 def ARMv3     : Architecture<"armv3",     "ARMv3",    []>;
 618
 619 def ARMv3m    : Architecture<"armv3m",    "ARMv3m",   []>;
 620
 621 def ARMv4     : Architecture<"armv4",     "ARMv4",    []>;
 622
 623 def ARMv4t    : Architecture<"armv4t",    "ARMv4t",   [HasV4TOps]>;
 624
 625 def ARMv5t    : Architecture<"armv5t",    "ARMv5t",   [HasV5TOps]>;
 626
 627 def ARMv5te   : Architecture<"armv5te",   "ARMv5te",  [HasV5TEOps]>;
 628
 629 def ARMv5tej  : Architecture<"armv5tej",  "ARMv5tej", [HasV5TEOps]>;
 630
 631 def ARMv6     : Architecture<"armv6",     "ARMv6",    [HasV6Ops,
 632                                                        FeatureDSP]>;
 633
 634 def ARMv6t2   : Architecture<"armv6t2",   "ARMv6t2",  [HasV6T2Ops,
 635                                                        FeatureDSP]>;
 636
 637 def ARMv6k    : Architecture<"armv6k",    "ARMv6k",   [HasV6KOps]>;
 638
 639 def ARMv6kz   : Architecture<"armv6kz",   "ARMv6kz",  [HasV6KOps,
 640                                                        FeatureTrustZone]>;
 641
 642 def ARMv6m    : Architecture<"armv6-m",   "ARMv6m",   [HasV6MOps,
 643                                                        FeatureNoARM,
 644                                                        ModeThumb,
 645                                                        FeatureDB,
 646                                                        FeatureMClass,
 647                                                        FeatureStrictAlign]>;
 648
 649 def ARMv6sm   : Architecture<"armv6s-m",  "ARMv6sm",  [HasV6MOps,
 650                                                        FeatureNoARM,
 651                                                        ModeThumb,
 652                                                        FeatureDB,
 653                                                        FeatureMClass,
 654                                                        FeatureStrictAlign]>;
 655
 656 def ARMv7a    : Architecture<"armv7-a",   "ARMv7a",   [HasV7Ops,
 657                                                        FeatureNEON,
 658                                                        FeatureDB,
 659                                                        FeatureDSP,
 660                                                        FeatureAClass]>;
 661
 662 def ARMv7ve   : Architecture<"armv7ve",   "ARMv7ve",  [HasV7Ops,
 663                                                        FeatureNEON,
 664                                                        FeatureDB,
 665                                                        FeatureDSP,
 666                                                        FeatureTrustZone,
 667                                                        FeatureMP,
 668                                                        FeatureVirtualization,
 669                                                        FeatureAClass]>;
 670
 671 def ARMv7r    : Architecture<"armv7-r",   "ARMv7r",   [HasV7Ops,
 672                                                        FeatureDB,
 673                                                        FeatureDSP,
 674                                                        FeatureHWDivThumb,
 675                                                        FeatureRClass]>;
 676
 677 def ARMv7m    : Architecture<"armv7-m",   "ARMv7m",   [HasV7Ops,
 678                                                        FeatureThumb2,
 679                                                        FeatureNoARM,
 680                                                        ModeThumb,
 681                                                        FeatureDB,
 682                                                        FeatureHWDivThumb,
 683                                                        FeatureMClass]>;
 684
 685 def ARMv7em   : Architecture<"armv7e-m",  "ARMv7em",  [HasV7Ops,
 686                                                        FeatureThumb2,
 687                                                        FeatureNoARM,
 688                                                        ModeThumb,
 689                                                        FeatureDB,
 690                                                        FeatureHWDivThumb,
 691                                                        FeatureMClass,
 692                                                        FeatureDSP]>;
 693
 694 def ARMv8a    : Architecture<"armv8-a",   "ARMv8a",   [HasV8Ops,
 695                                                        FeatureAClass,
 696                                                        FeatureDB,
 697                                                        FeatureFPARMv8,
 698                                                        FeatureNEON,
 699                                                        FeatureDSP,
 700                                                        FeatureTrustZone,
 701                                                        FeatureMP,
 702                                                        FeatureVirtualization,
 703                                                        FeatureCrypto,
 704                                                        FeatureCRC]>;
 705
 706 def ARMv81a   : Architecture<"armv8.1-a", "ARMv81a",  [HasV8_1aOps,
 707                                                        FeatureAClass,
 708                                                        FeatureDB,
 709                                                        FeatureFPARMv8,
 710                                                        FeatureNEON,
 711                                                        FeatureDSP,
 712                                                        FeatureTrustZone,
 713                                                        FeatureMP,
 714                                                        FeatureVirtualization,
 715                                                        FeatureCrypto,
 716                                                        FeatureCRC]>;
 717
 718 def ARMv82a   : Architecture<"armv8.2-a", "ARMv82a",  [HasV8_2aOps,
 719                                                        FeatureAClass,
 720                                                        FeatureDB,
 721                                                        FeatureFPARMv8,
 722                                                        FeatureNEON,
 723                                                        FeatureDSP,
 724                                                        FeatureTrustZone,
 725                                                        FeatureMP,
 726                                                        FeatureVirtualization,
 727                                                        FeatureCrypto,
 728                                                        FeatureCRC,
 729                                                        FeatureRAS]>;
 730
 731 def ARMv83a   : Architecture<"armv8.3-a", "ARMv83a",  [HasV8_3aOps,
 732                                                        FeatureAClass,
 733                                                        FeatureDB,
 734                                                        FeatureFPARMv8,
 735                                                        FeatureNEON,
 736                                                        FeatureDSP,
 737                                                        FeatureTrustZone,
 738                                                        FeatureMP,
 739                                                        FeatureVirtualization,
 740                                                        FeatureCrypto,
 741                                                        FeatureCRC,
 742                                                        FeatureRAS]>;
 743
 744 def ARMv84a   : Architecture<"armv8.4-a", "ARMv84a",  [HasV8_4aOps,
 745                                                        FeatureAClass,
 746                                                        FeatureDB,
 747                                                        FeatureFPARMv8,
 748                                                        FeatureNEON,
 749                                                        FeatureDSP,
 750                                                        FeatureTrustZone,
 751                                                        FeatureMP,
 752                                                        FeatureVirtualization,
 753                                                        FeatureCrypto,
 754                                                        FeatureCRC,
 755                                                        FeatureRAS,
 756                                                        FeatureDotProd]>;
 757
 758 def ARMv85a   : Architecture<"armv8.5-a", "ARMv85a",  [HasV8_5aOps,
 759                                                        FeatureAClass,
 760                                                        FeatureDB,
 761                                                        FeatureFPARMv8,
 762                                                        FeatureNEON,
 763                                                        FeatureDSP,
 764                                                        FeatureTrustZone,
 765                                                        FeatureMP,
 766                                                        FeatureVirtualization,
 767                                                        FeatureCrypto,
 768                                                        FeatureCRC,
 769                                                        FeatureRAS,
 770                                                        FeatureDotProd]>;
 771
 772 def ARMv8r    : Architecture<"armv8-r",   "ARMv8r",   [HasV8Ops,
 773                                                        FeatureRClass,
 774                                                        FeatureDB,
 775                                                        FeatureDFB,
 776                                                        FeatureDSP,
 777                                                        FeatureCRC,
 778                                                        FeatureMP,
 779                                                        FeatureVirtualization,
 780                                                        FeatureFPARMv8,
 781                                                        FeatureNEON]>;
 782
 783 def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
 784                                                       [HasV8MBaselineOps,
 785                                                        FeatureNoARM,
 786                                                        ModeThumb,
 787                                                        FeatureDB,
 788                                                        FeatureHWDivThumb,
 789                                                        FeatureV7Clrex,
 790                                                        Feature8MSecExt,
 791                                                        FeatureAcquireRelease,
 792                                                        FeatureMClass,
 793                                                        FeatureStrictAlign]>;
 794
 795 def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline",
 796                                                       [HasV8MMainlineOps,
 797                                                        FeatureNoARM,
 798                                                        ModeThumb,
 799                                                        FeatureDB,
 800                                                        FeatureHWDivThumb,
 801                                                        Feature8MSecExt,
 802                                                        FeatureAcquireRelease,
 803                                                        FeatureMClass]>;
 804
 805 def ARMv81mMainline : Architecture<"armv8.1-m.main", "ARMv81mMainline",
 806                                                       [HasV8_1MMainlineOps,
 807                                                        FeatureNoARM,
 808                                                        ModeThumb,
 809                                                        FeatureDB,
 810                                                        FeatureHWDivThumb,
 811                                                        Feature8MSecExt,
 812                                                        FeatureAcquireRelease,
 813                                                        FeatureMClass,
 814                                                        FeatureRAS,
 815                                                        FeatureLOB]>;
 816
 817 // Aliases
 818 def IWMMXT   : Architecture<"iwmmxt",      "ARMv5te",  [ARMv5te]>;
 819 def IWMMXT2  : Architecture<"iwmmxt2",     "ARMv5te",  [ARMv5te]>;
 820 def XScale   : Architecture<"xscale",      "ARMv5te",  [ARMv5te]>;
 821 def ARMv6j   : Architecture<"armv6j",      "ARMv7a",   [ARMv6]>;
 822 def ARMv7k   : Architecture<"armv7k",      "ARMv7a",   [ARMv7a]>;
 823 def ARMv7s   : Architecture<"armv7s",      "ARMv7a",   [ARMv7a]>;
 824
 825
 826 //===----------------------------------------------------------------------===//
 827 // ARM schedules.
 828 //===----------------------------------------------------------------------===//
 829 //
 830 include "ARMPredicates.td"
 831 include "ARMSchedule.td"
 832
 833 //===----------------------------------------------------------------------===//
 834 // ARM processors
 835 //
 836
 837 // Dummy CPU, used to target architectures
 838 def : ProcessorModel<"generic",     CortexA8Model,      []>;
 839
 840 // FIXME: Several processors below are not using their own scheduler
 841 // model, but one of similar/previous processor. These should be fixed.
 842
 843 def : ProcNoItin<"arm8",                                [ARMv4]>;
 844 def : ProcNoItin<"arm810",                              [ARMv4]>;
 845 def : ProcNoItin<"strongarm",                           [ARMv4]>;
 846 def : ProcNoItin<"strongarm110",                        [ARMv4]>;
 847 def : ProcNoItin<"strongarm1100",                       [ARMv4]>;
 848 def : ProcNoItin<"strongarm1110",                       [ARMv4]>;
 849
 850 def : ProcNoItin<"arm7tdmi",                            [ARMv4t]>;
 851 def : ProcNoItin<"arm7tdmi-s",                          [ARMv4t]>;
 852 def : ProcNoItin<"arm710t",                             [ARMv4t]>;
 853 def : ProcNoItin<"arm720t",                             [ARMv4t]>;
 854 def : ProcNoItin<"arm9",                                [ARMv4t]>;
 855 def : ProcNoItin<"arm9tdmi",                            [ARMv4t]>;
 856 def : ProcNoItin<"arm920",                              [ARMv4t]>;
 857 def : ProcNoItin<"arm920t",                             [ARMv4t]>;
 858 def : ProcNoItin<"arm922t",                             [ARMv4t]>;
 859 def : ProcNoItin<"arm940t",                             [ARMv4t]>;
 860 def : ProcNoItin<"ep9312",                              [ARMv4t]>;
 861
 862 def : ProcNoItin<"arm10tdmi",                           [ARMv5t]>;
 863 def : ProcNoItin<"arm1020t",                            [ARMv5t]>;
 864
 865 def : ProcNoItin<"arm9e",                               [ARMv5te]>;
 866 def : ProcNoItin<"arm926ej-s",                          [ARMv5te]>;
 867 def : ProcNoItin<"arm946e-s",                           [ARMv5te]>;
 868 def : ProcNoItin<"arm966e-s",                           [ARMv5te]>;
 869 def : ProcNoItin<"arm968e-s",                           [ARMv5te]>;
 870 def : ProcNoItin<"arm10e",                              [ARMv5te]>;
 871 def : ProcNoItin<"arm1020e",                            [ARMv5te]>;
 872 def : ProcNoItin<"arm1022e",                            [ARMv5te]>;
 873 def : ProcNoItin<"xscale",                              [ARMv5te]>;
 874 def : ProcNoItin<"iwmmxt",                              [ARMv5te]>;
 875
 876 def : Processor<"arm1136j-s",       ARMV6Itineraries,   [ARMv6]>;
 877 def : Processor<"arm1136jf-s",      ARMV6Itineraries,   [ARMv6,
 878                                                          FeatureVFP2,
 879                                                          FeatureHasSlowFPVMLx]>;
 880
 881 def : Processor<"cortex-m0",        ARMV6Itineraries,   [ARMv6m]>;
 882 def : Processor<"cortex-m0plus",    ARMV6Itineraries,   [ARMv6m]>;
 883 def : Processor<"cortex-m1",        ARMV6Itineraries,   [ARMv6m]>;
 884 def : Processor<"sc000",            ARMV6Itineraries,   [ARMv6m]>;
 885
 886 def : Processor<"arm1176j-s",       ARMV6Itineraries,   [ARMv6kz]>;
 887 def : Processor<"arm1176jz-s",      ARMV6Itineraries,   [ARMv6kz]>;
 888 def : Processor<"arm1176jzf-s",     ARMV6Itineraries,   [ARMv6kz,
 889                                                          FeatureVFP2,
 890                                                          FeatureHasSlowFPVMLx]>;
 891
 892 def : Processor<"mpcorenovfp",      ARMV6Itineraries,   [ARMv6k]>;
 893 def : Processor<"mpcore",           ARMV6Itineraries,   [ARMv6k,
 894                                                          FeatureVFP2,
 895                                                          FeatureHasSlowFPVMLx]>;
 896
 897 def : Processor<"arm1156t2-s",      ARMV6Itineraries,   [ARMv6t2]>;
 898 def : Processor<"arm1156t2f-s",     ARMV6Itineraries,   [ARMv6t2,
 899                                                          FeatureVFP2,
 900                                                          FeatureHasSlowFPVMLx]>;
 901
 902 def : ProcessorModel<"cortex-a5",   CortexA8Model,      [ARMv7a, ProcA5,
 903                                                          FeatureHasRetAddrStack,
 904                                                          FeatureTrustZone,
 905                                                          FeatureSlowFPBrcc,
 906                                                          FeatureHasSlowFPVMLx,
 907                                                          FeatureVMLxForwarding,
 908                                                          FeatureMP,
 909                                                          FeatureVFP4]>;
 910
 911 def : ProcessorModel<"cortex-a7",   CortexA8Model,      [ARMv7a, ProcA7,
 912                                                          FeatureHasRetAddrStack,
 913                                                          FeatureTrustZone,
 914                                                          FeatureSlowFPBrcc,
 915                                                          FeatureHasVMLxHazards,
 916                                                          FeatureHasSlowFPVMLx,
 917                                                          FeatureVMLxForwarding,
 918                                                          FeatureMP,
 919                                                          FeatureVFP4,
 920                                                          FeatureVirtualization]>;
 921
 922 def : ProcessorModel<"cortex-a8",   CortexA8Model,      [ARMv7a, ProcA8,
 923                                                          FeatureHasRetAddrStack,
 924                                                          FeatureNonpipelinedVFP,
 925                                                          FeatureTrustZone,
 926                                                          FeatureSlowFPBrcc,
 927                                                          FeatureHasVMLxHazards,
 928                                                          FeatureHasSlowFPVMLx,
 929                                                          FeatureVMLxForwarding]>;
 930
 931 def : ProcessorModel<"cortex-a9",   CortexA9Model,      [ARMv7a, ProcA9,
 932                                                          FeatureHasRetAddrStack,
 933                                                          FeatureTrustZone,
 934                                                          FeatureHasVMLxHazards,
 935                                                          FeatureVMLxForwarding,
 936                                                          FeatureFP16,
 937                                                          FeatureAvoidPartialCPSR,
 938                                                          FeatureExpandMLx,
 939                                                          FeaturePreferVMOVSR,
 940                                                          FeatureMuxedUnits,
 941                                                          FeatureNEONForFPMovs,
 942                                                          FeatureCheckVLDnAlign,
 943                                                          FeatureMP]>;
 944
 945 def : ProcessorModel<"cortex-a12",  CortexA9Model,      [ARMv7a, ProcA12,
 946                                                          FeatureHasRetAddrStack,
 947                                                          FeatureTrustZone,
 948                                                          FeatureVMLxForwarding,
 949                                                          FeatureVFP4,
 950                                                          FeatureAvoidPartialCPSR,
 951                                                          FeatureVirtualization,
 952                                                          FeatureMP]>;
 953
 954 def : ProcessorModel<"cortex-a15",  CortexA9Model,      [ARMv7a, ProcA15,
 955                                                          FeatureDontWidenVMOVS,
 956                                                          FeatureSplatVFPToNeon,
 957                                                          FeatureHasRetAddrStack,
 958                                                          FeatureMuxedUnits,
 959                                                          FeatureTrustZone,
 960                                                          FeatureVFP4,
 961                                                          FeatureMP,
 962                                                          FeatureCheckVLDnAlign,
 963                                                          FeatureAvoidPartialCPSR,
 964                                                          FeatureVirtualization]>;
 965
 966 def : ProcessorModel<"cortex-a17",  CortexA9Model,      [ARMv7a, ProcA17,
 967                                                          FeatureHasRetAddrStack,
 968                                                          FeatureTrustZone,
 969                                                          FeatureMP,
 970                                                          FeatureVMLxForwarding,
 971                                                          FeatureVFP4,
 972                                                          FeatureAvoidPartialCPSR,
 973                                                          FeatureVirtualization]>;
 974
 975 // FIXME: krait has currently the same features as A9 plus VFP4 and  HWDiv
 976 def : ProcessorModel<"krait",       CortexA9Model,      [ARMv7a, ProcKrait,
 977                                                          FeatureHasRetAddrStack,
 978                                                          FeatureMuxedUnits,
 979                                                          FeatureCheckVLDnAlign,
 980                                                          FeatureVMLxForwarding,
 981                                                          FeatureFP16,
 982                                                          FeatureAvoidPartialCPSR,
 983                                                          FeatureVFP4,
 984                                                          FeatureHWDivThumb,
 985                                                          FeatureHWDivARM]>;
 986
 987 def : ProcessorModel<"swift",       SwiftModel,         [ARMv7a, ProcSwift,
 988                                                          FeatureHasRetAddrStack,
 989                                                          FeatureNEONForFP,
 990                                                          FeatureVFP4,
 991                                                          FeatureUseWideStrideVFP,
 992                                                          FeatureMP,
 993                                                          FeatureHWDivThumb,
 994                                                          FeatureHWDivARM,
 995                                                          FeatureAvoidPartialCPSR,
 996                                                          FeatureAvoidMOVsShOp,
 997                                                          FeatureHasSlowFPVMLx,
 998                                                          FeatureHasVMLxHazards,
 999                                                          FeatureProfUnpredicate,
1000                                                          FeaturePrefISHSTBarrier,
1001                                                          FeatureSlowOddRegister,
1002                                                          FeatureSlowLoadDSubreg,
1003                                                          FeatureSlowVGETLNi32,
1004                                                          FeatureSlowVDUP32,
1005                                                          FeatureUseMISched,
1006                                                          FeatureNoPostRASched]>;
1007
1008 def : ProcessorModel<"cortex-r4",   CortexA8Model,      [ARMv7r, ProcR4,
1009                                                          FeatureHasRetAddrStack,
1010                                                          FeatureAvoidPartialCPSR]>;
1011
1012 def : ProcessorModel<"cortex-r4f",  CortexA8Model,      [ARMv7r, ProcR4,
1013                                                          FeatureHasRetAddrStack,
1014                                                          FeatureSlowFPBrcc,
1015                                                          FeatureHasSlowFPVMLx,
1016                                                          FeatureVFP3_D16,
1017                                                          FeatureAvoidPartialCPSR]>;
1018
1019 def : ProcessorModel<"cortex-r5",   CortexA8Model,      [ARMv7r, ProcR5,
1020                                                          FeatureHasRetAddrStack,
1021                                                          FeatureVFP3_D16,
1022                                                          FeatureSlowFPBrcc,
1023                                                          FeatureHWDivARM,
1024                                                          FeatureHasSlowFPVMLx,
1025                                                          FeatureAvoidPartialCPSR]>;
1026
1027 def : ProcessorModel<"cortex-r7",   CortexA8Model,      [ARMv7r, ProcR7,
1028                                                          FeatureHasRetAddrStack,
1029                                                          FeatureVFP3_D16,
1030                                                          FeatureFP16,
1031                                                          FeatureMP,
1032                                                          FeatureSlowFPBrcc,
1033                                                          FeatureHWDivARM,
1034                                                          FeatureHasSlowFPVMLx,
1035                                                          FeatureAvoidPartialCPSR]>;
1036
1037 def : ProcessorModel<"cortex-r8",   CortexA8Model,      [ARMv7r,
1038                                                          FeatureHasRetAddrStack,
1039                                                          FeatureVFP3_D16,
1040                                                          FeatureFP16,
1041                                                          FeatureMP,
1042                                                          FeatureSlowFPBrcc,
1043                                                          FeatureHWDivARM,
1044                                                          FeatureHasSlowFPVMLx,
1045                                                          FeatureAvoidPartialCPSR]>;
1046
1047 def : ProcessorModel<"cortex-m3",   CortexM4Model,      [ARMv7m,
1048                                                          ProcM3,
1049                                                          FeaturePrefLoopAlign32,
1050                                                          FeatureUseMISched,
1051                                                          FeatureUseAA,
1052                                                          FeatureHasNoBranchPredictor]>;
1053
1054 def : ProcessorModel<"sc300",       CortexM4Model,      [ARMv7m,
1055                                                          ProcM3,
1056                                                          FeatureUseMISched,
1057                                                          FeatureUseAA,
1058                                                          FeatureHasNoBranchPredictor]>;
1059
1060 def : ProcessorModel<"cortex-m4", CortexM4Model,        [ARMv7em,
1061                                                          FeatureVFP4_D16_SP,
1062                                                          FeaturePrefLoopAlign32,
1063                                                          FeatureHasSlowFPVMLx,
1064                                                          FeatureUseMISched,
1065                                                          FeatureUseAA,
1066                                                          FeatureHasNoBranchPredictor]>;
1067
1068 def : ProcNoItin<"cortex-m7",                           [ARMv7em,
1069                                                          FeatureFPARMv8_D16]>;
1070
1071 def : ProcNoItin<"cortex-m23",                          [ARMv8mBaseline,
1072                                                          FeatureNoMovt]>;
1073
1074 def : ProcessorModel<"cortex-m33", CortexM4Model,       [ARMv8mMainline,
1075                                                          FeatureDSP,
1076                                                          FeatureFPARMv8_D16_SP,
1077                                                          FeaturePrefLoopAlign32,
1078                                                          FeatureHasSlowFPVMLx,
1079                                                          FeatureUseMISched,
1080                                                          FeatureUseAA,
1081                                                          FeatureHasNoBranchPredictor]>;
1082
1083 def : ProcessorModel<"cortex-m35p", CortexM4Model,      [ARMv8mMainline,
1084                                                          FeatureDSP,
1085                                                          FeatureFPARMv8_D16_SP,
1086                                                          FeaturePrefLoopAlign32,
1087                                                          FeatureHasSlowFPVMLx,
1088                                                          FeatureUseMISched,
1089                                                          FeatureUseAA,
1090                                                          FeatureHasNoBranchPredictor]>;
1091
1092
1093 def : ProcNoItin<"cortex-a32",                           [ARMv8a,
1094                                                          FeatureHWDivThumb,
1095                                                          FeatureHWDivARM,
1096                                                          FeatureCrypto,
1097                                                          FeatureCRC]>;
1098
1099 def : ProcNoItin<"cortex-a35",                          [ARMv8a, ProcA35,
1100                                                          FeatureHWDivThumb,
1101                                                          FeatureHWDivARM,
1102                                                          FeatureCrypto,
1103                                                          FeatureCRC]>;
1104
1105 def : ProcNoItin<"cortex-a53",                          [ARMv8a, ProcA53,
1106                                                          FeatureHWDivThumb,
1107                                                          FeatureHWDivARM,
1108                                                          FeatureCrypto,
1109                                                          FeatureCRC,
1110                                                          FeatureFPAO]>;
1111
1112 def : ProcNoItin<"cortex-a55",                          [ARMv82a, ProcA55,
1113                                                          FeatureHWDivThumb,
1114                                                          FeatureHWDivARM,
1115                                                          FeatureDotProd]>;
1116
1117 def : ProcessorModel<"cortex-a57",  CortexA57Model,     [ARMv8a, ProcA57,
1118                                                          FeatureHWDivThumb,
1119                                                          FeatureHWDivARM,
1120                                                          FeatureCrypto,
1121                                                          FeatureCRC,
1122                                                          FeatureFPAO,
1123                                                          FeatureAvoidPartialCPSR,
1124                                                          FeatureCheapPredicableCPSR]>;
1125
1126 def : ProcessorModel<"cortex-a72",  CortexA57Model,     [ARMv8a, ProcA72,
1127                                                          FeatureHWDivThumb,
1128                                                          FeatureHWDivARM,
1129                                                          FeatureCrypto,
1130                                                          FeatureCRC]>;
1131
1132 def : ProcNoItin<"cortex-a73",                          [ARMv8a, ProcA73,
1133                                                          FeatureHWDivThumb,
1134                                                          FeatureHWDivARM,
1135                                                          FeatureCrypto,
1136                                                          FeatureCRC]>;
1137
1138 def : ProcNoItin<"cortex-a75",                          [ARMv82a, ProcA75,
1139                                                          FeatureHWDivThumb,
1140                                                          FeatureHWDivARM,
1141                                                          FeatureDotProd]>;
1142
1143 def : ProcNoItin<"cortex-a76",                          [ARMv82a, ProcA76,
1144                                                          FeatureHWDivThumb,
1145                                                          FeatureHWDivARM,
1146                                                          FeatureCrypto,
1147                                                          FeatureCRC,
1148                                                          FeatureFullFP16,
1149                                                          FeatureDotProd]>;
1150
1151 def : ProcNoItin<"cortex-a76ae",                        [ARMv82a, ProcA76,
1152                                                          FeatureHWDivThumb,
1153                                                          FeatureHWDivARM,
1154                                                          FeatureCrypto,
1155                                                          FeatureCRC,
1156                                                          FeatureFullFP16,
1157                                                          FeatureDotProd]>;
1158
1159 def : ProcNoItin<"neoverse-n1",                         [ARMv82a,
1160                                                          FeatureHWDivThumb,
1161                                                          FeatureHWDivARM,
1162                                                          FeatureCrypto,
1163                                                          FeatureCRC,
1164                                                          FeatureDotProd]>;
1165
1166 def : ProcessorModel<"cyclone",     SwiftModel,         [ARMv8a, ProcSwift,
1167                                                          FeatureHasRetAddrStack,
1168                                                          FeatureNEONForFP,
1169                                                          FeatureVFP4,
1170                                                          FeatureMP,
1171                                                          FeatureHWDivThumb,
1172                                                          FeatureHWDivARM,
1173                                                          FeatureAvoidPartialCPSR,
1174                                                          FeatureAvoidMOVsShOp,
1175                                                          FeatureHasSlowFPVMLx,
1176                                                          FeatureCrypto,
1177                                                          FeatureUseMISched,
1178                                                          FeatureZCZeroing,
1179                                                          FeatureNoPostRASched]>;
1180
1181 def : ProcNoItin<"exynos-m1",                           [ARMv8a, ProcExynos]>;
1182 def : ProcNoItin<"exynos-m2",                           [ARMv8a, ProcExynos]>;
1183 def : ProcNoItin<"exynos-m3",                           [ARMv8a, ProcExynos]>;
1184 def : ProcNoItin<"exynos-m4",                           [ARMv82a, ProcExynos,
1185                                                          FeatureFullFP16,
1186                                                          FeatureDotProd]>;
1187 def : ProcNoItin<"exynos-m5",                           [ARMv82a, ProcExynos,
1188                                                          FeatureFullFP16,
1189                                                          FeatureDotProd]>;
1190
1191 def : ProcNoItin<"kryo",                                [ARMv8a, ProcKryo,
1192                                                          FeatureHWDivThumb,
1193                                                          FeatureHWDivARM,
1194                                                          FeatureCrypto,
1195                                                          FeatureCRC]>;
1196
1197 def : ProcessorModel<"cortex-r52", CortexR52Model,      [ARMv8r, ProcR52,
1198                                                          FeatureUseMISched,
1199                                                          FeatureFPAO,
1200                                                          FeatureUseAA]>;
1201
1202 //===----------------------------------------------------------------------===//
1203 // Register File Description
1204 //===----------------------------------------------------------------------===//
1205
1206 include "ARMRegisterInfo.td"
1207 include "ARMRegisterBanks.td"
1208 include "ARMCallingConv.td"
1209
1210 //===----------------------------------------------------------------------===//
1211 // Instruction Descriptions
1212 //===----------------------------------------------------------------------===//
1213
1214 include "ARMInstrInfo.td"
1215 def ARMInstrInfo : InstrInfo;
1216
1217 //===----------------------------------------------------------------------===//
1218 // Declare the target which we are implementing
1219 //===----------------------------------------------------------------------===//
1220
1221 def ARMAsmWriter : AsmWriter {
1222   string AsmWriterClassName  = "InstPrinter";
1223   int PassSubtarget = 1;
1224   int Variant = 0;
1225   bit isMCAsmWriter = 1;
1226 }
1227
1228 def ARMAsmParser : AsmParser {
1229   bit ReportMultipleNearMisses = 1;
1230 }
1231
1232 def ARMAsmParserVariant : AsmParserVariant {
1233   int Variant = 0;
1234   string Name = "ARM";
1235   string BreakCharacters = ".";
1236 }
1237
1238 def ARM : Target {
1239   // Pull in Instruction Info.
1240   let InstructionSet = ARMInstrInfo;
1241   let AssemblyWriters = [ARMAsmWriter];
1242   let AssemblyParsers = [ARMAsmParser];
1243   let AssemblyParserVariants = [ARMAsmParserVariant];
1244   let AllowRegisterRenaming = 1;
1245 }