1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
4 declare i4 @llvm.sadd.sat.i4(i4, i4)
5 declare i8 @llvm.sadd.sat.i8(i8, i8)
6 declare i16 @llvm.sadd.sat.i16(i16, i16)
7 declare i32 @llvm.sadd.sat.i32(i32, i32)
8 declare i64 @llvm.sadd.sat.i64(i64, i64)
9 declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32>, <4 x i32>)
11 define i32 @func(i32 %x, i32 %y) nounwind {
14 ; CHECK-NEXT: adds w8, w0, w1
15 ; CHECK-NEXT: mov w9, #2147483647
16 ; CHECK-NEXT: cmp w8, #0 // =0
17 ; CHECK-NEXT: cinv w8, w9, ge
18 ; CHECK-NEXT: adds w9, w0, w1
19 ; CHECK-NEXT: csel w0, w8, w9, vs
21 %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y);
25 define i64 @func2(i64 %x, i64 %y) nounwind {
28 ; CHECK-NEXT: adds x8, x0, x1
29 ; CHECK-NEXT: mov x9, #9223372036854775807
30 ; CHECK-NEXT: cmp x8, #0 // =0
31 ; CHECK-NEXT: cinv x8, x9, ge
32 ; CHECK-NEXT: adds x9, x0, x1
33 ; CHECK-NEXT: csel x0, x8, x9, vs
35 %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y);
39 define i16 @func16(i16 %x, i16 %y) nounwind {
40 ; CHECK-LABEL: func16:
42 ; CHECK-NEXT: lsl w8, w0, #16
43 ; CHECK-NEXT: adds w10, w8, w1, lsl #16
44 ; CHECK-NEXT: mov w9, #2147483647
45 ; CHECK-NEXT: cmp w10, #0 // =0
46 ; CHECK-NEXT: cinv w9, w9, ge
47 ; CHECK-NEXT: adds w8, w8, w1, lsl #16
48 ; CHECK-NEXT: csel w8, w9, w8, vs
49 ; CHECK-NEXT: asr w0, w8, #16
51 %tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %y);
55 define i8 @func8(i8 %x, i8 %y) nounwind {
58 ; CHECK-NEXT: lsl w8, w0, #24
59 ; CHECK-NEXT: adds w10, w8, w1, lsl #24
60 ; CHECK-NEXT: mov w9, #2147483647
61 ; CHECK-NEXT: cmp w10, #0 // =0
62 ; CHECK-NEXT: cinv w9, w9, ge
63 ; CHECK-NEXT: adds w8, w8, w1, lsl #24
64 ; CHECK-NEXT: csel w8, w9, w8, vs
65 ; CHECK-NEXT: asr w0, w8, #24
67 %tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %y);
71 define i4 @func3(i4 %x, i4 %y) nounwind {
74 ; CHECK-NEXT: lsl w8, w0, #28
75 ; CHECK-NEXT: adds w10, w8, w1, lsl #28
76 ; CHECK-NEXT: mov w9, #2147483647
77 ; CHECK-NEXT: cmp w10, #0 // =0
78 ; CHECK-NEXT: cinv w9, w9, ge
79 ; CHECK-NEXT: adds w8, w8, w1, lsl #28
80 ; CHECK-NEXT: csel w8, w9, w8, vs
81 ; CHECK-NEXT: asr w0, w8, #28
83 %tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y);
87 define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
90 ; CHECK-NEXT: add v2.4s, v0.4s, v1.4s
91 ; CHECK-NEXT: cmlt v4.4s, v2.4s, #0
92 ; CHECK-NEXT: mvni v3.4s, #128, lsl #24
93 ; CHECK-NEXT: cmlt v1.4s, v1.4s, #0
94 ; CHECK-NEXT: cmgt v0.4s, v0.4s, v2.4s
95 ; CHECK-NEXT: mvn v5.16b, v4.16b
96 ; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
97 ; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
98 ; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
100 %tmp = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y);