lib/Analysis/TargetTransformInfo.cpp

   1 //===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #include "llvm/Analysis/TargetTransformInfo.h"
  11 #include "llvm/Analysis/TargetTransformInfoImpl.h"
  12 #include "llvm/IR/CallSite.h"
  13 #include "llvm/IR/DataLayout.h"
  14 #include "llvm/IR/Instruction.h"
  15 #include "llvm/IR/Instructions.h"
  16 #include "llvm/IR/IntrinsicInst.h"
  17 #include "llvm/IR/Module.h"
  18 #include "llvm/IR/Operator.h"
  19 #include "llvm/IR/PatternMatch.h"
  20 #include "llvm/Support/CommandLine.h"
  21 #include "llvm/Support/ErrorHandling.h"
  22 #include <utility>
  23
  24 using namespace llvm;
  25 using namespace PatternMatch;
  26
  27 #define DEBUG_TYPE "tti"
  28
  29 static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
  30                                      cl::Hidden,
  31                                      cl::desc("Recognize reduction patterns."));
  32
  33 namespace {
  34 /// No-op implementation of the TTI interface using the utility base
  35 /// classes.
  36 ///
  37 /// This is used when no target specific information is available.
  38 struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
  39   explicit NoTTIImpl(const DataLayout &DL)
  40       : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
  41 };
  42 }
  43
  44 TargetTransformInfo::TargetTransformInfo(const DataLayout &DL)
  45     : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
  46
  47 TargetTransformInfo::~TargetTransformInfo() {}
  48
  49 TargetTransformInfo::TargetTransformInfo(TargetTransformInfo &&Arg)
  50     : TTIImpl(std::move(Arg.TTIImpl)) {}
  51
  52 TargetTransformInfo &TargetTransformInfo::operator=(TargetTransformInfo &&RHS) {
  53   TTIImpl = std::move(RHS.TTIImpl);
  54   return *this;
  55 }
  56
  57 int TargetTransformInfo::getOperationCost(unsigned Opcode, Type *Ty,
  58                                           Type *OpTy) const {
  59   int Cost = TTIImpl->getOperationCost(Opcode, Ty, OpTy);
  60   assert(Cost >= 0 && "TTI should not produce negative costs!");
  61   return Cost;
  62 }
  63
  64 int TargetTransformInfo::getCallCost(FunctionType *FTy, int NumArgs) const {
  65   int Cost = TTIImpl->getCallCost(FTy, NumArgs);
  66   assert(Cost >= 0 && "TTI should not produce negative costs!");
  67   return Cost;
  68 }
  69
  70 int TargetTransformInfo::getCallCost(const Function *F,
  71                                      ArrayRef<const Value *> Arguments) const {
  72   int Cost = TTIImpl->getCallCost(F, Arguments);
  73   assert(Cost >= 0 && "TTI should not produce negative costs!");
  74   return Cost;
  75 }
  76
  77 unsigned TargetTransformInfo::getInliningThresholdMultiplier() const {
  78   return TTIImpl->getInliningThresholdMultiplier();
  79 }
  80
  81 int TargetTransformInfo::getGEPCost(Type *PointeeType, const Value *Ptr,
  82                                     ArrayRef<const Value *> Operands) const {
  83   return TTIImpl->getGEPCost(PointeeType, Ptr, Operands);
  84 }
  85
  86 int TargetTransformInfo::getExtCost(const Instruction *I,
  87                                     const Value *Src) const {
  88   return TTIImpl->getExtCost(I, Src);
  89 }
  90
  91 int TargetTransformInfo::getIntrinsicCost(
  92     Intrinsic::ID IID, Type *RetTy, ArrayRef<const Value *> Arguments) const {
  93   int Cost = TTIImpl->getIntrinsicCost(IID, RetTy, Arguments);
  94   assert(Cost >= 0 && "TTI should not produce negative costs!");
  95   return Cost;
  96 }
  97
  98 unsigned
  99 TargetTransformInfo::getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
 100                                                       unsigned &JTSize) const {
 101   return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize);
 102 }
 103
 104 int TargetTransformInfo::getUserCost(const User *U,
 105     ArrayRef<const Value *> Operands) const {
 106   int Cost = TTIImpl->getUserCost(U, Operands);
 107   assert(Cost >= 0 && "TTI should not produce negative costs!");
 108   return Cost;
 109 }
 110
 111 bool TargetTransformInfo::hasBranchDivergence() const {
 112   return TTIImpl->hasBranchDivergence();
 113 }
 114
 115 bool TargetTransformInfo::isSourceOfDivergence(const Value *V) const {
 116   return TTIImpl->isSourceOfDivergence(V);
 117 }
 118
 119 bool llvm::TargetTransformInfo::isAlwaysUniform(const Value *V) const {
 120   return TTIImpl->isAlwaysUniform(V);
 121 }
 122
 123 unsigned TargetTransformInfo::getFlatAddressSpace() const {
 124   return TTIImpl->getFlatAddressSpace();
 125 }
 126
 127 bool TargetTransformInfo::isLoweredToCall(const Function *F) const {
 128   return TTIImpl->isLoweredToCall(F);
 129 }
 130
 131 void TargetTransformInfo::getUnrollingPreferences(
 132     Loop *L, ScalarEvolution &SE, UnrollingPreferences &UP) const {
 133   return TTIImpl->getUnrollingPreferences(L, SE, UP);
 134 }
 135
 136 bool TargetTransformInfo::isLegalAddImmediate(int64_t Imm) const {
 137   return TTIImpl->isLegalAddImmediate(Imm);
 138 }
 139
 140 bool TargetTransformInfo::isLegalICmpImmediate(int64_t Imm) const {
 141   return TTIImpl->isLegalICmpImmediate(Imm);
 142 }
 143
 144 bool TargetTransformInfo::isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
 145                                                 int64_t BaseOffset,
 146                                                 bool HasBaseReg,
 147                                                 int64_t Scale,
 148                                                 unsigned AddrSpace,
 149                                                 Instruction *I) const {
 150   return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
 151                                         Scale, AddrSpace, I);
 152 }
 153
 154 bool TargetTransformInfo::isLSRCostLess(LSRCost &C1, LSRCost &C2) const {
 155   return TTIImpl->isLSRCostLess(C1, C2);
 156 }
 157
 158 bool TargetTransformInfo::canMacroFuseCmp() const {
 159   return TTIImpl->canMacroFuseCmp();
 160 }
 161
 162 bool TargetTransformInfo::shouldFavorPostInc() const {
 163   return TTIImpl->shouldFavorPostInc();
 164 }
 165
 166 bool TargetTransformInfo::isLegalMaskedStore(Type *DataType) const {
 167   return TTIImpl->isLegalMaskedStore(DataType);
 168 }
 169
 170 bool TargetTransformInfo::isLegalMaskedLoad(Type *DataType) const {
 171   return TTIImpl->isLegalMaskedLoad(DataType);
 172 }
 173
 174 bool TargetTransformInfo::isLegalMaskedGather(Type *DataType) const {
 175   return TTIImpl->isLegalMaskedGather(DataType);
 176 }
 177
 178 bool TargetTransformInfo::isLegalMaskedScatter(Type *DataType) const {
 179   return TTIImpl->isLegalMaskedScatter(DataType);
 180 }
 181
 182 bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
 183   return TTIImpl->hasDivRemOp(DataType, IsSigned);
 184 }
 185
 186 bool TargetTransformInfo::hasVolatileVariant(Instruction *I,
 187                                              unsigned AddrSpace) const {
 188   return TTIImpl->hasVolatileVariant(I, AddrSpace);
 189 }
 190
 191 bool TargetTransformInfo::prefersVectorizedAddressing() const {
 192   return TTIImpl->prefersVectorizedAddressing();
 193 }
 194
 195 int TargetTransformInfo::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
 196                                               int64_t BaseOffset,
 197                                               bool HasBaseReg,
 198                                               int64_t Scale,
 199                                               unsigned AddrSpace) const {
 200   int Cost = TTIImpl->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg,
 201                                            Scale, AddrSpace);
 202   assert(Cost >= 0 && "TTI should not produce negative costs!");
 203   return Cost;
 204 }
 205
 206 bool TargetTransformInfo::LSRWithInstrQueries() const {
 207   return TTIImpl->LSRWithInstrQueries();
 208 }
 209
 210 bool TargetTransformInfo::isTruncateFree(Type *Ty1, Type *Ty2) const {
 211   return TTIImpl->isTruncateFree(Ty1, Ty2);
 212 }
 213
 214 bool TargetTransformInfo::isProfitableToHoist(Instruction *I) const {
 215   return TTIImpl->isProfitableToHoist(I);
 216 }
 217
 218 bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
 219
 220 bool TargetTransformInfo::isTypeLegal(Type *Ty) const {
 221   return TTIImpl->isTypeLegal(Ty);
 222 }
 223
 224 unsigned TargetTransformInfo::getJumpBufAlignment() const {
 225   return TTIImpl->getJumpBufAlignment();
 226 }
 227
 228 unsigned TargetTransformInfo::getJumpBufSize() const {
 229   return TTIImpl->getJumpBufSize();
 230 }
 231
 232 bool TargetTransformInfo::shouldBuildLookupTables() const {
 233   return TTIImpl->shouldBuildLookupTables();
 234 }
 235 bool TargetTransformInfo::shouldBuildLookupTablesForConstant(Constant *C) const {
 236   return TTIImpl->shouldBuildLookupTablesForConstant(C);
 237 }
 238
 239 bool TargetTransformInfo::useColdCCForColdCall(Function &F) const {
 240   return TTIImpl->useColdCCForColdCall(F);
 241 }
 242
 243 unsigned TargetTransformInfo::
 244 getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const {
 245   return TTIImpl->getScalarizationOverhead(Ty, Insert, Extract);
 246 }
 247
 248 unsigned TargetTransformInfo::
 249 getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
 250                                  unsigned VF) const {
 251   return TTIImpl->getOperandsScalarizationOverhead(Args, VF);
 252 }
 253
 254 bool TargetTransformInfo::supportsEfficientVectorElementLoadStore() const {
 255   return TTIImpl->supportsEfficientVectorElementLoadStore();
 256 }
 257
 258 bool TargetTransformInfo::enableAggressiveInterleaving(bool LoopHasReductions) const {
 259   return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
 260 }
 261
 262 const TargetTransformInfo::MemCmpExpansionOptions *
 263 TargetTransformInfo::enableMemCmpExpansion(bool IsZeroCmp) const {
 264   return TTIImpl->enableMemCmpExpansion(IsZeroCmp);
 265 }
 266
 267 bool TargetTransformInfo::enableInterleavedAccessVectorization() const {
 268   return TTIImpl->enableInterleavedAccessVectorization();
 269 }
 270
 271 bool TargetTransformInfo::enableMaskedInterleavedAccessVectorization() const {
 272   return TTIImpl->enableMaskedInterleavedAccessVectorization();
 273 }
 274
 275 bool TargetTransformInfo::isFPVectorizationPotentiallyUnsafe() const {
 276   return TTIImpl->isFPVectorizationPotentiallyUnsafe();
 277 }
 278
 279 bool TargetTransformInfo::allowsMisalignedMemoryAccesses(LLVMContext &Context,
 280                                                          unsigned BitWidth,
 281                                                          unsigned AddressSpace,
 282                                                          unsigned Alignment,
 283                                                          bool *Fast) const {
 284   return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth, AddressSpace,
 285                                                  Alignment, Fast);
 286 }
 287
 288 TargetTransformInfo::PopcntSupportKind
 289 TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
 290   return TTIImpl->getPopcntSupport(IntTyWidthInBit);
 291 }
 292
 293 bool TargetTransformInfo::haveFastSqrt(Type *Ty) const {
 294   return TTIImpl->haveFastSqrt(Ty);
 295 }
 296
 297 bool TargetTransformInfo::isFCmpOrdCheaperThanFCmpZero(Type *Ty) const {
 298   return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
 299 }
 300
 301 int TargetTransformInfo::getFPOpCost(Type *Ty) const {
 302   int Cost = TTIImpl->getFPOpCost(Ty);
 303   assert(Cost >= 0 && "TTI should not produce negative costs!");
 304   return Cost;
 305 }
 306
 307 int TargetTransformInfo::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
 308                                                const APInt &Imm,
 309                                                Type *Ty) const {
 310   int Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
 311   assert(Cost >= 0 && "TTI should not produce negative costs!");
 312   return Cost;
 313 }
 314
 315 int TargetTransformInfo::getIntImmCost(const APInt &Imm, Type *Ty) const {
 316   int Cost = TTIImpl->getIntImmCost(Imm, Ty);
 317   assert(Cost >= 0 && "TTI should not produce negative costs!");
 318   return Cost;
 319 }
 320
 321 int TargetTransformInfo::getIntImmCost(unsigned Opcode, unsigned Idx,
 322                                        const APInt &Imm, Type *Ty) const {
 323   int Cost = TTIImpl->getIntImmCost(Opcode, Idx, Imm, Ty);
 324   assert(Cost >= 0 && "TTI should not produce negative costs!");
 325   return Cost;
 326 }
 327
 328 int TargetTransformInfo::getIntImmCost(Intrinsic::ID IID, unsigned Idx,
 329                                        const APInt &Imm, Type *Ty) const {
 330   int Cost = TTIImpl->getIntImmCost(IID, Idx, Imm, Ty);
 331   assert(Cost >= 0 && "TTI should not produce negative costs!");
 332   return Cost;
 333 }
 334
 335 unsigned TargetTransformInfo::getNumberOfRegisters(bool Vector) const {
 336   return TTIImpl->getNumberOfRegisters(Vector);
 337 }
 338
 339 unsigned TargetTransformInfo::getRegisterBitWidth(bool Vector) const {
 340   return TTIImpl->getRegisterBitWidth(Vector);
 341 }
 342
 343 unsigned TargetTransformInfo::getMinVectorRegisterBitWidth() const {
 344   return TTIImpl->getMinVectorRegisterBitWidth();
 345 }
 346
 347 bool TargetTransformInfo::shouldMaximizeVectorBandwidth(bool OptSize) const {
 348   return TTIImpl->shouldMaximizeVectorBandwidth(OptSize);
 349 }
 350
 351 unsigned TargetTransformInfo::getMinimumVF(unsigned ElemWidth) const {
 352   return TTIImpl->getMinimumVF(ElemWidth);
 353 }
 354
 355 bool TargetTransformInfo::shouldConsiderAddressTypePromotion(
 356     const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
 357   return TTIImpl->shouldConsiderAddressTypePromotion(
 358       I, AllowPromotionWithoutCommonHeader);
 359 }
 360
 361 unsigned TargetTransformInfo::getCacheLineSize() const {
 362   return TTIImpl->getCacheLineSize();
 363 }
 364
 365 llvm::Optional<unsigned> TargetTransformInfo::getCacheSize(CacheLevel Level)
 366   const {
 367   return TTIImpl->getCacheSize(Level);
 368 }
 369
 370 llvm::Optional<unsigned> TargetTransformInfo::getCacheAssociativity(
 371   CacheLevel Level) const {
 372   return TTIImpl->getCacheAssociativity(Level);
 373 }
 374
 375 unsigned TargetTransformInfo::getPrefetchDistance() const {
 376   return TTIImpl->getPrefetchDistance();
 377 }
 378
 379 unsigned TargetTransformInfo::getMinPrefetchStride() const {
 380   return TTIImpl->getMinPrefetchStride();
 381 }
 382
 383 unsigned TargetTransformInfo::getMaxPrefetchIterationsAhead() const {
 384   return TTIImpl->getMaxPrefetchIterationsAhead();
 385 }
 386
 387 unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
 388   return TTIImpl->getMaxInterleaveFactor(VF);
 389 }
 390
 391 TargetTransformInfo::OperandValueKind
 392 TargetTransformInfo::getOperandInfo(Value *V,
 393                                     OperandValueProperties &OpProps) const {
 394   OperandValueKind OpInfo = OK_AnyValue;
 395   OpProps = OP_None;
 396
 397   if (auto *CI = dyn_cast<ConstantInt>(V)) {
 398     if (CI->getValue().isPowerOf2())
 399       OpProps = OP_PowerOf2;
 400     return OK_UniformConstantValue;
 401   }
 402
 403   const Value *Splat = getSplatValue(V);
 404
 405   // Check for a splat of a constant or for a non uniform vector of constants
 406   // and check if the constant(s) are all powers of two.
 407   if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
 408     OpInfo = OK_NonUniformConstantValue;
 409     if (Splat) {
 410       OpInfo = OK_UniformConstantValue;
 411       if (auto *CI = dyn_cast<ConstantInt>(Splat))
 412         if (CI->getValue().isPowerOf2())
 413           OpProps = OP_PowerOf2;
 414     } else if (auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
 415       OpProps = OP_PowerOf2;
 416       for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
 417         if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I)))
 418           if (CI->getValue().isPowerOf2())
 419             continue;
 420         OpProps = OP_None;
 421         break;
 422       }
 423     }
 424   }
 425
 426   // Check for a splat of a uniform value. This is not loop aware, so return
 427   // true only for the obviously uniform cases (argument, globalvalue)
 428   if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
 429     OpInfo = OK_UniformValue;
 430
 431   return OpInfo;
 432 }
 433
 434 int TargetTransformInfo::getArithmeticInstrCost(
 435     unsigned Opcode, Type *Ty, OperandValueKind Opd1Info,
 436     OperandValueKind Opd2Info, OperandValueProperties Opd1PropInfo,
 437     OperandValueProperties Opd2PropInfo,
 438     ArrayRef<const Value *> Args) const {
 439   int Cost = TTIImpl->getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
 440                                              Opd1PropInfo, Opd2PropInfo, Args);
 441   assert(Cost >= 0 && "TTI should not produce negative costs!");
 442   return Cost;
 443 }
 444
 445 int TargetTransformInfo::getShuffleCost(ShuffleKind Kind, Type *Ty, int Index,
 446                                         Type *SubTp) const {
 447   int Cost = TTIImpl->getShuffleCost(Kind, Ty, Index, SubTp);
 448   assert(Cost >= 0 && "TTI should not produce negative costs!");
 449   return Cost;
 450 }
 451
 452 int TargetTransformInfo::getCastInstrCost(unsigned Opcode, Type *Dst,
 453                                  Type *Src, const Instruction *I) const {
 454   assert ((I == nullptr || I->getOpcode() == Opcode) &&
 455           "Opcode should reflect passed instruction.");
 456   int Cost = TTIImpl->getCastInstrCost(Opcode, Dst, Src, I);
 457   assert(Cost >= 0 && "TTI should not produce negative costs!");
 458   return Cost;
 459 }
 460
 461 int TargetTransformInfo::getExtractWithExtendCost(unsigned Opcode, Type *Dst,
 462                                                   VectorType *VecTy,
 463                                                   unsigned Index) const {
 464   int Cost = TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
 465   assert(Cost >= 0 && "TTI should not produce negative costs!");
 466   return Cost;
 467 }
 468
 469 int TargetTransformInfo::getCFInstrCost(unsigned Opcode) const {
 470   int Cost = TTIImpl->getCFInstrCost(Opcode);
 471   assert(Cost >= 0 && "TTI should not produce negative costs!");
 472   return Cost;
 473 }
 474
 475 int TargetTransformInfo::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
 476                                  Type *CondTy, const Instruction *I) const {
 477   assert ((I == nullptr || I->getOpcode() == Opcode) &&
 478           "Opcode should reflect passed instruction.");
 479   int Cost = TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
 480   assert(Cost >= 0 && "TTI should not produce negative costs!");
 481   return Cost;
 482 }
 483
 484 int TargetTransformInfo::getVectorInstrCost(unsigned Opcode, Type *Val,
 485                                             unsigned Index) const {
 486   int Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index);
 487   assert(Cost >= 0 && "TTI should not produce negative costs!");
 488   return Cost;
 489 }
 490
 491 int TargetTransformInfo::getMemoryOpCost(unsigned Opcode, Type *Src,
 492                                          unsigned Alignment,
 493                                          unsigned AddressSpace,
 494                                          const Instruction *I) const {
 495   assert ((I == nullptr || I->getOpcode() == Opcode) &&
 496           "Opcode should reflect passed instruction.");
 497   int Cost = TTIImpl->getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, I);
 498   assert(Cost >= 0 && "TTI should not produce negative costs!");
 499   return Cost;
 500 }
 501
 502 int TargetTransformInfo::getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
 503                                                unsigned Alignment,
 504                                                unsigned AddressSpace) const {
 505   int Cost =
 506       TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
 507   assert(Cost >= 0 && "TTI should not produce negative costs!");
 508   return Cost;
 509 }
 510
 511 int TargetTransformInfo::getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
 512                                                 Value *Ptr, bool VariableMask,
 513                                                 unsigned Alignment) const {
 514   int Cost = TTIImpl->getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
 515                                              Alignment);
 516   assert(Cost >= 0 && "TTI should not produce negative costs!");
 517   return Cost;
 518 }
 519
 520 int TargetTransformInfo::getInterleavedMemoryOpCost(
 521     unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
 522     unsigned Alignment, unsigned AddressSpace, bool IsMasked) const {
 523   int Cost = TTIImpl->getInterleavedMemoryOpCost(
 524       Opcode, VecTy, Factor, Indices, Alignment, AddressSpace, IsMasked);
 525   assert(Cost >= 0 && "TTI should not produce negative costs!");
 526   return Cost;
 527 }
 528
 529 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
 530                                     ArrayRef<Type *> Tys, FastMathFlags FMF,
 531                                     unsigned ScalarizationCostPassed) const {
 532   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Tys, FMF,
 533                                             ScalarizationCostPassed);
 534   assert(Cost >= 0 && "TTI should not produce negative costs!");
 535   return Cost;
 536 }
 537
 538 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
 539            ArrayRef<Value *> Args, FastMathFlags FMF, unsigned VF) const {
 540   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Args, FMF, VF);
 541   assert(Cost >= 0 && "TTI should not produce negative costs!");
 542   return Cost;
 543 }
 544
 545 int TargetTransformInfo::getCallInstrCost(Function *F, Type *RetTy,
 546                                           ArrayRef<Type *> Tys) const {
 547   int Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys);
 548   assert(Cost >= 0 && "TTI should not produce negative costs!");
 549   return Cost;
 550 }
 551
 552 unsigned TargetTransformInfo::getNumberOfParts(Type *Tp) const {
 553   return TTIImpl->getNumberOfParts(Tp);
 554 }
 555
 556 int TargetTransformInfo::getAddressComputationCost(Type *Tp,
 557                                                    ScalarEvolution *SE,
 558                                                    const SCEV *Ptr) const {
 559   int Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
 560   assert(Cost >= 0 && "TTI should not produce negative costs!");
 561   return Cost;
 562 }
 563
 564 int TargetTransformInfo::getArithmeticReductionCost(unsigned Opcode, Type *Ty,
 565                                                     bool IsPairwiseForm) const {
 566   int Cost = TTIImpl->getArithmeticReductionCost(Opcode, Ty, IsPairwiseForm);
 567   assert(Cost >= 0 && "TTI should not produce negative costs!");
 568   return Cost;
 569 }
 570
 571 int TargetTransformInfo::getMinMaxReductionCost(Type *Ty, Type *CondTy,
 572                                                 bool IsPairwiseForm,
 573                                                 bool IsUnsigned) const {
 574   int Cost =
 575       TTIImpl->getMinMaxReductionCost(Ty, CondTy, IsPairwiseForm, IsUnsigned);
 576   assert(Cost >= 0 && "TTI should not produce negative costs!");
 577   return Cost;
 578 }
 579
 580 unsigned
 581 TargetTransformInfo::getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) const {
 582   return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
 583 }
 584
 585 bool TargetTransformInfo::getTgtMemIntrinsic(IntrinsicInst *Inst,
 586                                              MemIntrinsicInfo &Info) const {
 587   return TTIImpl->getTgtMemIntrinsic(Inst, Info);
 588 }
 589
 590 unsigned TargetTransformInfo::getAtomicMemIntrinsicMaxElementSize() const {
 591   return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
 592 }
 593
 594 Value *TargetTransformInfo::getOrCreateResultFromMemIntrinsic(
 595     IntrinsicInst *Inst, Type *ExpectedType) const {
 596   return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
 597 }
 598
 599 Type *TargetTransformInfo::getMemcpyLoopLoweringType(LLVMContext &Context,
 600                                                      Value *Length,
 601                                                      unsigned SrcAlign,
 602                                                      unsigned DestAlign) const {
 603   return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAlign,
 604                                             DestAlign);
 605 }
 606
 607 void TargetTransformInfo::getMemcpyLoopResidualLoweringType(
 608     SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
 609     unsigned RemainingBytes, unsigned SrcAlign, unsigned DestAlign) const {
 610   TTIImpl->getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes,
 611                                              SrcAlign, DestAlign);
 612 }
 613
 614 bool TargetTransformInfo::areInlineCompatible(const Function *Caller,
 615                                               const Function *Callee) const {
 616   return TTIImpl->areInlineCompatible(Caller, Callee);
 617 }
 618
 619 bool TargetTransformInfo::isIndexedLoadLegal(MemIndexedMode Mode,
 620                                              Type *Ty) const {
 621   return TTIImpl->isIndexedLoadLegal(Mode, Ty);
 622 }
 623
 624 bool TargetTransformInfo::isIndexedStoreLegal(MemIndexedMode Mode,
 625                                               Type *Ty) const {
 626   return TTIImpl->isIndexedStoreLegal(Mode, Ty);
 627 }
 628
 629 unsigned TargetTransformInfo::getLoadStoreVecRegBitWidth(unsigned AS) const {
 630   return TTIImpl->getLoadStoreVecRegBitWidth(AS);
 631 }
 632
 633 bool TargetTransformInfo::isLegalToVectorizeLoad(LoadInst *LI) const {
 634   return TTIImpl->isLegalToVectorizeLoad(LI);
 635 }
 636
 637 bool TargetTransformInfo::isLegalToVectorizeStore(StoreInst *SI) const {
 638   return TTIImpl->isLegalToVectorizeStore(SI);
 639 }
 640
 641 bool TargetTransformInfo::isLegalToVectorizeLoadChain(
 642     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
 643   return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
 644                                               AddrSpace);
 645 }
 646
 647 bool TargetTransformInfo::isLegalToVectorizeStoreChain(
 648     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
 649   return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
 650                                                AddrSpace);
 651 }
 652
 653 unsigned TargetTransformInfo::getLoadVectorFactor(unsigned VF,
 654                                                   unsigned LoadSize,
 655                                                   unsigned ChainSizeInBytes,
 656                                                   VectorType *VecTy) const {
 657   return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
 658 }
 659
 660 unsigned TargetTransformInfo::getStoreVectorFactor(unsigned VF,
 661                                                    unsigned StoreSize,
 662                                                    unsigned ChainSizeInBytes,
 663                                                    VectorType *VecTy) const {
 664   return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
 665 }
 666
 667 bool TargetTransformInfo::useReductionIntrinsic(unsigned Opcode,
 668                                                 Type *Ty, ReductionFlags Flags) const {
 669   return TTIImpl->useReductionIntrinsic(Opcode, Ty, Flags);
 670 }
 671
 672 bool TargetTransformInfo::shouldExpandReduction(const IntrinsicInst *II) const {
 673   return TTIImpl->shouldExpandReduction(II);
 674 }
 675
 676 int TargetTransformInfo::getInstructionLatency(const Instruction *I) const {
 677   return TTIImpl->getInstructionLatency(I);
 678 }
 679
 680 static bool matchPairwiseShuffleMask(ShuffleVectorInst *SI, bool IsLeft,
 681                                      unsigned Level) {
 682   // We don't need a shuffle if we just want to have element 0 in position 0 of
 683   // the vector.
 684   if (!SI && Level == 0 && IsLeft)
 685     return true;
 686   else if (!SI)
 687     return false;
 688
 689   SmallVector<int, 32> Mask(SI->getType()->getVectorNumElements(), -1);
 690
 691   // Build a mask of 0, 2, ... (left) or 1, 3, ... (right) depending on whether
 692   // we look at the left or right side.
 693   for (unsigned i = 0, e = (1 << Level), val = !IsLeft; i != e; ++i, val += 2)
 694     Mask[i] = val;
 695
 696   SmallVector<int, 16> ActualMask = SI->getShuffleMask();
 697   return Mask == ActualMask;
 698 }
 699
 700 namespace {
 701 /// Kind of the reduction data.
 702 enum ReductionKind {
 703   RK_None,           /// Not a reduction.
 704   RK_Arithmetic,     /// Binary reduction data.
 705   RK_MinMax,         /// Min/max reduction data.
 706   RK_UnsignedMinMax, /// Unsigned min/max reduction data.
 707 };
 708 /// Contains opcode + LHS/RHS parts of the reduction operations.
 709 struct ReductionData {
 710   ReductionData() = delete;
 711   ReductionData(ReductionKind Kind, unsigned Opcode, Value *LHS, Value *RHS)
 712       : Opcode(Opcode), LHS(LHS), RHS(RHS), Kind(Kind) {
 713     assert(Kind != RK_None && "expected binary or min/max reduction only.");
 714   }
 715   unsigned Opcode = 0;
 716   Value *LHS = nullptr;
 717   Value *RHS = nullptr;
 718   ReductionKind Kind = RK_None;
 719   bool hasSameData(ReductionData &RD) const {
 720     return Kind == RD.Kind && Opcode == RD.Opcode;
 721   }
 722 };
 723 } // namespace
 724
 725 static Optional<ReductionData> getReductionData(Instruction *I) {
 726   Value *L, *R;
 727   if (m_BinOp(m_Value(L), m_Value(R)).match(I))
 728     return ReductionData(RK_Arithmetic, I->getOpcode(), L, R);
 729   if (auto *SI = dyn_cast<SelectInst>(I)) {
 730     if (m_SMin(m_Value(L), m_Value(R)).match(SI) ||
 731         m_SMax(m_Value(L), m_Value(R)).match(SI) ||
 732         m_OrdFMin(m_Value(L), m_Value(R)).match(SI) ||
 733         m_OrdFMax(m_Value(L), m_Value(R)).match(SI) ||
 734         m_UnordFMin(m_Value(L), m_Value(R)).match(SI) ||
 735         m_UnordFMax(m_Value(L), m_Value(R)).match(SI)) {
 736       auto *CI = cast<CmpInst>(SI->getCondition());
 737       return ReductionData(RK_MinMax, CI->getOpcode(), L, R);
 738     }
 739     if (m_UMin(m_Value(L), m_Value(R)).match(SI) ||
 740         m_UMax(m_Value(L), m_Value(R)).match(SI)) {
 741       auto *CI = cast<CmpInst>(SI->getCondition());
 742       return ReductionData(RK_UnsignedMinMax, CI->getOpcode(), L, R);
 743     }
 744   }
 745   return llvm::None;
 746 }
 747
 748 static ReductionKind matchPairwiseReductionAtLevel(Instruction *I,
 749                                                    unsigned Level,
 750                                                    unsigned NumLevels) {
 751   // Match one level of pairwise operations.
 752   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
 753   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
 754   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
 755   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
 756   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
 757   if (!I)
 758     return RK_None;
 759
 760   assert(I->getType()->isVectorTy() && "Expecting a vector type");
 761
 762   Optional<ReductionData> RD = getReductionData(I);
 763   if (!RD)
 764     return RK_None;
 765
 766   ShuffleVectorInst *LS = dyn_cast<ShuffleVectorInst>(RD->LHS);
 767   if (!LS && Level)
 768     return RK_None;
 769   ShuffleVectorInst *RS = dyn_cast<ShuffleVectorInst>(RD->RHS);
 770   if (!RS && Level)
 771     return RK_None;
 772
 773   // On level 0 we can omit one shufflevector instruction.
 774   if (!Level && !RS && !LS)
 775     return RK_None;
 776
 777   // Shuffle inputs must match.
 778   Value *NextLevelOpL = LS ? LS->getOperand(0) : nullptr;
 779   Value *NextLevelOpR = RS ? RS->getOperand(0) : nullptr;
 780   Value *NextLevelOp = nullptr;
 781   if (NextLevelOpR && NextLevelOpL) {
 782     // If we have two shuffles their operands must match.
 783     if (NextLevelOpL != NextLevelOpR)
 784       return RK_None;
 785
 786     NextLevelOp = NextLevelOpL;
 787   } else if (Level == 0 && (NextLevelOpR || NextLevelOpL)) {
 788     // On the first level we can omit the shufflevector <0, undef,...>. So the
 789     // input to the other shufflevector <1, undef> must match with one of the
 790     // inputs to the current binary operation.
 791     // Example:
 792     //  %NextLevelOpL = shufflevector %R, <1, undef ...>
 793     //  %BinOp        = fadd          %NextLevelOpL, %R
 794     if (NextLevelOpL && NextLevelOpL != RD->RHS)
 795       return RK_None;
 796     else if (NextLevelOpR && NextLevelOpR != RD->LHS)
 797       return RK_None;
 798
 799     NextLevelOp = NextLevelOpL ? RD->RHS : RD->LHS;
 800   } else
 801     return RK_None;
 802
 803   // Check that the next levels binary operation exists and matches with the
 804   // current one.
 805   if (Level + 1 != NumLevels) {
 806     Optional<ReductionData> NextLevelRD =
 807         getReductionData(cast<Instruction>(NextLevelOp));
 808     if (!NextLevelRD || !RD->hasSameData(*NextLevelRD))
 809       return RK_None;
 810   }
 811
 812   // Shuffle mask for pairwise operation must match.
 813   if (matchPairwiseShuffleMask(LS, /*IsLeft=*/true, Level)) {
 814     if (!matchPairwiseShuffleMask(RS, /*IsLeft=*/false, Level))
 815       return RK_None;
 816   } else if (matchPairwiseShuffleMask(RS, /*IsLeft=*/true, Level)) {
 817     if (!matchPairwiseShuffleMask(LS, /*IsLeft=*/false, Level))
 818       return RK_None;
 819   } else {
 820     return RK_None;
 821   }
 822
 823   if (++Level == NumLevels)
 824     return RD->Kind;
 825
 826   // Match next level.
 827   return matchPairwiseReductionAtLevel(cast<Instruction>(NextLevelOp), Level,
 828                                        NumLevels);
 829 }
 830
 831 static ReductionKind matchPairwiseReduction(const ExtractElementInst *ReduxRoot,
 832                                             unsigned &Opcode, Type *&Ty) {
 833   if (!EnableReduxCost)
 834     return RK_None;
 835
 836   // Need to extract the first element.
 837   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
 838   unsigned Idx = ~0u;
 839   if (CI)
 840     Idx = CI->getZExtValue();
 841   if (Idx != 0)
 842     return RK_None;
 843
 844   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
 845   if (!RdxStart)
 846     return RK_None;
 847   Optional<ReductionData> RD = getReductionData(RdxStart);
 848   if (!RD)
 849     return RK_None;
 850
 851   Type *VecTy = RdxStart->getType();
 852   unsigned NumVecElems = VecTy->getVectorNumElements();
 853   if (!isPowerOf2_32(NumVecElems))
 854     return RK_None;
 855
 856   // We look for a sequence of shuffle,shuffle,add triples like the following
 857   // that builds a pairwise reduction tree.
 858   //
 859   //  (X0, X1, X2, X3)
 860   //   (X0 + X1, X2 + X3, undef, undef)
 861   //    ((X0 + X1) + (X2 + X3), undef, undef, undef)
 862   //
 863   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
 864   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
 865   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
 866   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
 867   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
 868   // %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
 869   //       <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
 870   // %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
 871   //       <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
 872   // %bin.rdx8 = fadd <4 x float> %rdx.shuf.1.0, %rdx.shuf.1.1
 873   // %r = extractelement <4 x float> %bin.rdx8, i32 0
 874   if (matchPairwiseReductionAtLevel(RdxStart, 0, Log2_32(NumVecElems)) ==
 875       RK_None)
 876     return RK_None;
 877
 878   Opcode = RD->Opcode;
 879   Ty = VecTy;
 880
 881   return RD->Kind;
 882 }
 883
 884 static std::pair<Value *, ShuffleVectorInst *>
 885 getShuffleAndOtherOprd(Value *L, Value *R) {
 886   ShuffleVectorInst *S = nullptr;
 887
 888   if ((S = dyn_cast<ShuffleVectorInst>(L)))
 889     return std::make_pair(R, S);
 890
 891   S = dyn_cast<ShuffleVectorInst>(R);
 892   return std::make_pair(L, S);
 893 }
 894
 895 static ReductionKind
 896 matchVectorSplittingReduction(const ExtractElementInst *ReduxRoot,
 897                               unsigned &Opcode, Type *&Ty) {
 898   if (!EnableReduxCost)
 899     return RK_None;
 900
 901   // Need to extract the first element.
 902   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
 903   unsigned Idx = ~0u;
 904   if (CI)
 905     Idx = CI->getZExtValue();
 906   if (Idx != 0)
 907     return RK_None;
 908
 909   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
 910   if (!RdxStart)
 911     return RK_None;
 912   Optional<ReductionData> RD = getReductionData(RdxStart);
 913   if (!RD)
 914     return RK_None;
 915
 916   Type *VecTy = ReduxRoot->getOperand(0)->getType();
 917   unsigned NumVecElems = VecTy->getVectorNumElements();
 918   if (!isPowerOf2_32(NumVecElems))
 919     return RK_None;
 920
 921   // We look for a sequence of shuffles and adds like the following matching one
 922   // fadd, shuffle vector pair at a time.
 923   //
 924   // %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef,
 925   //                           <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
 926   // %bin.rdx = fadd <4 x float> %rdx, %rdx.shuf
 927   // %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef,
 928   //                          <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
 929   // %bin.rdx8 = fadd <4 x float> %bin.rdx, %rdx.shuf7
 930   // %r = extractelement <4 x float> %bin.rdx8, i32 0
 931
 932   unsigned MaskStart = 1;
 933   Instruction *RdxOp = RdxStart;
 934   SmallVector<int, 32> ShuffleMask(NumVecElems, 0);
 935   unsigned NumVecElemsRemain = NumVecElems;
 936   while (NumVecElemsRemain - 1) {
 937     // Check for the right reduction operation.
 938     if (!RdxOp)
 939       return RK_None;
 940     Optional<ReductionData> RDLevel = getReductionData(RdxOp);
 941     if (!RDLevel || !RDLevel->hasSameData(*RD))
 942       return RK_None;
 943
 944     Value *NextRdxOp;
 945     ShuffleVectorInst *Shuffle;
 946     std::tie(NextRdxOp, Shuffle) =
 947         getShuffleAndOtherOprd(RDLevel->LHS, RDLevel->RHS);
 948
 949     // Check the current reduction operation and the shuffle use the same value.
 950     if (Shuffle == nullptr)
 951       return RK_None;
 952     if (Shuffle->getOperand(0) != NextRdxOp)
 953       return RK_None;
 954
 955     // Check that shuffle masks matches.
 956     for (unsigned j = 0; j != MaskStart; ++j)
 957       ShuffleMask[j] = MaskStart + j;
 958     // Fill the rest of the mask with -1 for undef.
 959     std::fill(&ShuffleMask[MaskStart], ShuffleMask.end(), -1);
 960
 961     SmallVector<int, 16> Mask = Shuffle->getShuffleMask();
 962     if (ShuffleMask != Mask)
 963       return RK_None;
 964
 965     RdxOp = dyn_cast<Instruction>(NextRdxOp);
 966     NumVecElemsRemain /= 2;
 967     MaskStart *= 2;
 968   }
 969
 970   Opcode = RD->Opcode;
 971   Ty = VecTy;
 972   return RD->Kind;
 973 }
 974
 975 int TargetTransformInfo::getInstructionThroughput(const Instruction *I) const {
 976   switch (I->getOpcode()) {
 977   case Instruction::GetElementPtr:
 978     return getUserCost(I);
 979
 980   case Instruction::Ret:
 981   case Instruction::PHI:
 982   case Instruction::Br: {
 983     return getCFInstrCost(I->getOpcode());
 984   }
 985   case Instruction::Add:
 986   case Instruction::FAdd:
 987   case Instruction::Sub:
 988   case Instruction::FSub:
 989   case Instruction::Mul:
 990   case Instruction::FMul:
 991   case Instruction::UDiv:
 992   case Instruction::SDiv:
 993   case Instruction::FDiv:
 994   case Instruction::URem:
 995   case Instruction::SRem:
 996   case Instruction::FRem:
 997   case Instruction::Shl:
 998   case Instruction::LShr:
 999   case Instruction::AShr:
1000   case Instruction::And:
1001   case Instruction::Or:
1002   case Instruction::Xor: {
1003     TargetTransformInfo::OperandValueKind Op1VK, Op2VK;
1004     TargetTransformInfo::OperandValueProperties Op1VP, Op2VP;
1005     Op1VK = getOperandInfo(I->getOperand(0), Op1VP);
1006     Op2VK = getOperandInfo(I->getOperand(1), Op2VP);
1007     SmallVector<const Value *, 2> Operands(I->operand_values());
1008     return getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, Op2VK,
1009                                   Op1VP, Op2VP, Operands);
1010   }
1011   case Instruction::Select: {
1012     const SelectInst *SI = cast<SelectInst>(I);
1013     Type *CondTy = SI->getCondition()->getType();
1014     return getCmpSelInstrCost(I->getOpcode(), I->getType(), CondTy, I);
1015   }
1016   case Instruction::ICmp:
1017   case Instruction::FCmp: {
1018     Type *ValTy = I->getOperand(0)->getType();
1019     return getCmpSelInstrCost(I->getOpcode(), ValTy, I->getType(), I);
1020   }
1021   case Instruction::Store: {
1022     const StoreInst *SI = cast<StoreInst>(I);
1023     Type *ValTy = SI->getValueOperand()->getType();
1024     return getMemoryOpCost(I->getOpcode(), ValTy,
1025                                 SI->getAlignment(),
1026                                 SI->getPointerAddressSpace(), I);
1027   }
1028   case Instruction::Load: {
1029     const LoadInst *LI = cast<LoadInst>(I);
1030     return getMemoryOpCost(I->getOpcode(), I->getType(),
1031                                 LI->getAlignment(),
1032                                 LI->getPointerAddressSpace(), I);
1033   }
1034   case Instruction::ZExt:
1035   case Instruction::SExt:
1036   case Instruction::FPToUI:
1037   case Instruction::FPToSI:
1038   case Instruction::FPExt:
1039   case Instruction::PtrToInt:
1040   case Instruction::IntToPtr:
1041   case Instruction::SIToFP:
1042   case Instruction::UIToFP:
1043   case Instruction::Trunc:
1044   case Instruction::FPTrunc:
1045   case Instruction::BitCast:
1046   case Instruction::AddrSpaceCast: {
1047     Type *SrcTy = I->getOperand(0)->getType();
1048     return getCastInstrCost(I->getOpcode(), I->getType(), SrcTy, I);
1049   }
1050   case Instruction::ExtractElement: {
1051     const ExtractElementInst * EEI = cast<ExtractElementInst>(I);
1052     ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1));
1053     unsigned Idx = -1;
1054     if (CI)
1055       Idx = CI->getZExtValue();
1056
1057     // Try to match a reduction sequence (series of shufflevector and vector
1058     // adds followed by a extractelement).
1059     unsigned ReduxOpCode;
1060     Type *ReduxType;
1061
1062     switch (matchVectorSplittingReduction(EEI, ReduxOpCode, ReduxType)) {
1063     case RK_Arithmetic:
1064       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1065                                              /*IsPairwiseForm=*/false);
1066     case RK_MinMax:
1067       return getMinMaxReductionCost(
1068           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1069           /*IsPairwiseForm=*/false, /*IsUnsigned=*/false);
1070     case RK_UnsignedMinMax:
1071       return getMinMaxReductionCost(
1072           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1073           /*IsPairwiseForm=*/false, /*IsUnsigned=*/true);
1074     case RK_None:
1075       break;
1076     }
1077
1078     switch (matchPairwiseReduction(EEI, ReduxOpCode, ReduxType)) {
1079     case RK_Arithmetic:
1080       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1081                                              /*IsPairwiseForm=*/true);
1082     case RK_MinMax:
1083       return getMinMaxReductionCost(
1084           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1085           /*IsPairwiseForm=*/true, /*IsUnsigned=*/false);
1086     case RK_UnsignedMinMax:
1087       return getMinMaxReductionCost(
1088           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1089           /*IsPairwiseForm=*/true, /*IsUnsigned=*/true);
1090     case RK_None:
1091       break;
1092     }
1093
1094     return getVectorInstrCost(I->getOpcode(),
1095                                    EEI->getOperand(0)->getType(), Idx);
1096   }
1097   case Instruction::InsertElement: {
1098     const InsertElementInst * IE = cast<InsertElementInst>(I);
1099     ConstantInt *CI = dyn_cast<ConstantInt>(IE->getOperand(2));
1100     unsigned Idx = -1;
1101     if (CI)
1102       Idx = CI->getZExtValue();
1103     return getVectorInstrCost(I->getOpcode(),
1104                                    IE->getType(), Idx);
1105   }
1106   case Instruction::ShuffleVector: {
1107     const ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I);
1108     // TODO: Identify and add costs for insert/extract subvector, etc.
1109     if (Shuffle->changesLength())
1110       return -1;
1111
1112     if (Shuffle->isIdentity())
1113       return 0;
1114
1115     Type *Ty = Shuffle->getType();
1116     if (Shuffle->isReverse())
1117       return TTIImpl->getShuffleCost(SK_Reverse, Ty, 0, nullptr);
1118
1119     if (Shuffle->isSelect())
1120       return TTIImpl->getShuffleCost(SK_Select, Ty, 0, nullptr);
1121
1122     if (Shuffle->isTranspose())
1123       return TTIImpl->getShuffleCost(SK_Transpose, Ty, 0, nullptr);
1124
1125     if (Shuffle->isZeroEltSplat())
1126       return TTIImpl->getShuffleCost(SK_Broadcast, Ty, 0, nullptr);
1127
1128     if (Shuffle->isSingleSource())
1129       return TTIImpl->getShuffleCost(SK_PermuteSingleSrc, Ty, 0, nullptr);
1130
1131     return TTIImpl->getShuffleCost(SK_PermuteTwoSrc, Ty, 0, nullptr);
1132   }
1133   case Instruction::Call:
1134     if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
1135       SmallVector<Value *, 4> Args(II->arg_operands());
1136
1137       FastMathFlags FMF;
1138       if (auto *FPMO = dyn_cast<FPMathOperator>(II))
1139         FMF = FPMO->getFastMathFlags();
1140
1141       return getIntrinsicInstrCost(II->getIntrinsicID(), II->getType(),
1142                                         Args, FMF);
1143     }
1144     return -1;
1145   default:
1146     // We don't have any information on this instruction.
1147     return -1;
1148   }
1149 }
1150
1151 TargetTransformInfo::Concept::~Concept() {}
1152
1153 TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1154
1155 TargetIRAnalysis::TargetIRAnalysis(
1156     std::function<Result(const Function &)> TTICallback)
1157     : TTICallback(std::move(TTICallback)) {}
1158
1159 TargetIRAnalysis::Result TargetIRAnalysis::run(const Function &F,
1160                                                FunctionAnalysisManager &) {
1161   return TTICallback(F);
1162 }
1163
1164 AnalysisKey TargetIRAnalysis::Key;
1165
1166 TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1167   return Result(F.getParent()->getDataLayout());
1168 }
1169
1170 // Register the basic pass.
1171 INITIALIZE_PASS(TargetTransformInfoWrapperPass, "tti",
1172                 "Target Transform Information", false, true)
1173 char TargetTransformInfoWrapperPass::ID = 0;
1174
1175 void TargetTransformInfoWrapperPass::anchor() {}
1176
1177 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass()
1178     : ImmutablePass(ID) {
1179   initializeTargetTransformInfoWrapperPassPass(
1180       *PassRegistry::getPassRegistry());
1181 }
1182
1183 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass(
1184     TargetIRAnalysis TIRA)
1185     : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1186   initializeTargetTransformInfoWrapperPassPass(
1187       *PassRegistry::getPassRegistry());
1188 }
1189
1190 TargetTransformInfo &TargetTransformInfoWrapperPass::getTTI(const Function &F) {
1191   FunctionAnalysisManager DummyFAM;
1192   TTI = TIRA.run(F, DummyFAM);
1193   return *TTI;
1194 }
1195
1196 ImmutablePass *
1197 llvm::createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA) {
1198   return new TargetTransformInfoWrapperPass(std::move(TIRA));
1199 }