1 //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements an allocation order for virtual registers.
12 // The preferred allocation order for a virtual register depends on allocation
13 // hints and target hooks. The AllocationOrder class encapsulates all of that.
15 //===----------------------------------------------------------------------===//
17 #include "AllocationOrder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/RegisterClassInfo.h"
21 #include "llvm/CodeGen/VirtRegMap.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/raw_ostream.h"
27 #define DEBUG_TYPE "regalloc"
29 // Compare VirtRegMap::getRegAllocPref().
30 AllocationOrder::AllocationOrder(unsigned VirtReg
,
31 const VirtRegMap
&VRM
,
32 const RegisterClassInfo
&RegClassInfo
,
33 const LiveRegMatrix
*Matrix
)
34 : Pos(0), HardHints(false) {
35 const MachineFunction
&MF
= VRM
.getMachineFunction();
36 const TargetRegisterInfo
*TRI
= &VRM
.getTargetRegInfo();
37 Order
= RegClassInfo
.getOrder(MF
.getRegInfo().getRegClass(VirtReg
));
38 if (TRI
->getRegAllocationHints(VirtReg
, Order
, Hints
, MF
, &VRM
, Matrix
))
45 for (unsigned I
= 0, E
= Hints
.size(); I
!= E
; ++I
)
46 dbgs() << ' ' << printReg(Hints
[I
], TRI
);
51 for (unsigned I
= 0, E
= Hints
.size(); I
!= E
; ++I
)
52 assert(is_contained(Order
, Hints
[I
]) &&
53 "Target hint is outside allocation order.");