lib/CodeGen/GlobalISel/IRTranslator.cpp

   1 //===- llvm/CodeGen/GlobalISel/IRTranslator.cpp - IRTranslator ---*- C++ -*-==//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 /// \file
  10 /// This file implements the IRTranslator class.
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
  14 #include "llvm/ADT/PostOrderIterator.h"
  15 #include "llvm/ADT/STLExtras.h"
  16 #include "llvm/ADT/ScopeExit.h"
  17 #include "llvm/ADT/SmallSet.h"
  18 #include "llvm/ADT/SmallVector.h"
  19 #include "llvm/Analysis/OptimizationRemarkEmitter.h"
  20 #include "llvm/CodeGen/Analysis.h"
  21 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
  22 #include "llvm/CodeGen/LowLevelType.h"
  23 #include "llvm/CodeGen/MachineBasicBlock.h"
  24 #include "llvm/CodeGen/MachineFrameInfo.h"
  25 #include "llvm/CodeGen/MachineFunction.h"
  26 #include "llvm/CodeGen/MachineInstrBuilder.h"
  27 #include "llvm/CodeGen/MachineMemOperand.h"
  28 #include "llvm/CodeGen/MachineOperand.h"
  29 #include "llvm/CodeGen/MachineRegisterInfo.h"
  30 #include "llvm/CodeGen/StackProtector.h"
  31 #include "llvm/CodeGen/TargetFrameLowering.h"
  32 #include "llvm/CodeGen/TargetLowering.h"
  33 #include "llvm/CodeGen/TargetPassConfig.h"
  34 #include "llvm/CodeGen/TargetRegisterInfo.h"
  35 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  36 #include "llvm/IR/BasicBlock.h"
  37 #include "llvm/IR/CFG.h"
  38 #include "llvm/IR/Constant.h"
  39 #include "llvm/IR/Constants.h"
  40 #include "llvm/IR/DataLayout.h"
  41 #include "llvm/IR/DebugInfo.h"
  42 #include "llvm/IR/DerivedTypes.h"
  43 #include "llvm/IR/Function.h"
  44 #include "llvm/IR/GetElementPtrTypeIterator.h"
  45 #include "llvm/IR/InlineAsm.h"
  46 #include "llvm/IR/InstrTypes.h"
  47 #include "llvm/IR/Instructions.h"
  48 #include "llvm/IR/IntrinsicInst.h"
  49 #include "llvm/IR/Intrinsics.h"
  50 #include "llvm/IR/LLVMContext.h"
  51 #include "llvm/IR/Metadata.h"
  52 #include "llvm/IR/Type.h"
  53 #include "llvm/IR/User.h"
  54 #include "llvm/IR/Value.h"
  55 #include "llvm/MC/MCContext.h"
  56 #include "llvm/Pass.h"
  57 #include "llvm/Support/Casting.h"
  58 #include "llvm/Support/CodeGen.h"
  59 #include "llvm/Support/Debug.h"
  60 #include "llvm/Support/ErrorHandling.h"
  61 #include "llvm/Support/LowLevelTypeImpl.h"
  62 #include "llvm/Support/MathExtras.h"
  63 #include "llvm/Support/raw_ostream.h"
  64 #include "llvm/Target/TargetIntrinsicInfo.h"
  65 #include "llvm/Target/TargetMachine.h"
  66 #include <algorithm>
  67 #include <cassert>
  68 #include <cstdint>
  69 #include <iterator>
  70 #include <string>
  71 #include <utility>
  72 #include <vector>
  73
  74 #define DEBUG_TYPE "irtranslator"
  75
  76 using namespace llvm;
  77
  78 char IRTranslator::ID = 0;
  79
  80 INITIALIZE_PASS_BEGIN(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
  81                 false, false)
  82 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
  83 INITIALIZE_PASS_END(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
  84                 false, false)
  85
  86 static void reportTranslationError(MachineFunction &MF,
  87                                    const TargetPassConfig &TPC,
  88                                    OptimizationRemarkEmitter &ORE,
  89                                    OptimizationRemarkMissed &R) {
  90   MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
  91
  92   // Print the function name explicitly if we don't have a debug location (which
  93   // makes the diagnostic less useful) or if we're going to emit a raw error.
  94   if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
  95     R << (" (in function: " + MF.getName() + ")").str();
  96
  97   if (TPC.isGlobalISelAbortEnabled())
  98     report_fatal_error(R.getMsg());
  99   else
 100     ORE.emit(R);
 101 }
 102
 103 IRTranslator::IRTranslator() : MachineFunctionPass(ID) {
 104   initializeIRTranslatorPass(*PassRegistry::getPassRegistry());
 105 }
 106
 107 void IRTranslator::getAnalysisUsage(AnalysisUsage &AU) const {
 108   AU.addRequired<StackProtector>();
 109   AU.addRequired<TargetPassConfig>();
 110   getSelectionDAGFallbackAnalysisUsage(AU);
 111   MachineFunctionPass::getAnalysisUsage(AU);
 112 }
 113
 114 static void computeValueLLTs(const DataLayout &DL, Type &Ty,
 115                              SmallVectorImpl<LLT> &ValueTys,
 116                              SmallVectorImpl<uint64_t> *Offsets = nullptr,
 117                              uint64_t StartingOffset = 0) {
 118   // Given a struct type, recursively traverse the elements.
 119   if (StructType *STy = dyn_cast<StructType>(&Ty)) {
 120     const StructLayout *SL = DL.getStructLayout(STy);
 121     for (unsigned I = 0, E = STy->getNumElements(); I != E; ++I)
 122       computeValueLLTs(DL, *STy->getElementType(I), ValueTys, Offsets,
 123                        StartingOffset + SL->getElementOffset(I));
 124     return;
 125   }
 126   // Given an array type, recursively traverse the elements.
 127   if (ArrayType *ATy = dyn_cast<ArrayType>(&Ty)) {
 128     Type *EltTy = ATy->getElementType();
 129     uint64_t EltSize = DL.getTypeAllocSize(EltTy);
 130     for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
 131       computeValueLLTs(DL, *EltTy, ValueTys, Offsets,
 132                        StartingOffset + i * EltSize);
 133     return;
 134   }
 135   // Interpret void as zero return values.
 136   if (Ty.isVoidTy())
 137     return;
 138   // Base case: we can get an LLT for this LLVM IR type.
 139   ValueTys.push_back(getLLTForType(Ty, DL));
 140   if (Offsets != nullptr)
 141     Offsets->push_back(StartingOffset * 8);
 142 }
 143
 144 IRTranslator::ValueToVRegInfo::VRegListT &
 145 IRTranslator::allocateVRegs(const Value &Val) {
 146   assert(!VMap.contains(Val) && "Value already allocated in VMap");
 147   auto *Regs = VMap.getVRegs(Val);
 148   auto *Offsets = VMap.getOffsets(Val);
 149   SmallVector<LLT, 4> SplitTys;
 150   computeValueLLTs(*DL, *Val.getType(), SplitTys,
 151                    Offsets->empty() ? Offsets : nullptr);
 152   for (unsigned i = 0; i < SplitTys.size(); ++i)
 153     Regs->push_back(0);
 154   return *Regs;
 155 }
 156
 157 ArrayRef<unsigned> IRTranslator::getOrCreateVRegs(const Value &Val) {
 158   auto VRegsIt = VMap.findVRegs(Val);
 159   if (VRegsIt != VMap.vregs_end())
 160     return *VRegsIt->second;
 161
 162   if (Val.getType()->isVoidTy())
 163     return *VMap.getVRegs(Val);
 164
 165   // Create entry for this type.
 166   auto *VRegs = VMap.getVRegs(Val);
 167   auto *Offsets = VMap.getOffsets(Val);
 168
 169   assert(Val.getType()->isSized() &&
 170          "Don't know how to create an empty vreg");
 171
 172   SmallVector<LLT, 4> SplitTys;
 173   computeValueLLTs(*DL, *Val.getType(), SplitTys,
 174                    Offsets->empty() ? Offsets : nullptr);
 175
 176   if (!isa<Constant>(Val)) {
 177     for (auto Ty : SplitTys)
 178       VRegs->push_back(MRI->createGenericVirtualRegister(Ty));
 179     return *VRegs;
 180   }
 181
 182   if (Val.getType()->isAggregateType()) {
 183     // UndefValue, ConstantAggregateZero
 184     auto &C = cast<Constant>(Val);
 185     unsigned Idx = 0;
 186     while (auto Elt = C.getAggregateElement(Idx++)) {
 187       auto EltRegs = getOrCreateVRegs(*Elt);
 188       std::copy(EltRegs.begin(), EltRegs.end(), std::back_inserter(*VRegs));
 189     }
 190   } else {
 191     assert(SplitTys.size() == 1 && "unexpectedly split LLT");
 192     VRegs->push_back(MRI->createGenericVirtualRegister(SplitTys[0]));
 193     bool Success = translate(cast<Constant>(Val), VRegs->front());
 194     if (!Success) {
 195       OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
 196                                  MF->getFunction().getSubprogram(),
 197                                  &MF->getFunction().getEntryBlock());
 198       R << "unable to translate constant: " << ore::NV("Type", Val.getType());
 199       reportTranslationError(*MF, *TPC, *ORE, R);
 200       return *VRegs;
 201     }
 202   }
 203
 204   return *VRegs;
 205 }
 206
 207 int IRTranslator::getOrCreateFrameIndex(const AllocaInst &AI) {
 208   if (FrameIndices.find(&AI) != FrameIndices.end())
 209     return FrameIndices[&AI];
 210
 211   unsigned ElementSize = DL->getTypeStoreSize(AI.getAllocatedType());
 212   unsigned Size =
 213       ElementSize * cast<ConstantInt>(AI.getArraySize())->getZExtValue();
 214
 215   // Always allocate at least one byte.
 216   Size = std::max(Size, 1u);
 217
 218   unsigned Alignment = AI.getAlignment();
 219   if (!Alignment)
 220     Alignment = DL->getABITypeAlignment(AI.getAllocatedType());
 221
 222   int &FI = FrameIndices[&AI];
 223   FI = MF->getFrameInfo().CreateStackObject(Size, Alignment, false, &AI);
 224   return FI;
 225 }
 226
 227 unsigned IRTranslator::getMemOpAlignment(const Instruction &I) {
 228   unsigned Alignment = 0;
 229   Type *ValTy = nullptr;
 230   if (const StoreInst *SI = dyn_cast<StoreInst>(&I)) {
 231     Alignment = SI->getAlignment();
 232     ValTy = SI->getValueOperand()->getType();
 233   } else if (const LoadInst *LI = dyn_cast<LoadInst>(&I)) {
 234     Alignment = LI->getAlignment();
 235     ValTy = LI->getType();
 236   } else if (const AtomicCmpXchgInst *AI = dyn_cast<AtomicCmpXchgInst>(&I)) {
 237     // TODO(PR27168): This instruction has no alignment attribute, but unlike
 238     // the default alignment for load/store, the default here is to assume
 239     // it has NATURAL alignment, not DataLayout-specified alignment.
 240     const DataLayout &DL = AI->getModule()->getDataLayout();
 241     Alignment = DL.getTypeStoreSize(AI->getCompareOperand()->getType());
 242     ValTy = AI->getCompareOperand()->getType();
 243   } else if (const AtomicRMWInst *AI = dyn_cast<AtomicRMWInst>(&I)) {
 244     // TODO(PR27168): This instruction has no alignment attribute, but unlike
 245     // the default alignment for load/store, the default here is to assume
 246     // it has NATURAL alignment, not DataLayout-specified alignment.
 247     const DataLayout &DL = AI->getModule()->getDataLayout();
 248     Alignment = DL.getTypeStoreSize(AI->getValOperand()->getType());
 249     ValTy = AI->getType();
 250   } else {
 251     OptimizationRemarkMissed R("gisel-irtranslator", "", &I);
 252     R << "unable to translate memop: " << ore::NV("Opcode", &I);
 253     reportTranslationError(*MF, *TPC, *ORE, R);
 254     return 1;
 255   }
 256
 257   return Alignment ? Alignment : DL->getABITypeAlignment(ValTy);
 258 }
 259
 260 MachineBasicBlock &IRTranslator::getMBB(const BasicBlock &BB) {
 261   MachineBasicBlock *&MBB = BBToMBB[&BB];
 262   assert(MBB && "BasicBlock was not encountered before");
 263   return *MBB;
 264 }
 265
 266 void IRTranslator::addMachineCFGPred(CFGEdge Edge, MachineBasicBlock *NewPred) {
 267   assert(NewPred && "new predecessor must be a real MachineBasicBlock");
 268   MachinePreds[Edge].push_back(NewPred);
 269 }
 270
 271 bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U,
 272                                      MachineIRBuilder &MIRBuilder) {
 273   // FIXME: handle signed/unsigned wrapping flags.
 274
 275   // Get or create a virtual register for each value.
 276   // Unless the value is a Constant => loadimm cst?
 277   // or inline constant each time?
 278   // Creation of a virtual register needs to have a size.
 279   unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
 280   unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
 281   unsigned Res = getOrCreateVReg(U);
 282   auto FBinOp = MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op0).addUse(Op1);
 283   if (isa<Instruction>(U)) {
 284     MachineInstr *FBinOpMI = FBinOp.getInstr();
 285     const Instruction &I = cast<Instruction>(U);
 286     FBinOpMI->copyIRFlags(I);
 287   }
 288   return true;
 289 }
 290
 291 bool IRTranslator::translateFSub(const User &U, MachineIRBuilder &MIRBuilder) {
 292   // -0.0 - X --> G_FNEG
 293   if (isa<Constant>(U.getOperand(0)) &&
 294       U.getOperand(0) == ConstantFP::getZeroValueForNegation(U.getType())) {
 295     MIRBuilder.buildInstr(TargetOpcode::G_FNEG)
 296         .addDef(getOrCreateVReg(U))
 297         .addUse(getOrCreateVReg(*U.getOperand(1)));
 298     return true;
 299   }
 300   return translateBinaryOp(TargetOpcode::G_FSUB, U, MIRBuilder);
 301 }
 302
 303 bool IRTranslator::translateCompare(const User &U,
 304                                     MachineIRBuilder &MIRBuilder) {
 305   const CmpInst *CI = dyn_cast<CmpInst>(&U);
 306   unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
 307   unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
 308   unsigned Res = getOrCreateVReg(U);
 309   CmpInst::Predicate Pred =
 310       CI ? CI->getPredicate() : static_cast<CmpInst::Predicate>(
 311                                     cast<ConstantExpr>(U).getPredicate());
 312   if (CmpInst::isIntPredicate(Pred))
 313     MIRBuilder.buildICmp(Pred, Res, Op0, Op1);
 314   else if (Pred == CmpInst::FCMP_FALSE)
 315     MIRBuilder.buildCopy(
 316         Res, getOrCreateVReg(*Constant::getNullValue(CI->getType())));
 317   else if (Pred == CmpInst::FCMP_TRUE)
 318     MIRBuilder.buildCopy(
 319         Res, getOrCreateVReg(*Constant::getAllOnesValue(CI->getType())));
 320   else
 321     MIRBuilder.buildFCmp(Pred, Res, Op0, Op1);
 322
 323   return true;
 324 }
 325
 326 bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
 327   const ReturnInst &RI = cast<ReturnInst>(U);
 328   const Value *Ret = RI.getReturnValue();
 329   if (Ret && DL->getTypeStoreSize(Ret->getType()) == 0)
 330     Ret = nullptr;
 331
 332   ArrayRef<unsigned> VRegs;
 333   if (Ret)
 334     VRegs = getOrCreateVRegs(*Ret);
 335
 336   // The target may mess up with the insertion point, but
 337   // this is not important as a return is the last instruction
 338   // of the block anyway.
 339
 340   return CLI->lowerReturn(MIRBuilder, Ret, VRegs);
 341 }
 342
 343 bool IRTranslator::translateBr(const User &U, MachineIRBuilder &MIRBuilder) {
 344   const BranchInst &BrInst = cast<BranchInst>(U);
 345   unsigned Succ = 0;
 346   if (!BrInst.isUnconditional()) {
 347     // We want a G_BRCOND to the true BB followed by an unconditional branch.
 348     unsigned Tst = getOrCreateVReg(*BrInst.getCondition());
 349     const BasicBlock &TrueTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ++));
 350     MachineBasicBlock &TrueBB = getMBB(TrueTgt);
 351     MIRBuilder.buildBrCond(Tst, TrueBB);
 352   }
 353
 354   const BasicBlock &BrTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ));
 355   MachineBasicBlock &TgtBB = getMBB(BrTgt);
 356   MachineBasicBlock &CurBB = MIRBuilder.getMBB();
 357
 358   // If the unconditional target is the layout successor, fallthrough.
 359   if (!CurBB.isLayoutSuccessor(&TgtBB))
 360     MIRBuilder.buildBr(TgtBB);
 361
 362   // Link successors.
 363   for (const BasicBlock *Succ : successors(&BrInst))
 364     CurBB.addSuccessor(&getMBB(*Succ));
 365   return true;
 366 }
 367
 368 bool IRTranslator::translateSwitch(const User &U,
 369                                    MachineIRBuilder &MIRBuilder) {
 370   // For now, just translate as a chain of conditional branches.
 371   // FIXME: could we share most of the logic/code in
 372   // SelectionDAGBuilder::visitSwitch between SelectionDAG and GlobalISel?
 373   // At first sight, it seems most of the logic in there is independent of
 374   // SelectionDAG-specifics and a lot of work went in to optimize switch
 375   // lowering in there.
 376
 377   const SwitchInst &SwInst = cast<SwitchInst>(U);
 378   const unsigned SwCondValue = getOrCreateVReg(*SwInst.getCondition());
 379   const BasicBlock *OrigBB = SwInst.getParent();
 380
 381   LLT LLTi1 = getLLTForType(*Type::getInt1Ty(U.getContext()), *DL);
 382   for (auto &CaseIt : SwInst.cases()) {
 383     const unsigned CaseValueReg = getOrCreateVReg(*CaseIt.getCaseValue());
 384     const unsigned Tst = MRI->createGenericVirtualRegister(LLTi1);
 385     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, Tst, CaseValueReg, SwCondValue);
 386     MachineBasicBlock &CurMBB = MIRBuilder.getMBB();
 387     const BasicBlock *TrueBB = CaseIt.getCaseSuccessor();
 388     MachineBasicBlock &TrueMBB = getMBB(*TrueBB);
 389
 390     MIRBuilder.buildBrCond(Tst, TrueMBB);
 391     CurMBB.addSuccessor(&TrueMBB);
 392     addMachineCFGPred({OrigBB, TrueBB}, &CurMBB);
 393
 394     MachineBasicBlock *FalseMBB =
 395         MF->CreateMachineBasicBlock(SwInst.getParent());
 396     // Insert the comparison blocks one after the other.
 397     MF->insert(std::next(CurMBB.getIterator()), FalseMBB);
 398     MIRBuilder.buildBr(*FalseMBB);
 399     CurMBB.addSuccessor(FalseMBB);
 400
 401     MIRBuilder.setMBB(*FalseMBB);
 402   }
 403   // handle default case
 404   const BasicBlock *DefaultBB = SwInst.getDefaultDest();
 405   MachineBasicBlock &DefaultMBB = getMBB(*DefaultBB);
 406   MIRBuilder.buildBr(DefaultMBB);
 407   MachineBasicBlock &CurMBB = MIRBuilder.getMBB();
 408   CurMBB.addSuccessor(&DefaultMBB);
 409   addMachineCFGPred({OrigBB, DefaultBB}, &CurMBB);
 410
 411   return true;
 412 }
 413
 414 bool IRTranslator::translateIndirectBr(const User &U,
 415                                        MachineIRBuilder &MIRBuilder) {
 416   const IndirectBrInst &BrInst = cast<IndirectBrInst>(U);
 417
 418   const unsigned Tgt = getOrCreateVReg(*BrInst.getAddress());
 419   MIRBuilder.buildBrIndirect(Tgt);
 420
 421   // Link successors.
 422   MachineBasicBlock &CurBB = MIRBuilder.getMBB();
 423   for (const BasicBlock *Succ : successors(&BrInst))
 424     CurBB.addSuccessor(&getMBB(*Succ));
 425
 426   return true;
 427 }
 428
 429 bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
 430   const LoadInst &LI = cast<LoadInst>(U);
 431
 432   auto Flags = LI.isVolatile() ? MachineMemOperand::MOVolatile
 433                                : MachineMemOperand::MONone;
 434   Flags |= MachineMemOperand::MOLoad;
 435
 436   if (DL->getTypeStoreSize(LI.getType()) == 0)
 437     return true;
 438
 439   ArrayRef<unsigned> Regs = getOrCreateVRegs(LI);
 440   ArrayRef<uint64_t> Offsets = *VMap.getOffsets(LI);
 441   unsigned Base = getOrCreateVReg(*LI.getPointerOperand());
 442
 443   for (unsigned i = 0; i < Regs.size(); ++i) {
 444     unsigned Addr = 0;
 445     MIRBuilder.materializeGEP(Addr, Base, LLT::scalar(64), Offsets[i] / 8);
 446
 447     MachinePointerInfo Ptr(LI.getPointerOperand(), Offsets[i] / 8);
 448     unsigned BaseAlign = getMemOpAlignment(LI);
 449     auto MMO = MF->getMachineMemOperand(
 450         Ptr, Flags, (MRI->getType(Regs[i]).getSizeInBits() + 7) / 8,
 451         MinAlign(BaseAlign, Offsets[i] / 8), AAMDNodes(), nullptr,
 452         LI.getSyncScopeID(), LI.getOrdering());
 453     MIRBuilder.buildLoad(Regs[i], Addr, *MMO);
 454   }
 455
 456   return true;
 457 }
 458
 459 bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
 460   const StoreInst &SI = cast<StoreInst>(U);
 461   auto Flags = SI.isVolatile() ? MachineMemOperand::MOVolatile
 462                                : MachineMemOperand::MONone;
 463   Flags |= MachineMemOperand::MOStore;
 464
 465   if (DL->getTypeStoreSize(SI.getValueOperand()->getType()) == 0)
 466     return true;
 467
 468   ArrayRef<unsigned> Vals = getOrCreateVRegs(*SI.getValueOperand());
 469   ArrayRef<uint64_t> Offsets = *VMap.getOffsets(*SI.getValueOperand());
 470   unsigned Base = getOrCreateVReg(*SI.getPointerOperand());
 471
 472   for (unsigned i = 0; i < Vals.size(); ++i) {
 473     unsigned Addr = 0;
 474     MIRBuilder.materializeGEP(Addr, Base, LLT::scalar(64), Offsets[i] / 8);
 475
 476     MachinePointerInfo Ptr(SI.getPointerOperand(), Offsets[i] / 8);
 477     unsigned BaseAlign = getMemOpAlignment(SI);
 478     auto MMO = MF->getMachineMemOperand(
 479         Ptr, Flags, (MRI->getType(Vals[i]).getSizeInBits() + 7) / 8,
 480         MinAlign(BaseAlign, Offsets[i] / 8), AAMDNodes(), nullptr,
 481         SI.getSyncScopeID(), SI.getOrdering());
 482     MIRBuilder.buildStore(Vals[i], Addr, *MMO);
 483   }
 484   return true;
 485 }
 486
 487 static uint64_t getOffsetFromIndices(const User &U, const DataLayout &DL) {
 488   const Value *Src = U.getOperand(0);
 489   Type *Int32Ty = Type::getInt32Ty(U.getContext());
 490
 491   // getIndexedOffsetInType is designed for GEPs, so the first index is the
 492   // usual array element rather than looking into the actual aggregate.
 493   SmallVector<Value *, 1> Indices;
 494   Indices.push_back(ConstantInt::get(Int32Ty, 0));
 495
 496   if (const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(&U)) {
 497     for (auto Idx : EVI->indices())
 498       Indices.push_back(ConstantInt::get(Int32Ty, Idx));
 499   } else if (const InsertValueInst *IVI = dyn_cast<InsertValueInst>(&U)) {
 500     for (auto Idx : IVI->indices())
 501       Indices.push_back(ConstantInt::get(Int32Ty, Idx));
 502   } else {
 503     for (unsigned i = 1; i < U.getNumOperands(); ++i)
 504       Indices.push_back(U.getOperand(i));
 505   }
 506
 507   return 8 * static_cast<uint64_t>(
 508                  DL.getIndexedOffsetInType(Src->getType(), Indices));
 509 }
 510
 511 bool IRTranslator::translateExtractValue(const User &U,
 512                                          MachineIRBuilder &MIRBuilder) {
 513   const Value *Src = U.getOperand(0);
 514   uint64_t Offset = getOffsetFromIndices(U, *DL);
 515   ArrayRef<unsigned> SrcRegs = getOrCreateVRegs(*Src);
 516   ArrayRef<uint64_t> Offsets = *VMap.getOffsets(*Src);
 517   unsigned Idx = std::lower_bound(Offsets.begin(), Offsets.end(), Offset) -
 518                  Offsets.begin();
 519   auto &DstRegs = allocateVRegs(U);
 520
 521   for (unsigned i = 0; i < DstRegs.size(); ++i)
 522     DstRegs[i] = SrcRegs[Idx++];
 523
 524   return true;
 525 }
 526
 527 bool IRTranslator::translateInsertValue(const User &U,
 528                                         MachineIRBuilder &MIRBuilder) {
 529   const Value *Src = U.getOperand(0);
 530   uint64_t Offset = getOffsetFromIndices(U, *DL);
 531   auto &DstRegs = allocateVRegs(U);
 532   ArrayRef<uint64_t> DstOffsets = *VMap.getOffsets(U);
 533   ArrayRef<unsigned> SrcRegs = getOrCreateVRegs(*Src);
 534   ArrayRef<unsigned> InsertedRegs = getOrCreateVRegs(*U.getOperand(1));
 535   auto InsertedIt = InsertedRegs.begin();
 536
 537   for (unsigned i = 0; i < DstRegs.size(); ++i) {
 538     if (DstOffsets[i] >= Offset && InsertedIt != InsertedRegs.end())
 539       DstRegs[i] = *InsertedIt++;
 540     else
 541       DstRegs[i] = SrcRegs[i];
 542   }
 543
 544   return true;
 545 }
 546
 547 bool IRTranslator::translateSelect(const User &U,
 548                                    MachineIRBuilder &MIRBuilder) {
 549   unsigned Tst = getOrCreateVReg(*U.getOperand(0));
 550   ArrayRef<unsigned> ResRegs = getOrCreateVRegs(U);
 551   ArrayRef<unsigned> Op0Regs = getOrCreateVRegs(*U.getOperand(1));
 552   ArrayRef<unsigned> Op1Regs = getOrCreateVRegs(*U.getOperand(2));
 553
 554   for (unsigned i = 0; i < ResRegs.size(); ++i)
 555     MIRBuilder.buildSelect(ResRegs[i], Tst, Op0Regs[i], Op1Regs[i]);
 556
 557   return true;
 558 }
 559
 560 bool IRTranslator::translateBitCast(const User &U,
 561                                     MachineIRBuilder &MIRBuilder) {
 562   // If we're bitcasting to the source type, we can reuse the source vreg.
 563   if (getLLTForType(*U.getOperand(0)->getType(), *DL) ==
 564       getLLTForType(*U.getType(), *DL)) {
 565     unsigned SrcReg = getOrCreateVReg(*U.getOperand(0));
 566     auto &Regs = *VMap.getVRegs(U);
 567     // If we already assigned a vreg for this bitcast, we can't change that.
 568     // Emit a copy to satisfy the users we already emitted.
 569     if (!Regs.empty())
 570       MIRBuilder.buildCopy(Regs[0], SrcReg);
 571     else {
 572       Regs.push_back(SrcReg);
 573       VMap.getOffsets(U)->push_back(0);
 574     }
 575     return true;
 576   }
 577   return translateCast(TargetOpcode::G_BITCAST, U, MIRBuilder);
 578 }
 579
 580 bool IRTranslator::translateCast(unsigned Opcode, const User &U,
 581                                  MachineIRBuilder &MIRBuilder) {
 582   unsigned Op = getOrCreateVReg(*U.getOperand(0));
 583   unsigned Res = getOrCreateVReg(U);
 584   MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op);
 585   return true;
 586 }
 587
 588 bool IRTranslator::translateGetElementPtr(const User &U,
 589                                           MachineIRBuilder &MIRBuilder) {
 590   // FIXME: support vector GEPs.
 591   if (U.getType()->isVectorTy())
 592     return false;
 593
 594   Value &Op0 = *U.getOperand(0);
 595   unsigned BaseReg = getOrCreateVReg(Op0);
 596   Type *PtrIRTy = Op0.getType();
 597   LLT PtrTy = getLLTForType(*PtrIRTy, *DL);
 598   Type *OffsetIRTy = DL->getIntPtrType(PtrIRTy);
 599   LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
 600
 601   int64_t Offset = 0;
 602   for (gep_type_iterator GTI = gep_type_begin(&U), E = gep_type_end(&U);
 603        GTI != E; ++GTI) {
 604     const Value *Idx = GTI.getOperand();
 605     if (StructType *StTy = GTI.getStructTypeOrNull()) {
 606       unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
 607       Offset += DL->getStructLayout(StTy)->getElementOffset(Field);
 608       continue;
 609     } else {
 610       uint64_t ElementSize = DL->getTypeAllocSize(GTI.getIndexedType());
 611
 612       // If this is a scalar constant or a splat vector of constants,
 613       // handle it quickly.
 614       if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
 615         Offset += ElementSize * CI->getSExtValue();
 616         continue;
 617       }
 618
 619       if (Offset != 0) {
 620         unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
 621         unsigned OffsetReg =
 622             getOrCreateVReg(*ConstantInt::get(OffsetIRTy, Offset));
 623         MIRBuilder.buildGEP(NewBaseReg, BaseReg, OffsetReg);
 624
 625         BaseReg = NewBaseReg;
 626         Offset = 0;
 627       }
 628
 629       unsigned IdxReg = getOrCreateVReg(*Idx);
 630       if (MRI->getType(IdxReg) != OffsetTy) {
 631         unsigned NewIdxReg = MRI->createGenericVirtualRegister(OffsetTy);
 632         MIRBuilder.buildSExtOrTrunc(NewIdxReg, IdxReg);
 633         IdxReg = NewIdxReg;
 634       }
 635
 636       // N = N + Idx * ElementSize;
 637       // Avoid doing it for ElementSize of 1.
 638       unsigned GepOffsetReg;
 639       if (ElementSize != 1) {
 640         unsigned ElementSizeReg =
 641             getOrCreateVReg(*ConstantInt::get(OffsetIRTy, ElementSize));
 642
 643         GepOffsetReg = MRI->createGenericVirtualRegister(OffsetTy);
 644         MIRBuilder.buildMul(GepOffsetReg, ElementSizeReg, IdxReg);
 645       } else
 646         GepOffsetReg = IdxReg;
 647
 648       unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
 649       MIRBuilder.buildGEP(NewBaseReg, BaseReg, GepOffsetReg);
 650       BaseReg = NewBaseReg;
 651     }
 652   }
 653
 654   if (Offset != 0) {
 655     unsigned OffsetReg = getOrCreateVReg(*ConstantInt::get(OffsetIRTy, Offset));
 656     MIRBuilder.buildGEP(getOrCreateVReg(U), BaseReg, OffsetReg);
 657     return true;
 658   }
 659
 660   MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg);
 661   return true;
 662 }
 663
 664 bool IRTranslator::translateMemfunc(const CallInst &CI,
 665                                     MachineIRBuilder &MIRBuilder,
 666                                     unsigned ID) {
 667   LLT SizeTy = getLLTForType(*CI.getArgOperand(2)->getType(), *DL);
 668   Type *DstTy = CI.getArgOperand(0)->getType();
 669   if (cast<PointerType>(DstTy)->getAddressSpace() != 0 ||
 670       SizeTy.getSizeInBits() != DL->getPointerSizeInBits(0))
 671     return false;
 672
 673   SmallVector<CallLowering::ArgInfo, 8> Args;
 674   for (int i = 0; i < 3; ++i) {
 675     const auto &Arg = CI.getArgOperand(i);
 676     Args.emplace_back(getOrCreateVReg(*Arg), Arg->getType());
 677   }
 678
 679   const char *Callee;
 680   switch (ID) {
 681   case Intrinsic::memmove:
 682   case Intrinsic::memcpy: {
 683     Type *SrcTy = CI.getArgOperand(1)->getType();
 684     if(cast<PointerType>(SrcTy)->getAddressSpace() != 0)
 685       return false;
 686     Callee = ID == Intrinsic::memcpy ? "memcpy" : "memmove";
 687     break;
 688   }
 689   case Intrinsic::memset:
 690     Callee = "memset";
 691     break;
 692   default:
 693     return false;
 694   }
 695
 696   return CLI->lowerCall(MIRBuilder, CI.getCallingConv(),
 697                         MachineOperand::CreateES(Callee),
 698                         CallLowering::ArgInfo(0, CI.getType()), Args);
 699 }
 700
 701 void IRTranslator::getStackGuard(unsigned DstReg,
 702                                  MachineIRBuilder &MIRBuilder) {
 703   const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
 704   MRI->setRegClass(DstReg, TRI->getPointerRegClass(*MF));
 705   auto MIB = MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD);
 706   MIB.addDef(DstReg);
 707
 708   auto &TLI = *MF->getSubtarget().getTargetLowering();
 709   Value *Global = TLI.getSDagStackGuard(*MF->getFunction().getParent());
 710   if (!Global)
 711     return;
 712
 713   MachinePointerInfo MPInfo(Global);
 714   auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant |
 715                MachineMemOperand::MODereferenceable;
 716   MachineMemOperand *MemRef =
 717       MF->getMachineMemOperand(MPInfo, Flags, DL->getPointerSizeInBits() / 8,
 718                                DL->getPointerABIAlignment(0));
 719   MIB.setMemRefs({MemRef});
 720 }
 721
 722 bool IRTranslator::translateOverflowIntrinsic(const CallInst &CI, unsigned Op,
 723                                               MachineIRBuilder &MIRBuilder) {
 724   ArrayRef<unsigned> ResRegs = getOrCreateVRegs(CI);
 725   MIRBuilder.buildInstr(Op)
 726       .addDef(ResRegs[0])
 727       .addDef(ResRegs[1])
 728       .addUse(getOrCreateVReg(*CI.getOperand(0)))
 729       .addUse(getOrCreateVReg(*CI.getOperand(1)));
 730
 731   return true;
 732 }
 733
 734 bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
 735                                            MachineIRBuilder &MIRBuilder) {
 736   switch (ID) {
 737   default:
 738     break;
 739   case Intrinsic::lifetime_start:
 740   case Intrinsic::lifetime_end:
 741     // Stack coloring is not enabled in O0 (which we care about now) so we can
 742     // drop these. Make sure someone notices when we start compiling at higher
 743     // opts though.
 744     if (MF->getTarget().getOptLevel() != CodeGenOpt::None)
 745       return false;
 746     return true;
 747   case Intrinsic::dbg_declare: {
 748     const DbgDeclareInst &DI = cast<DbgDeclareInst>(CI);
 749     assert(DI.getVariable() && "Missing variable");
 750
 751     const Value *Address = DI.getAddress();
 752     if (!Address || isa<UndefValue>(Address)) {
 753       LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
 754       return true;
 755     }
 756
 757     assert(DI.getVariable()->isValidLocationForIntrinsic(
 758                MIRBuilder.getDebugLoc()) &&
 759            "Expected inlined-at fields to agree");
 760     auto AI = dyn_cast<AllocaInst>(Address);
 761     if (AI && AI->isStaticAlloca()) {
 762       // Static allocas are tracked at the MF level, no need for DBG_VALUE
 763       // instructions (in fact, they get ignored if they *do* exist).
 764       MF->setVariableDbgInfo(DI.getVariable(), DI.getExpression(),
 765                              getOrCreateFrameIndex(*AI), DI.getDebugLoc());
 766     } else {
 767       // A dbg.declare describes the address of a source variable, so lower it
 768       // into an indirect DBG_VALUE.
 769       MIRBuilder.buildIndirectDbgValue(getOrCreateVReg(*Address),
 770                                        DI.getVariable(), DI.getExpression());
 771     }
 772     return true;
 773   }
 774   case Intrinsic::dbg_label: {
 775     const DbgLabelInst &DI = cast<DbgLabelInst>(CI);
 776     assert(DI.getLabel() && "Missing label");
 777
 778     assert(DI.getLabel()->isValidLocationForIntrinsic(
 779                MIRBuilder.getDebugLoc()) &&
 780            "Expected inlined-at fields to agree");
 781
 782     MIRBuilder.buildDbgLabel(DI.getLabel());
 783     return true;
 784   }
 785   case Intrinsic::vaend:
 786     // No target I know of cares about va_end. Certainly no in-tree target
 787     // does. Simplest intrinsic ever!
 788     return true;
 789   case Intrinsic::vastart: {
 790     auto &TLI = *MF->getSubtarget().getTargetLowering();
 791     Value *Ptr = CI.getArgOperand(0);
 792     unsigned ListSize = TLI.getVaListSizeInBits(*DL) / 8;
 793
 794     MIRBuilder.buildInstr(TargetOpcode::G_VASTART)
 795         .addUse(getOrCreateVReg(*Ptr))
 796         .addMemOperand(MF->getMachineMemOperand(
 797             MachinePointerInfo(Ptr), MachineMemOperand::MOStore, ListSize, 0));
 798     return true;
 799   }
 800   case Intrinsic::dbg_value: {
 801     // This form of DBG_VALUE is target-independent.
 802     const DbgValueInst &DI = cast<DbgValueInst>(CI);
 803     const Value *V = DI.getValue();
 804     assert(DI.getVariable()->isValidLocationForIntrinsic(
 805                MIRBuilder.getDebugLoc()) &&
 806            "Expected inlined-at fields to agree");
 807     if (!V) {
 808       // Currently the optimizer can produce this; insert an undef to
 809       // help debugging.  Probably the optimizer should not do this.
 810       MIRBuilder.buildIndirectDbgValue(0, DI.getVariable(), DI.getExpression());
 811     } else if (const auto *CI = dyn_cast<Constant>(V)) {
 812       MIRBuilder.buildConstDbgValue(*CI, DI.getVariable(), DI.getExpression());
 813     } else {
 814       unsigned Reg = getOrCreateVReg(*V);
 815       // FIXME: This does not handle register-indirect values at offset 0. The
 816       // direct/indirect thing shouldn't really be handled by something as
 817       // implicit as reg+noreg vs reg+imm in the first palce, but it seems
 818       // pretty baked in right now.
 819       MIRBuilder.buildDirectDbgValue(Reg, DI.getVariable(), DI.getExpression());
 820     }
 821     return true;
 822   }
 823   case Intrinsic::uadd_with_overflow:
 824     return translateOverflowIntrinsic(CI, TargetOpcode::G_UADDO, MIRBuilder);
 825   case Intrinsic::sadd_with_overflow:
 826     return translateOverflowIntrinsic(CI, TargetOpcode::G_SADDO, MIRBuilder);
 827   case Intrinsic::usub_with_overflow:
 828     return translateOverflowIntrinsic(CI, TargetOpcode::G_USUBO, MIRBuilder);
 829   case Intrinsic::ssub_with_overflow:
 830     return translateOverflowIntrinsic(CI, TargetOpcode::G_SSUBO, MIRBuilder);
 831   case Intrinsic::umul_with_overflow:
 832     return translateOverflowIntrinsic(CI, TargetOpcode::G_UMULO, MIRBuilder);
 833   case Intrinsic::smul_with_overflow:
 834     return translateOverflowIntrinsic(CI, TargetOpcode::G_SMULO, MIRBuilder);
 835   case Intrinsic::pow:
 836     MIRBuilder.buildInstr(TargetOpcode::G_FPOW)
 837         .addDef(getOrCreateVReg(CI))
 838         .addUse(getOrCreateVReg(*CI.getArgOperand(0)))
 839         .addUse(getOrCreateVReg(*CI.getArgOperand(1)));
 840     return true;
 841   case Intrinsic::exp:
 842     MIRBuilder.buildInstr(TargetOpcode::G_FEXP)
 843         .addDef(getOrCreateVReg(CI))
 844         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
 845     return true;
 846   case Intrinsic::exp2:
 847     MIRBuilder.buildInstr(TargetOpcode::G_FEXP2)
 848         .addDef(getOrCreateVReg(CI))
 849         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
 850     return true;
 851   case Intrinsic::log:
 852     MIRBuilder.buildInstr(TargetOpcode::G_FLOG)
 853         .addDef(getOrCreateVReg(CI))
 854         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
 855     return true;
 856   case Intrinsic::log2:
 857     MIRBuilder.buildInstr(TargetOpcode::G_FLOG2)
 858         .addDef(getOrCreateVReg(CI))
 859         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
 860     return true;
 861   case Intrinsic::fabs:
 862     MIRBuilder.buildInstr(TargetOpcode::G_FABS)
 863         .addDef(getOrCreateVReg(CI))
 864         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
 865     return true;
 866   case Intrinsic::trunc:
 867     MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_TRUNC)
 868         .addDef(getOrCreateVReg(CI))
 869         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
 870     return true;
 871   case Intrinsic::round:
 872     MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_ROUND)
 873         .addDef(getOrCreateVReg(CI))
 874         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
 875     return true;
 876   case Intrinsic::fma:
 877     MIRBuilder.buildInstr(TargetOpcode::G_FMA)
 878         .addDef(getOrCreateVReg(CI))
 879         .addUse(getOrCreateVReg(*CI.getArgOperand(0)))
 880         .addUse(getOrCreateVReg(*CI.getArgOperand(1)))
 881         .addUse(getOrCreateVReg(*CI.getArgOperand(2)));
 882     return true;
 883   case Intrinsic::fmuladd: {
 884     const TargetMachine &TM = MF->getTarget();
 885     const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
 886     unsigned Dst = getOrCreateVReg(CI);
 887     unsigned Op0 = getOrCreateVReg(*CI.getArgOperand(0));
 888     unsigned Op1 = getOrCreateVReg(*CI.getArgOperand(1));
 889     unsigned Op2 = getOrCreateVReg(*CI.getArgOperand(2));
 890     if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
 891         TLI.isFMAFasterThanFMulAndFAdd(TLI.getValueType(*DL, CI.getType()))) {
 892       // TODO: Revisit this to see if we should move this part of the
 893       // lowering to the combiner.
 894       MIRBuilder.buildInstr(TargetOpcode::G_FMA, Dst, Op0, Op1, Op2);
 895     } else {
 896       LLT Ty = getLLTForType(*CI.getType(), *DL);
 897       auto FMul = MIRBuilder.buildInstr(TargetOpcode::G_FMUL, Ty, Op0, Op1);
 898       MIRBuilder.buildInstr(TargetOpcode::G_FADD, Dst, FMul, Op2);
 899     }
 900     return true;
 901   }
 902   case Intrinsic::memcpy:
 903   case Intrinsic::memmove:
 904   case Intrinsic::memset:
 905     return translateMemfunc(CI, MIRBuilder, ID);
 906   case Intrinsic::eh_typeid_for: {
 907     GlobalValue *GV = ExtractTypeInfo(CI.getArgOperand(0));
 908     unsigned Reg = getOrCreateVReg(CI);
 909     unsigned TypeID = MF->getTypeIDFor(GV);
 910     MIRBuilder.buildConstant(Reg, TypeID);
 911     return true;
 912   }
 913   case Intrinsic::objectsize: {
 914     // If we don't know by now, we're never going to know.
 915     const ConstantInt *Min = cast<ConstantInt>(CI.getArgOperand(1));
 916
 917     MIRBuilder.buildConstant(getOrCreateVReg(CI), Min->isZero() ? -1ULL : 0);
 918     return true;
 919   }
 920   case Intrinsic::stackguard:
 921     getStackGuard(getOrCreateVReg(CI), MIRBuilder);
 922     return true;
 923   case Intrinsic::stackprotector: {
 924     LLT PtrTy = getLLTForType(*CI.getArgOperand(0)->getType(), *DL);
 925     unsigned GuardVal = MRI->createGenericVirtualRegister(PtrTy);
 926     getStackGuard(GuardVal, MIRBuilder);
 927
 928     AllocaInst *Slot = cast<AllocaInst>(CI.getArgOperand(1));
 929     MIRBuilder.buildStore(
 930         GuardVal, getOrCreateVReg(*Slot),
 931         *MF->getMachineMemOperand(
 932             MachinePointerInfo::getFixedStack(*MF,
 933                                               getOrCreateFrameIndex(*Slot)),
 934             MachineMemOperand::MOStore | MachineMemOperand::MOVolatile,
 935             PtrTy.getSizeInBits() / 8, 8));
 936     return true;
 937   }
 938   case Intrinsic::cttz:
 939   case Intrinsic::ctlz: {
 940     ConstantInt *Cst = cast<ConstantInt>(CI.getArgOperand(1));
 941     bool isTrailing = ID == Intrinsic::cttz;
 942     unsigned Opcode = isTrailing
 943                           ? Cst->isZero() ? TargetOpcode::G_CTTZ
 944                                           : TargetOpcode::G_CTTZ_ZERO_UNDEF
 945                           : Cst->isZero() ? TargetOpcode::G_CTLZ
 946                                           : TargetOpcode::G_CTLZ_ZERO_UNDEF;
 947     MIRBuilder.buildInstr(Opcode)
 948         .addDef(getOrCreateVReg(CI))
 949         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
 950     return true;
 951   }
 952   case Intrinsic::ctpop: {
 953     MIRBuilder.buildInstr(TargetOpcode::G_CTPOP)
 954         .addDef(getOrCreateVReg(CI))
 955         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
 956     return true;
 957   }
 958   case Intrinsic::invariant_start: {
 959     LLT PtrTy = getLLTForType(*CI.getArgOperand(0)->getType(), *DL);
 960     unsigned Undef = MRI->createGenericVirtualRegister(PtrTy);
 961     MIRBuilder.buildUndef(Undef);
 962     return true;
 963   }
 964   case Intrinsic::invariant_end:
 965     return true;
 966   }
 967   return false;
 968 }
 969
 970 bool IRTranslator::translateInlineAsm(const CallInst &CI,
 971                                       MachineIRBuilder &MIRBuilder) {
 972   const InlineAsm &IA = cast<InlineAsm>(*CI.getCalledValue());
 973   if (!IA.getConstraintString().empty())
 974     return false;
 975
 976   unsigned ExtraInfo = 0;
 977   if (IA.hasSideEffects())
 978     ExtraInfo |= InlineAsm::Extra_HasSideEffects;
 979   if (IA.getDialect() == InlineAsm::AD_Intel)
 980     ExtraInfo |= InlineAsm::Extra_AsmDialect;
 981
 982   MIRBuilder.buildInstr(TargetOpcode::INLINEASM)
 983     .addExternalSymbol(IA.getAsmString().c_str())
 984     .addImm(ExtraInfo);
 985
 986   return true;
 987 }
 988
 989 unsigned IRTranslator::packRegs(const Value &V,
 990                                   MachineIRBuilder &MIRBuilder) {
 991   ArrayRef<unsigned> Regs = getOrCreateVRegs(V);
 992   ArrayRef<uint64_t> Offsets = *VMap.getOffsets(V);
 993   LLT BigTy = getLLTForType(*V.getType(), *DL);
 994
 995   if (Regs.size() == 1)
 996     return Regs[0];
 997
 998   unsigned Dst = MRI->createGenericVirtualRegister(BigTy);
 999   MIRBuilder.buildUndef(Dst);
1000   for (unsigned i = 0; i < Regs.size(); ++i) {
1001     unsigned NewDst = MRI->createGenericVirtualRegister(BigTy);
1002     MIRBuilder.buildInsert(NewDst, Dst, Regs[i], Offsets[i]);
1003     Dst = NewDst;
1004   }
1005   return Dst;
1006 }
1007
1008 void IRTranslator::unpackRegs(const Value &V, unsigned Src,
1009                                 MachineIRBuilder &MIRBuilder) {
1010   ArrayRef<unsigned> Regs = getOrCreateVRegs(V);
1011   ArrayRef<uint64_t> Offsets = *VMap.getOffsets(V);
1012
1013   for (unsigned i = 0; i < Regs.size(); ++i)
1014     MIRBuilder.buildExtract(Regs[i], Src, Offsets[i]);
1015 }
1016
1017 bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
1018   const CallInst &CI = cast<CallInst>(U);
1019   auto TII = MF->getTarget().getIntrinsicInfo();
1020   const Function *F = CI.getCalledFunction();
1021
1022   // FIXME: support Windows dllimport function calls.
1023   if (F && F->hasDLLImportStorageClass())
1024     return false;
1025
1026   if (CI.isInlineAsm())
1027     return translateInlineAsm(CI, MIRBuilder);
1028
1029   Intrinsic::ID ID = Intrinsic::not_intrinsic;
1030   if (F && F->isIntrinsic()) {
1031     ID = F->getIntrinsicID();
1032     if (TII && ID == Intrinsic::not_intrinsic)
1033       ID = static_cast<Intrinsic::ID>(TII->getIntrinsicID(F));
1034   }
1035
1036   bool IsSplitType = valueIsSplit(CI);
1037   if (!F || !F->isIntrinsic() || ID == Intrinsic::not_intrinsic) {
1038     unsigned Res = IsSplitType ? MRI->createGenericVirtualRegister(
1039                                      getLLTForType(*CI.getType(), *DL))
1040                                : getOrCreateVReg(CI);
1041
1042     SmallVector<unsigned, 8> Args;
1043     for (auto &Arg: CI.arg_operands())
1044       Args.push_back(packRegs(*Arg, MIRBuilder));
1045
1046     MF->getFrameInfo().setHasCalls(true);
1047     bool Success = CLI->lowerCall(MIRBuilder, &CI, Res, Args, [&]() {
1048       return getOrCreateVReg(*CI.getCalledValue());
1049     });
1050
1051     if (IsSplitType)
1052       unpackRegs(CI, Res, MIRBuilder);
1053     return Success;
1054   }
1055
1056   assert(ID != Intrinsic::not_intrinsic && "unknown intrinsic");
1057
1058   if (translateKnownIntrinsic(CI, ID, MIRBuilder))
1059     return true;
1060
1061   unsigned Res = 0;
1062   if (!CI.getType()->isVoidTy()) {
1063     if (IsSplitType)
1064       Res =
1065           MRI->createGenericVirtualRegister(getLLTForType(*CI.getType(), *DL));
1066     else
1067       Res = getOrCreateVReg(CI);
1068   }
1069   MachineInstrBuilder MIB =
1070       MIRBuilder.buildIntrinsic(ID, Res, !CI.doesNotAccessMemory());
1071
1072   for (auto &Arg : CI.arg_operands()) {
1073     // Some intrinsics take metadata parameters. Reject them.
1074     if (isa<MetadataAsValue>(Arg))
1075       return false;
1076     MIB.addUse(packRegs(*Arg, MIRBuilder));
1077   }
1078
1079   if (IsSplitType)
1080     unpackRegs(CI, Res, MIRBuilder);
1081
1082   // Add a MachineMemOperand if it is a target mem intrinsic.
1083   const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
1084   TargetLowering::IntrinsicInfo Info;
1085   // TODO: Add a GlobalISel version of getTgtMemIntrinsic.
1086   if (TLI.getTgtMemIntrinsic(Info, CI, *MF, ID)) {
1087     uint64_t Size = Info.memVT.getStoreSize();
1088     MIB.addMemOperand(MF->getMachineMemOperand(MachinePointerInfo(Info.ptrVal),
1089                                                Info.flags, Size, Info.align));
1090   }
1091
1092   return true;
1093 }
1094
1095 bool IRTranslator::translateInvoke(const User &U,
1096                                    MachineIRBuilder &MIRBuilder) {
1097   const InvokeInst &I = cast<InvokeInst>(U);
1098   MCContext &Context = MF->getContext();
1099
1100   const BasicBlock *ReturnBB = I.getSuccessor(0);
1101   const BasicBlock *EHPadBB = I.getSuccessor(1);
1102
1103   const Value *Callee = I.getCalledValue();
1104   const Function *Fn = dyn_cast<Function>(Callee);
1105   if (isa<InlineAsm>(Callee))
1106     return false;
1107
1108   // FIXME: support invoking patchpoint and statepoint intrinsics.
1109   if (Fn && Fn->isIntrinsic())
1110     return false;
1111
1112   // FIXME: support whatever these are.
1113   if (I.countOperandBundlesOfType(LLVMContext::OB_deopt))
1114     return false;
1115
1116   // FIXME: support Windows exception handling.
1117   if (!isa<LandingPadInst>(EHPadBB->front()))
1118     return false;
1119
1120   // Emit the actual call, bracketed by EH_LABELs so that the MF knows about
1121   // the region covered by the try.
1122   MCSymbol *BeginSymbol = Context.createTempSymbol();
1123   MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(BeginSymbol);
1124
1125   unsigned Res =
1126         MRI->createGenericVirtualRegister(getLLTForType(*I.getType(), *DL));
1127   SmallVector<unsigned, 8> Args;
1128   for (auto &Arg: I.arg_operands())
1129     Args.push_back(packRegs(*Arg, MIRBuilder));
1130
1131   if (!CLI->lowerCall(MIRBuilder, &I, Res, Args,
1132                       [&]() { return getOrCreateVReg(*I.getCalledValue()); }))
1133     return false;
1134
1135   unpackRegs(I, Res, MIRBuilder);
1136
1137   MCSymbol *EndSymbol = Context.createTempSymbol();
1138   MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(EndSymbol);
1139
1140   // FIXME: track probabilities.
1141   MachineBasicBlock &EHPadMBB = getMBB(*EHPadBB),
1142                     &ReturnMBB = getMBB(*ReturnBB);
1143   MF->addInvoke(&EHPadMBB, BeginSymbol, EndSymbol);
1144   MIRBuilder.getMBB().addSuccessor(&ReturnMBB);
1145   MIRBuilder.getMBB().addSuccessor(&EHPadMBB);
1146   MIRBuilder.buildBr(ReturnMBB);
1147
1148   return true;
1149 }
1150
1151 bool IRTranslator::translateLandingPad(const User &U,
1152                                        MachineIRBuilder &MIRBuilder) {
1153   const LandingPadInst &LP = cast<LandingPadInst>(U);
1154
1155   MachineBasicBlock &MBB = MIRBuilder.getMBB();
1156
1157   MBB.setIsEHPad();
1158
1159   // If there aren't registers to copy the values into (e.g., during SjLj
1160   // exceptions), then don't bother.
1161   auto &TLI = *MF->getSubtarget().getTargetLowering();
1162   const Constant *PersonalityFn = MF->getFunction().getPersonalityFn();
1163   if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
1164       TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
1165     return true;
1166
1167   // If landingpad's return type is token type, we don't create DAG nodes
1168   // for its exception pointer and selector value. The extraction of exception
1169   // pointer or selector value from token type landingpads is not currently
1170   // supported.
1171   if (LP.getType()->isTokenTy())
1172     return true;
1173
1174   // Add a label to mark the beginning of the landing pad.  Deletion of the
1175   // landing pad can thus be detected via the MachineModuleInfo.
1176   MIRBuilder.buildInstr(TargetOpcode::EH_LABEL)
1177     .addSym(MF->addLandingPad(&MBB));
1178
1179   LLT Ty = getLLTForType(*LP.getType(), *DL);
1180   unsigned Undef = MRI->createGenericVirtualRegister(Ty);
1181   MIRBuilder.buildUndef(Undef);
1182
1183   SmallVector<LLT, 2> Tys;
1184   for (Type *Ty : cast<StructType>(LP.getType())->elements())
1185     Tys.push_back(getLLTForType(*Ty, *DL));
1186   assert(Tys.size() == 2 && "Only two-valued landingpads are supported");
1187
1188   // Mark exception register as live in.
1189   unsigned ExceptionReg = TLI.getExceptionPointerRegister(PersonalityFn);
1190   if (!ExceptionReg)
1191     return false;
1192
1193   MBB.addLiveIn(ExceptionReg);
1194   ArrayRef<unsigned> ResRegs = getOrCreateVRegs(LP);
1195   MIRBuilder.buildCopy(ResRegs[0], ExceptionReg);
1196
1197   unsigned SelectorReg = TLI.getExceptionSelectorRegister(PersonalityFn);
1198   if (!SelectorReg)
1199     return false;
1200
1201   MBB.addLiveIn(SelectorReg);
1202   unsigned PtrVReg = MRI->createGenericVirtualRegister(Tys[0]);
1203   MIRBuilder.buildCopy(PtrVReg, SelectorReg);
1204   MIRBuilder.buildCast(ResRegs[1], PtrVReg);
1205
1206   return true;
1207 }
1208
1209 bool IRTranslator::translateAlloca(const User &U,
1210                                    MachineIRBuilder &MIRBuilder) {
1211   auto &AI = cast<AllocaInst>(U);
1212
1213   if (AI.isSwiftError())
1214     return false;
1215
1216   if (AI.isStaticAlloca()) {
1217     unsigned Res = getOrCreateVReg(AI);
1218     int FI = getOrCreateFrameIndex(AI);
1219     MIRBuilder.buildFrameIndex(Res, FI);
1220     return true;
1221   }
1222
1223   // FIXME: support stack probing for Windows.
1224   if (MF->getTarget().getTargetTriple().isOSWindows())
1225     return false;
1226
1227   // Now we're in the harder dynamic case.
1228   Type *Ty = AI.getAllocatedType();
1229   unsigned Align =
1230       std::max((unsigned)DL->getPrefTypeAlignment(Ty), AI.getAlignment());
1231
1232   unsigned NumElts = getOrCreateVReg(*AI.getArraySize());
1233
1234   Type *IntPtrIRTy = DL->getIntPtrType(AI.getType());
1235   LLT IntPtrTy = getLLTForType(*IntPtrIRTy, *DL);
1236   if (MRI->getType(NumElts) != IntPtrTy) {
1237     unsigned ExtElts = MRI->createGenericVirtualRegister(IntPtrTy);
1238     MIRBuilder.buildZExtOrTrunc(ExtElts, NumElts);
1239     NumElts = ExtElts;
1240   }
1241
1242   unsigned AllocSize = MRI->createGenericVirtualRegister(IntPtrTy);
1243   unsigned TySize =
1244       getOrCreateVReg(*ConstantInt::get(IntPtrIRTy, -DL->getTypeAllocSize(Ty)));
1245   MIRBuilder.buildMul(AllocSize, NumElts, TySize);
1246
1247   LLT PtrTy = getLLTForType(*AI.getType(), *DL);
1248   auto &TLI = *MF->getSubtarget().getTargetLowering();
1249   unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1250
1251   unsigned SPTmp = MRI->createGenericVirtualRegister(PtrTy);
1252   MIRBuilder.buildCopy(SPTmp, SPReg);
1253
1254   unsigned AllocTmp = MRI->createGenericVirtualRegister(PtrTy);
1255   MIRBuilder.buildGEP(AllocTmp, SPTmp, AllocSize);
1256
1257   // Handle alignment. We have to realign if the allocation granule was smaller
1258   // than stack alignment, or the specific alloca requires more than stack
1259   // alignment.
1260   unsigned StackAlign =
1261       MF->getSubtarget().getFrameLowering()->getStackAlignment();
1262   Align = std::max(Align, StackAlign);
1263   if (Align > StackAlign || DL->getTypeAllocSize(Ty) % StackAlign != 0) {
1264     // Round the size of the allocation up to the stack alignment size
1265     // by add SA-1 to the size. This doesn't overflow because we're computing
1266     // an address inside an alloca.
1267     unsigned AlignedAlloc = MRI->createGenericVirtualRegister(PtrTy);
1268     MIRBuilder.buildPtrMask(AlignedAlloc, AllocTmp, Log2_32(Align));
1269     AllocTmp = AlignedAlloc;
1270   }
1271
1272   MIRBuilder.buildCopy(SPReg, AllocTmp);
1273   MIRBuilder.buildCopy(getOrCreateVReg(AI), AllocTmp);
1274
1275   MF->getFrameInfo().CreateVariableSizedObject(Align ? Align : 1, &AI);
1276   assert(MF->getFrameInfo().hasVarSizedObjects());
1277   return true;
1278 }
1279
1280 bool IRTranslator::translateVAArg(const User &U, MachineIRBuilder &MIRBuilder) {
1281   // FIXME: We may need more info about the type. Because of how LLT works,
1282   // we're completely discarding the i64/double distinction here (amongst
1283   // others). Fortunately the ABIs I know of where that matters don't use va_arg
1284   // anyway but that's not guaranteed.
1285   MIRBuilder.buildInstr(TargetOpcode::G_VAARG)
1286     .addDef(getOrCreateVReg(U))
1287     .addUse(getOrCreateVReg(*U.getOperand(0)))
1288     .addImm(DL->getABITypeAlignment(U.getType()));
1289   return true;
1290 }
1291
1292 bool IRTranslator::translateInsertElement(const User &U,
1293                                           MachineIRBuilder &MIRBuilder) {
1294   // If it is a <1 x Ty> vector, use the scalar as it is
1295   // not a legal vector type in LLT.
1296   if (U.getType()->getVectorNumElements() == 1) {
1297     unsigned Elt = getOrCreateVReg(*U.getOperand(1));
1298     auto &Regs = *VMap.getVRegs(U);
1299     if (Regs.empty()) {
1300       Regs.push_back(Elt);
1301       VMap.getOffsets(U)->push_back(0);
1302     } else {
1303       MIRBuilder.buildCopy(Regs[0], Elt);
1304     }
1305     return true;
1306   }
1307
1308   unsigned Res = getOrCreateVReg(U);
1309   unsigned Val = getOrCreateVReg(*U.getOperand(0));
1310   unsigned Elt = getOrCreateVReg(*U.getOperand(1));
1311   unsigned Idx = getOrCreateVReg(*U.getOperand(2));
1312   MIRBuilder.buildInsertVectorElement(Res, Val, Elt, Idx);
1313   return true;
1314 }
1315
1316 bool IRTranslator::translateExtractElement(const User &U,
1317                                            MachineIRBuilder &MIRBuilder) {
1318   // If it is a <1 x Ty> vector, use the scalar as it is
1319   // not a legal vector type in LLT.
1320   if (U.getOperand(0)->getType()->getVectorNumElements() == 1) {
1321     unsigned Elt = getOrCreateVReg(*U.getOperand(0));
1322     auto &Regs = *VMap.getVRegs(U);
1323     if (Regs.empty()) {
1324       Regs.push_back(Elt);
1325       VMap.getOffsets(U)->push_back(0);
1326     } else {
1327       MIRBuilder.buildCopy(Regs[0], Elt);
1328     }
1329     return true;
1330   }
1331   unsigned Res = getOrCreateVReg(U);
1332   unsigned Val = getOrCreateVReg(*U.getOperand(0));
1333   unsigned Idx = getOrCreateVReg(*U.getOperand(1));
1334   MIRBuilder.buildExtractVectorElement(Res, Val, Idx);
1335   return true;
1336 }
1337
1338 bool IRTranslator::translateShuffleVector(const User &U,
1339                                           MachineIRBuilder &MIRBuilder) {
1340   MIRBuilder.buildInstr(TargetOpcode::G_SHUFFLE_VECTOR)
1341       .addDef(getOrCreateVReg(U))
1342       .addUse(getOrCreateVReg(*U.getOperand(0)))
1343       .addUse(getOrCreateVReg(*U.getOperand(1)))
1344       .addUse(getOrCreateVReg(*U.getOperand(2)));
1345   return true;
1346 }
1347
1348 bool IRTranslator::translatePHI(const User &U, MachineIRBuilder &MIRBuilder) {
1349   const PHINode &PI = cast<PHINode>(U);
1350
1351   SmallVector<MachineInstr *, 4> Insts;
1352   for (auto Reg : getOrCreateVRegs(PI)) {
1353     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI, Reg);
1354     Insts.push_back(MIB.getInstr());
1355   }
1356
1357   PendingPHIs.emplace_back(&PI, std::move(Insts));
1358   return true;
1359 }
1360
1361 bool IRTranslator::translateAtomicCmpXchg(const User &U,
1362                                           MachineIRBuilder &MIRBuilder) {
1363   const AtomicCmpXchgInst &I = cast<AtomicCmpXchgInst>(U);
1364
1365   if (I.isWeak())
1366     return false;
1367
1368   auto Flags = I.isVolatile() ? MachineMemOperand::MOVolatile
1369                               : MachineMemOperand::MONone;
1370   Flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
1371
1372   Type *ResType = I.getType();
1373   Type *ValType = ResType->Type::getStructElementType(0);
1374
1375   auto Res = getOrCreateVRegs(I);
1376   unsigned OldValRes = Res[0];
1377   unsigned SuccessRes = Res[1];
1378   unsigned Addr = getOrCreateVReg(*I.getPointerOperand());
1379   unsigned Cmp = getOrCreateVReg(*I.getCompareOperand());
1380   unsigned NewVal = getOrCreateVReg(*I.getNewValOperand());
1381
1382   MIRBuilder.buildAtomicCmpXchgWithSuccess(
1383       OldValRes, SuccessRes, Addr, Cmp, NewVal,
1384       *MF->getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
1385                                 Flags, DL->getTypeStoreSize(ValType),
1386                                 getMemOpAlignment(I), AAMDNodes(), nullptr,
1387                                 I.getSyncScopeID(), I.getSuccessOrdering(),
1388                                 I.getFailureOrdering()));
1389   return true;
1390 }
1391
1392 bool IRTranslator::translateAtomicRMW(const User &U,
1393                                       MachineIRBuilder &MIRBuilder) {
1394   const AtomicRMWInst &I = cast<AtomicRMWInst>(U);
1395
1396   auto Flags = I.isVolatile() ? MachineMemOperand::MOVolatile
1397                               : MachineMemOperand::MONone;
1398   Flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
1399
1400   Type *ResType = I.getType();
1401
1402   unsigned Res = getOrCreateVReg(I);
1403   unsigned Addr = getOrCreateVReg(*I.getPointerOperand());
1404   unsigned Val = getOrCreateVReg(*I.getValOperand());
1405
1406   unsigned Opcode = 0;
1407   switch (I.getOperation()) {
1408   default:
1409     llvm_unreachable("Unknown atomicrmw op");
1410     return false;
1411   case AtomicRMWInst::Xchg:
1412     Opcode = TargetOpcode::G_ATOMICRMW_XCHG;
1413     break;
1414   case AtomicRMWInst::Add:
1415     Opcode = TargetOpcode::G_ATOMICRMW_ADD;
1416     break;
1417   case AtomicRMWInst::Sub:
1418     Opcode = TargetOpcode::G_ATOMICRMW_SUB;
1419     break;
1420   case AtomicRMWInst::And:
1421     Opcode = TargetOpcode::G_ATOMICRMW_AND;
1422     break;
1423   case AtomicRMWInst::Nand:
1424     Opcode = TargetOpcode::G_ATOMICRMW_NAND;
1425     break;
1426   case AtomicRMWInst::Or:
1427     Opcode = TargetOpcode::G_ATOMICRMW_OR;
1428     break;
1429   case AtomicRMWInst::Xor:
1430     Opcode = TargetOpcode::G_ATOMICRMW_XOR;
1431     break;
1432   case AtomicRMWInst::Max:
1433     Opcode = TargetOpcode::G_ATOMICRMW_MAX;
1434     break;
1435   case AtomicRMWInst::Min:
1436     Opcode = TargetOpcode::G_ATOMICRMW_MIN;
1437     break;
1438   case AtomicRMWInst::UMax:
1439     Opcode = TargetOpcode::G_ATOMICRMW_UMAX;
1440     break;
1441   case AtomicRMWInst::UMin:
1442     Opcode = TargetOpcode::G_ATOMICRMW_UMIN;
1443     break;
1444   }
1445
1446   MIRBuilder.buildAtomicRMW(
1447       Opcode, Res, Addr, Val,
1448       *MF->getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
1449                                 Flags, DL->getTypeStoreSize(ResType),
1450                                 getMemOpAlignment(I), AAMDNodes(), nullptr,
1451                                 I.getSyncScopeID(), I.getOrdering()));
1452   return true;
1453 }
1454
1455 void IRTranslator::finishPendingPhis() {
1456   for (auto &Phi : PendingPHIs) {
1457     const PHINode *PI = Phi.first;
1458     ArrayRef<MachineInstr *> ComponentPHIs = Phi.second;
1459
1460     // All MachineBasicBlocks exist, add them to the PHI. We assume IRTranslator
1461     // won't create extra control flow here, otherwise we need to find the
1462     // dominating predecessor here (or perhaps force the weirder IRTranslators
1463     // to provide a simple boundary).
1464     SmallSet<const BasicBlock *, 4> HandledPreds;
1465
1466     for (unsigned i = 0; i < PI->getNumIncomingValues(); ++i) {
1467       auto IRPred = PI->getIncomingBlock(i);
1468       if (HandledPreds.count(IRPred))
1469         continue;
1470
1471       HandledPreds.insert(IRPred);
1472       ArrayRef<unsigned> ValRegs = getOrCreateVRegs(*PI->getIncomingValue(i));
1473       for (auto Pred : getMachinePredBBs({IRPred, PI->getParent()})) {
1474         assert(Pred->isSuccessor(ComponentPHIs[0]->getParent()) &&
1475                "incorrect CFG at MachineBasicBlock level");
1476         for (unsigned j = 0; j < ValRegs.size(); ++j) {
1477           MachineInstrBuilder MIB(*MF, ComponentPHIs[j]);
1478           MIB.addUse(ValRegs[j]);
1479           MIB.addMBB(Pred);
1480         }
1481       }
1482     }
1483   }
1484 }
1485
1486 bool IRTranslator::valueIsSplit(const Value &V,
1487                                 SmallVectorImpl<uint64_t> *Offsets) {
1488   SmallVector<LLT, 4> SplitTys;
1489   if (Offsets && !Offsets->empty())
1490     Offsets->clear();
1491   computeValueLLTs(*DL, *V.getType(), SplitTys, Offsets);
1492   return SplitTys.size() > 1;
1493 }
1494
1495 bool IRTranslator::translate(const Instruction &Inst) {
1496   CurBuilder.setDebugLoc(Inst.getDebugLoc());
1497   switch(Inst.getOpcode()) {
1498 #define HANDLE_INST(NUM, OPCODE, CLASS) \
1499     case Instruction::OPCODE: return translate##OPCODE(Inst, CurBuilder);
1500 #include "llvm/IR/Instruction.def"
1501   default:
1502     return false;
1503   }
1504 }
1505
1506 bool IRTranslator::translate(const Constant &C, unsigned Reg) {
1507   if (auto CI = dyn_cast<ConstantInt>(&C))
1508     EntryBuilder.buildConstant(Reg, *CI);
1509   else if (auto CF = dyn_cast<ConstantFP>(&C))
1510     EntryBuilder.buildFConstant(Reg, *CF);
1511   else if (isa<UndefValue>(C))
1512     EntryBuilder.buildUndef(Reg);
1513   else if (isa<ConstantPointerNull>(C)) {
1514     // As we are trying to build a constant val of 0 into a pointer,
1515     // insert a cast to make them correct with respect to types.
1516     unsigned NullSize = DL->getTypeSizeInBits(C.getType());
1517     auto *ZeroTy = Type::getIntNTy(C.getContext(), NullSize);
1518     auto *ZeroVal = ConstantInt::get(ZeroTy, 0);
1519     unsigned ZeroReg = getOrCreateVReg(*ZeroVal);
1520     EntryBuilder.buildCast(Reg, ZeroReg);
1521   } else if (auto GV = dyn_cast<GlobalValue>(&C))
1522     EntryBuilder.buildGlobalValue(Reg, GV);
1523   else if (auto CAZ = dyn_cast<ConstantAggregateZero>(&C)) {
1524     if (!CAZ->getType()->isVectorTy())
1525       return false;
1526     // Return the scalar if it is a <1 x Ty> vector.
1527     if (CAZ->getNumElements() == 1)
1528       return translate(*CAZ->getElementValue(0u), Reg);
1529     std::vector<unsigned> Ops;
1530     for (unsigned i = 0; i < CAZ->getNumElements(); ++i) {
1531       Constant &Elt = *CAZ->getElementValue(i);
1532       Ops.push_back(getOrCreateVReg(Elt));
1533     }
1534     EntryBuilder.buildMerge(Reg, Ops);
1535   } else if (auto CV = dyn_cast<ConstantDataVector>(&C)) {
1536     // Return the scalar if it is a <1 x Ty> vector.
1537     if (CV->getNumElements() == 1)
1538       return translate(*CV->getElementAsConstant(0), Reg);
1539     std::vector<unsigned> Ops;
1540     for (unsigned i = 0; i < CV->getNumElements(); ++i) {
1541       Constant &Elt = *CV->getElementAsConstant(i);
1542       Ops.push_back(getOrCreateVReg(Elt));
1543     }
1544     EntryBuilder.buildMerge(Reg, Ops);
1545   } else if (auto CE = dyn_cast<ConstantExpr>(&C)) {
1546     switch(CE->getOpcode()) {
1547 #define HANDLE_INST(NUM, OPCODE, CLASS)                         \
1548       case Instruction::OPCODE: return translate##OPCODE(*CE, EntryBuilder);
1549 #include "llvm/IR/Instruction.def"
1550     default:
1551       return false;
1552     }
1553   } else if (auto CV = dyn_cast<ConstantVector>(&C)) {
1554     if (CV->getNumOperands() == 1)
1555       return translate(*CV->getOperand(0), Reg);
1556     SmallVector<unsigned, 4> Ops;
1557     for (unsigned i = 0; i < CV->getNumOperands(); ++i) {
1558       Ops.push_back(getOrCreateVReg(*CV->getOperand(i)));
1559     }
1560     EntryBuilder.buildMerge(Reg, Ops);
1561   } else if (auto *BA = dyn_cast<BlockAddress>(&C)) {
1562     EntryBuilder.buildBlockAddress(Reg, BA);
1563   } else
1564     return false;
1565
1566   return true;
1567 }
1568
1569 void IRTranslator::finalizeFunction() {
1570   // Release the memory used by the different maps we
1571   // needed during the translation.
1572   PendingPHIs.clear();
1573   VMap.reset();
1574   FrameIndices.clear();
1575   MachinePreds.clear();
1576   // MachineIRBuilder::DebugLoc can outlive the DILocation it holds. Clear it
1577   // to avoid accessing free’d memory (in runOnMachineFunction) and to avoid
1578   // destroying it twice (in ~IRTranslator() and ~LLVMContext())
1579   EntryBuilder = MachineIRBuilder();
1580   CurBuilder = MachineIRBuilder();
1581 }
1582
1583 bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
1584   MF = &CurMF;
1585   const Function &F = MF->getFunction();
1586   if (F.empty())
1587     return false;
1588   CLI = MF->getSubtarget().getCallLowering();
1589   CurBuilder.setMF(*MF);
1590   EntryBuilder.setMF(*MF);
1591   MRI = &MF->getRegInfo();
1592   DL = &F.getParent()->getDataLayout();
1593   TPC = &getAnalysis<TargetPassConfig>();
1594   ORE = llvm::make_unique<OptimizationRemarkEmitter>(&F);
1595
1596   assert(PendingPHIs.empty() && "stale PHIs");
1597
1598   if (!DL->isLittleEndian()) {
1599     // Currently we don't properly handle big endian code.
1600     OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
1601                                F.getSubprogram(), &F.getEntryBlock());
1602     R << "unable to translate in big endian mode";
1603     reportTranslationError(*MF, *TPC, *ORE, R);
1604   }
1605
1606   // Release the per-function state when we return, whether we succeeded or not.
1607   auto FinalizeOnReturn = make_scope_exit([this]() { finalizeFunction(); });
1608
1609   // Setup a separate basic-block for the arguments and constants
1610   MachineBasicBlock *EntryBB = MF->CreateMachineBasicBlock();
1611   MF->push_back(EntryBB);
1612   EntryBuilder.setMBB(*EntryBB);
1613
1614   // Create all blocks, in IR order, to preserve the layout.
1615   for (const BasicBlock &BB: F) {
1616     auto *&MBB = BBToMBB[&BB];
1617
1618     MBB = MF->CreateMachineBasicBlock(&BB);
1619     MF->push_back(MBB);
1620
1621     if (BB.hasAddressTaken())
1622       MBB->setHasAddressTaken();
1623   }
1624
1625   // Make our arguments/constants entry block fallthrough to the IR entry block.
1626   EntryBB->addSuccessor(&getMBB(F.front()));
1627
1628   // Lower the actual args into this basic block.
1629   SmallVector<unsigned, 8> VRegArgs;
1630   for (const Argument &Arg: F.args()) {
1631     if (DL->getTypeStoreSize(Arg.getType()) == 0)
1632       continue; // Don't handle zero sized types.
1633     VRegArgs.push_back(
1634         MRI->createGenericVirtualRegister(getLLTForType(*Arg.getType(), *DL)));
1635   }
1636
1637   // We don't currently support translating swifterror or swiftself functions.
1638   for (auto &Arg : F.args()) {
1639     if (Arg.hasSwiftErrorAttr() || Arg.hasSwiftSelfAttr()) {
1640       OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
1641                                  F.getSubprogram(), &F.getEntryBlock());
1642       R << "unable to lower arguments due to swifterror/swiftself: "
1643         << ore::NV("Prototype", F.getType());
1644       reportTranslationError(*MF, *TPC, *ORE, R);
1645       return false;
1646     }
1647   }
1648
1649   if (!CLI->lowerFormalArguments(EntryBuilder, F, VRegArgs)) {
1650     OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
1651                                F.getSubprogram(), &F.getEntryBlock());
1652     R << "unable to lower arguments: " << ore::NV("Prototype", F.getType());
1653     reportTranslationError(*MF, *TPC, *ORE, R);
1654     return false;
1655   }
1656
1657   auto ArgIt = F.arg_begin();
1658   for (auto &VArg : VRegArgs) {
1659     // If the argument is an unsplit scalar then don't use unpackRegs to avoid
1660     // creating redundant copies.
1661     if (!valueIsSplit(*ArgIt, VMap.getOffsets(*ArgIt))) {
1662       auto &VRegs = *VMap.getVRegs(cast<Value>(*ArgIt));
1663       assert(VRegs.empty() && "VRegs already populated?");
1664       VRegs.push_back(VArg);
1665     } else {
1666       unpackRegs(*ArgIt, VArg, EntryBuilder);
1667     }
1668     ArgIt++;
1669   }
1670
1671   // Need to visit defs before uses when translating instructions.
1672   ReversePostOrderTraversal<const Function *> RPOT(&F);
1673   for (const BasicBlock *BB : RPOT) {
1674     MachineBasicBlock &MBB = getMBB(*BB);
1675     // Set the insertion point of all the following translations to
1676     // the end of this basic block.
1677     CurBuilder.setMBB(MBB);
1678
1679     for (const Instruction &Inst : *BB) {
1680       if (translate(Inst))
1681         continue;
1682
1683       OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
1684                                  Inst.getDebugLoc(), BB);
1685       R << "unable to translate instruction: " << ore::NV("Opcode", &Inst);
1686
1687       if (ORE->allowExtraAnalysis("gisel-irtranslator")) {
1688         std::string InstStrStorage;
1689         raw_string_ostream InstStr(InstStrStorage);
1690         InstStr << Inst;
1691
1692         R << ": '" << InstStr.str() << "'";
1693       }
1694
1695       reportTranslationError(*MF, *TPC, *ORE, R);
1696       return false;
1697     }
1698   }
1699
1700   finishPendingPhis();
1701
1702   // Merge the argument lowering and constants block with its single
1703   // successor, the LLVM-IR entry block.  We want the basic block to
1704   // be maximal.
1705   assert(EntryBB->succ_size() == 1 &&
1706          "Custom BB used for lowering should have only one successor");
1707   // Get the successor of the current entry block.
1708   MachineBasicBlock &NewEntryBB = **EntryBB->succ_begin();
1709   assert(NewEntryBB.pred_size() == 1 &&
1710          "LLVM-IR entry block has a predecessor!?");
1711   // Move all the instruction from the current entry block to the
1712   // new entry block.
1713   NewEntryBB.splice(NewEntryBB.begin(), EntryBB, EntryBB->begin(),
1714                     EntryBB->end());
1715
1716   // Update the live-in information for the new entry block.
1717   for (const MachineBasicBlock::RegisterMaskPair &LiveIn : EntryBB->liveins())
1718     NewEntryBB.addLiveIn(LiveIn);
1719   NewEntryBB.sortUniqueLiveIns();
1720
1721   // Get rid of the now empty basic block.
1722   EntryBB->removeSuccessor(&NewEntryBB);
1723   MF->remove(EntryBB);
1724   MF->DeleteMachineBasicBlock(EntryBB);
1725
1726   assert(&MF->front() == &NewEntryBB &&
1727          "New entry wasn't next in the list of basic block!");
1728
1729   // Initialize stack protector information.
1730   StackProtector &SP = getAnalysis<StackProtector>();
1731   SP.copyToMachineFrameInfo(MF->getFrameInfo());
1732
1733   return false;
1734 }