1 //===- llvm/CodeGen/GlobalISel/RegisterBank.cpp - Register Bank --*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements the RegisterBank class.
11 //===----------------------------------------------------------------------===//
13 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
14 #include "llvm/CodeGen/TargetRegisterInfo.h"
15 #include "llvm/Config/llvm-config.h"
17 #define DEBUG_TYPE "registerbank"
21 const unsigned RegisterBank::InvalidID
= UINT_MAX
;
23 RegisterBank::RegisterBank(
24 unsigned ID
, const char *Name
, unsigned Size
,
25 const uint32_t *CoveredClasses
, unsigned NumRegClasses
)
26 : ID(ID
), Name(Name
), Size(Size
) {
27 ContainedRegClasses
.resize(NumRegClasses
);
28 ContainedRegClasses
.setBitsInMask(CoveredClasses
);
31 bool RegisterBank::verify(const TargetRegisterInfo
&TRI
) const {
32 assert(isValid() && "Invalid register bank");
33 for (unsigned RCId
= 0, End
= TRI
.getNumRegClasses(); RCId
!= End
; ++RCId
) {
34 const TargetRegisterClass
&RC
= *TRI
.getRegClass(RCId
);
38 // Verify that the register bank covers all the sub classes of the
41 // Use a different (slow in that case) method than
42 // RegisterBankInfo to find the subclasses of RC, to make sure
43 // both agree on the covers.
44 for (unsigned SubRCId
= 0; SubRCId
!= End
; ++SubRCId
) {
45 const TargetRegisterClass
&SubRC
= *TRI
.getRegClass(RCId
);
47 if (!RC
.hasSubClassEq(&SubRC
))
50 // Verify that the Size of the register bank is big enough to cover
51 // all the register classes it covers.
52 assert(getSize() >= TRI
.getRegSizeInBits(SubRC
) &&
53 "Size is not big enough for all the subclasses!");
54 assert(covers(SubRC
) && "Not all subclasses are covered");
60 bool RegisterBank::covers(const TargetRegisterClass
&RC
) const {
61 assert(isValid() && "RB hasn't been initialized yet");
62 return ContainedRegClasses
.test(RC
.getID());
65 bool RegisterBank::isValid() const {
66 return ID
!= InvalidID
&& Name
!= nullptr && Size
!= 0 &&
67 // A register bank that does not cover anything is useless.
68 !ContainedRegClasses
.empty();
71 bool RegisterBank::operator==(const RegisterBank
&OtherRB
) const {
72 // There must be only one instance of a given register bank alive
73 // for the whole compilation.
74 // The RegisterBankInfo is supposed to enforce that.
75 assert((OtherRB
.getID() != getID() || &OtherRB
== this) &&
76 "ID does not uniquely identify a RegisterBank");
77 return &OtherRB
== this;
80 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
81 LLVM_DUMP_METHOD
void RegisterBank::dump(const TargetRegisterInfo
*TRI
) const {
82 print(dbgs(), /* IsForDebug */ true, TRI
);
86 void RegisterBank::print(raw_ostream
&OS
, bool IsForDebug
,
87 const TargetRegisterInfo
*TRI
) const {
91 OS
<< "(ID:" << getID() << ", Size:" << getSize() << ")\n"
92 << "isValid:" << isValid() << '\n'
93 << "Number of Covered register classes: " << ContainedRegClasses
.count()
95 // Print all the subclasses if we can.
96 // This register classes may not be properly initialized yet.
97 if (!TRI
|| ContainedRegClasses
.empty())
99 assert(ContainedRegClasses
.size() == TRI
->getNumRegClasses() &&
100 "TRI does not match the initialization process?");
102 OS
<< "Covered register classes:\n";
103 for (unsigned RCId
= 0, End
= TRI
->getNumRegClasses(); RCId
!= End
; ++RCId
) {
104 const TargetRegisterClass
&RC
= *TRI
->getRegClass(RCId
);
111 OS
<< TRI
->getRegClassName(&RC
);