lib/CodeGen/MachineCSE.cpp

   1 //===- MachineCSE.cpp - Machine Common Subexpression Elimination Pass -----===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This pass performs global common subexpression elimination on machine
  11 // instructions using a scoped hash table based value numbering scheme. It
  12 // must be run while the machine function is still in SSA form.
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #include "llvm/ADT/DenseMap.h"
  17 #include "llvm/ADT/ScopedHashTable.h"
  18 #include "llvm/ADT/SmallPtrSet.h"
  19 #include "llvm/ADT/SmallSet.h"
  20 #include "llvm/ADT/SmallVector.h"
  21 #include "llvm/ADT/Statistic.h"
  22 #include "llvm/Analysis/AliasAnalysis.h"
  23 #include "llvm/CodeGen/MachineBasicBlock.h"
  24 #include "llvm/CodeGen/MachineDominators.h"
  25 #include "llvm/CodeGen/MachineFunction.h"
  26 #include "llvm/CodeGen/MachineFunctionPass.h"
  27 #include "llvm/CodeGen/MachineInstr.h"
  28 #include "llvm/CodeGen/MachineOperand.h"
  29 #include "llvm/CodeGen/MachineRegisterInfo.h"
  30 #include "llvm/CodeGen/Passes.h"
  31 #include "llvm/CodeGen/TargetInstrInfo.h"
  32 #include "llvm/CodeGen/TargetOpcodes.h"
  33 #include "llvm/CodeGen/TargetRegisterInfo.h"
  34 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  35 #include "llvm/MC/MCInstrDesc.h"
  36 #include "llvm/MC/MCRegisterInfo.h"
  37 #include "llvm/Pass.h"
  38 #include "llvm/Support/Allocator.h"
  39 #include "llvm/Support/Debug.h"
  40 #include "llvm/Support/RecyclingAllocator.h"
  41 #include "llvm/Support/raw_ostream.h"
  42 #include <cassert>
  43 #include <iterator>
  44 #include <utility>
  45 #include <vector>
  46
  47 using namespace llvm;
  48
  49 #define DEBUG_TYPE "machine-cse"
  50
  51 STATISTIC(NumCoalesces, "Number of copies coalesced");
  52 STATISTIC(NumCSEs,      "Number of common subexpression eliminated");
  53 STATISTIC(NumPhysCSEs,
  54           "Number of physreg referencing common subexpr eliminated");
  55 STATISTIC(NumCrossBBCSEs,
  56           "Number of cross-MBB physreg referencing CS eliminated");
  57 STATISTIC(NumCommutes,  "Number of copies coalesced after commuting");
  58
  59 namespace {
  60
  61   class MachineCSE : public MachineFunctionPass {
  62     const TargetInstrInfo *TII;
  63     const TargetRegisterInfo *TRI;
  64     AliasAnalysis *AA;
  65     MachineDominatorTree *DT;
  66     MachineRegisterInfo *MRI;
  67
  68   public:
  69     static char ID; // Pass identification
  70
  71     MachineCSE() : MachineFunctionPass(ID) {
  72       initializeMachineCSEPass(*PassRegistry::getPassRegistry());
  73     }
  74
  75     bool runOnMachineFunction(MachineFunction &MF) override;
  76
  77     void getAnalysisUsage(AnalysisUsage &AU) const override {
  78       AU.setPreservesCFG();
  79       MachineFunctionPass::getAnalysisUsage(AU);
  80       AU.addRequired<AAResultsWrapperPass>();
  81       AU.addPreservedID(MachineLoopInfoID);
  82       AU.addRequired<MachineDominatorTree>();
  83       AU.addPreserved<MachineDominatorTree>();
  84     }
  85
  86     void releaseMemory() override {
  87       ScopeMap.clear();
  88       Exps.clear();
  89     }
  90
  91   private:
  92     using AllocatorTy = RecyclingAllocator<BumpPtrAllocator,
  93                             ScopedHashTableVal<MachineInstr *, unsigned>>;
  94     using ScopedHTType =
  95         ScopedHashTable<MachineInstr *, unsigned, MachineInstrExpressionTrait,
  96                         AllocatorTy>;
  97     using ScopeType = ScopedHTType::ScopeTy;
  98
  99     unsigned LookAheadLimit = 0;
 100     DenseMap<MachineBasicBlock *, ScopeType *> ScopeMap;
 101     ScopedHTType VNT;
 102     SmallVector<MachineInstr *, 64> Exps;
 103     unsigned CurrVN = 0;
 104
 105     bool PerformTrivialCopyPropagation(MachineInstr *MI,
 106                                        MachineBasicBlock *MBB);
 107     bool isPhysDefTriviallyDead(unsigned Reg,
 108                                 MachineBasicBlock::const_iterator I,
 109                                 MachineBasicBlock::const_iterator E) const;
 110     bool hasLivePhysRegDefUses(const MachineInstr *MI,
 111                                const MachineBasicBlock *MBB,
 112                                SmallSet<unsigned,8> &PhysRefs,
 113                                SmallVectorImpl<unsigned> &PhysDefs,
 114                                bool &PhysUseDef) const;
 115     bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
 116                           SmallSet<unsigned,8> &PhysRefs,
 117                           SmallVectorImpl<unsigned> &PhysDefs,
 118                           bool &NonLocal) const;
 119     bool isCSECandidate(MachineInstr *MI);
 120     bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
 121                            MachineInstr *CSMI, MachineInstr *MI);
 122     void EnterScope(MachineBasicBlock *MBB);
 123     void ExitScope(MachineBasicBlock *MBB);
 124     bool ProcessBlock(MachineBasicBlock *MBB);
 125     void ExitScopeIfDone(MachineDomTreeNode *Node,
 126                          DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren);
 127     bool PerformCSE(MachineDomTreeNode *Node);
 128   };
 129
 130 } // end anonymous namespace
 131
 132 char MachineCSE::ID = 0;
 133
 134 char &llvm::MachineCSEID = MachineCSE::ID;
 135
 136 INITIALIZE_PASS_BEGIN(MachineCSE, DEBUG_TYPE,
 137                       "Machine Common Subexpression Elimination", false, false)
 138 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
 139 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
 140 INITIALIZE_PASS_END(MachineCSE, DEBUG_TYPE,
 141                     "Machine Common Subexpression Elimination", false, false)
 142
 143 /// The source register of a COPY machine instruction can be propagated to all
 144 /// its users, and this propagation could increase the probability of finding
 145 /// common subexpressions. If the COPY has only one user, the COPY itself can
 146 /// be removed.
 147 bool MachineCSE::PerformTrivialCopyPropagation(MachineInstr *MI,
 148                                                MachineBasicBlock *MBB) {
 149   bool Changed = false;
 150   for (MachineOperand &MO : MI->operands()) {
 151     if (!MO.isReg() || !MO.isUse())
 152       continue;
 153     unsigned Reg = MO.getReg();
 154     if (!TargetRegisterInfo::isVirtualRegister(Reg))
 155       continue;
 156     bool OnlyOneUse = MRI->hasOneNonDBGUse(Reg);
 157     MachineInstr *DefMI = MRI->getVRegDef(Reg);
 158     if (!DefMI->isCopy())
 159       continue;
 160     unsigned SrcReg = DefMI->getOperand(1).getReg();
 161     if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
 162       continue;
 163     if (DefMI->getOperand(0).getSubReg())
 164       continue;
 165     // FIXME: We should trivially coalesce subregister copies to expose CSE
 166     // opportunities on instructions with truncated operands (see
 167     // cse-add-with-overflow.ll). This can be done here as follows:
 168     // if (SrcSubReg)
 169     //  RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
 170     //                                     SrcSubReg);
 171     // MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
 172     //
 173     // The 2-addr pass has been updated to handle coalesced subregs. However,
 174     // some machine-specific code still can't handle it.
 175     // To handle it properly we also need a way find a constrained subregister
 176     // class given a super-reg class and subreg index.
 177     if (DefMI->getOperand(1).getSubReg())
 178       continue;
 179     if (!MRI->constrainRegAttrs(SrcReg, Reg))
 180       continue;
 181     LLVM_DEBUG(dbgs() << "Coalescing: " << *DefMI);
 182     LLVM_DEBUG(dbgs() << "***     to: " << *MI);
 183
 184     // Update matching debug values.
 185     DefMI->changeDebugValuesDefReg(SrcReg);
 186
 187     // Propagate SrcReg of copies to MI.
 188     MO.setReg(SrcReg);
 189     MRI->clearKillFlags(SrcReg);
 190     // Coalesce single use copies.
 191     if (OnlyOneUse) {
 192       DefMI->eraseFromParent();
 193       ++NumCoalesces;
 194     }
 195     Changed = true;
 196   }
 197
 198   return Changed;
 199 }
 200
 201 bool
 202 MachineCSE::isPhysDefTriviallyDead(unsigned Reg,
 203                                    MachineBasicBlock::const_iterator I,
 204                                    MachineBasicBlock::const_iterator E) const {
 205   unsigned LookAheadLeft = LookAheadLimit;
 206   while (LookAheadLeft) {
 207     // Skip over dbg_value's.
 208     I = skipDebugInstructionsForward(I, E);
 209
 210     if (I == E)
 211       // Reached end of block, we don't know if register is dead or not.
 212       return false;
 213
 214     bool SeenDef = false;
 215     for (const MachineOperand &MO : I->operands()) {
 216       if (MO.isRegMask() && MO.clobbersPhysReg(Reg))
 217         SeenDef = true;
 218       if (!MO.isReg() || !MO.getReg())
 219         continue;
 220       if (!TRI->regsOverlap(MO.getReg(), Reg))
 221         continue;
 222       if (MO.isUse())
 223         // Found a use!
 224         return false;
 225       SeenDef = true;
 226     }
 227     if (SeenDef)
 228       // See a def of Reg (or an alias) before encountering any use, it's
 229       // trivially dead.
 230       return true;
 231
 232     --LookAheadLeft;
 233     ++I;
 234   }
 235   return false;
 236 }
 237
 238 /// hasLivePhysRegDefUses - Return true if the specified instruction read/write
 239 /// physical registers (except for dead defs of physical registers). It also
 240 /// returns the physical register def by reference if it's the only one and the
 241 /// instruction does not uses a physical register.
 242 bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
 243                                        const MachineBasicBlock *MBB,
 244                                        SmallSet<unsigned,8> &PhysRefs,
 245                                        SmallVectorImpl<unsigned> &PhysDefs,
 246                                        bool &PhysUseDef) const{
 247   // First, add all uses to PhysRefs.
 248   for (const MachineOperand &MO : MI->operands()) {
 249     if (!MO.isReg() || MO.isDef())
 250       continue;
 251     unsigned Reg = MO.getReg();
 252     if (!Reg)
 253       continue;
 254     if (TargetRegisterInfo::isVirtualRegister(Reg))
 255       continue;
 256     // Reading either caller preserved or constant physregs is ok.
 257     if (!MRI->isCallerPreservedOrConstPhysReg(Reg))
 258       for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
 259         PhysRefs.insert(*AI);
 260   }
 261
 262   // Next, collect all defs into PhysDefs.  If any is already in PhysRefs
 263   // (which currently contains only uses), set the PhysUseDef flag.
 264   PhysUseDef = false;
 265   MachineBasicBlock::const_iterator I = MI; I = std::next(I);
 266   for (const MachineOperand &MO : MI->operands()) {
 267     if (!MO.isReg() || !MO.isDef())
 268       continue;
 269     unsigned Reg = MO.getReg();
 270     if (!Reg)
 271       continue;
 272     if (TargetRegisterInfo::isVirtualRegister(Reg))
 273       continue;
 274     // Check against PhysRefs even if the def is "dead".
 275     if (PhysRefs.count(Reg))
 276       PhysUseDef = true;
 277     // If the def is dead, it's ok. But the def may not marked "dead". That's
 278     // common since this pass is run before livevariables. We can scan
 279     // forward a few instructions and check if it is obviously dead.
 280     if (!MO.isDead() && !isPhysDefTriviallyDead(Reg, I, MBB->end()))
 281       PhysDefs.push_back(Reg);
 282   }
 283
 284   // Finally, add all defs to PhysRefs as well.
 285   for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i)
 286     for (MCRegAliasIterator AI(PhysDefs[i], TRI, true); AI.isValid(); ++AI)
 287       PhysRefs.insert(*AI);
 288
 289   return !PhysRefs.empty();
 290 }
 291
 292 bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
 293                                   SmallSet<unsigned,8> &PhysRefs,
 294                                   SmallVectorImpl<unsigned> &PhysDefs,
 295                                   bool &NonLocal) const {
 296   // For now conservatively returns false if the common subexpression is
 297   // not in the same basic block as the given instruction. The only exception
 298   // is if the common subexpression is in the sole predecessor block.
 299   const MachineBasicBlock *MBB = MI->getParent();
 300   const MachineBasicBlock *CSMBB = CSMI->getParent();
 301
 302   bool CrossMBB = false;
 303   if (CSMBB != MBB) {
 304     if (MBB->pred_size() != 1 || *MBB->pred_begin() != CSMBB)
 305       return false;
 306
 307     for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
 308       if (MRI->isAllocatable(PhysDefs[i]) || MRI->isReserved(PhysDefs[i]))
 309         // Avoid extending live range of physical registers if they are
 310         //allocatable or reserved.
 311         return false;
 312     }
 313     CrossMBB = true;
 314   }
 315   MachineBasicBlock::const_iterator I = CSMI; I = std::next(I);
 316   MachineBasicBlock::const_iterator E = MI;
 317   MachineBasicBlock::const_iterator EE = CSMBB->end();
 318   unsigned LookAheadLeft = LookAheadLimit;
 319   while (LookAheadLeft) {
 320     // Skip over dbg_value's.
 321     while (I != E && I != EE && I->isDebugInstr())
 322       ++I;
 323
 324     if (I == EE) {
 325       assert(CrossMBB && "Reaching end-of-MBB without finding MI?");
 326       (void)CrossMBB;
 327       CrossMBB = false;
 328       NonLocal = true;
 329       I = MBB->begin();
 330       EE = MBB->end();
 331       continue;
 332     }
 333
 334     if (I == E)
 335       return true;
 336
 337     for (const MachineOperand &MO : I->operands()) {
 338       // RegMasks go on instructions like calls that clobber lots of physregs.
 339       // Don't attempt to CSE across such an instruction.
 340       if (MO.isRegMask())
 341         return false;
 342       if (!MO.isReg() || !MO.isDef())
 343         continue;
 344       unsigned MOReg = MO.getReg();
 345       if (TargetRegisterInfo::isVirtualRegister(MOReg))
 346         continue;
 347       if (PhysRefs.count(MOReg))
 348         return false;
 349     }
 350
 351     --LookAheadLeft;
 352     ++I;
 353   }
 354
 355   return false;
 356 }
 357
 358 bool MachineCSE::isCSECandidate(MachineInstr *MI) {
 359   if (MI->isPosition() || MI->isPHI() || MI->isImplicitDef() || MI->isKill() ||
 360       MI->isInlineAsm() || MI->isDebugInstr())
 361     return false;
 362
 363   // Ignore copies.
 364   if (MI->isCopyLike())
 365     return false;
 366
 367   // Ignore stuff that we obviously can't move.
 368   if (MI->mayStore() || MI->isCall() || MI->isTerminator() ||
 369       MI->hasUnmodeledSideEffects())
 370     return false;
 371
 372   if (MI->mayLoad()) {
 373     // Okay, this instruction does a load. As a refinement, we allow the target
 374     // to decide whether the loaded value is actually a constant. If so, we can
 375     // actually use it as a load.
 376     if (!MI->isDereferenceableInvariantLoad(AA))
 377       // FIXME: we should be able to hoist loads with no other side effects if
 378       // there are no other instructions which can change memory in this loop.
 379       // This is a trivial form of alias analysis.
 380       return false;
 381   }
 382
 383   // Ignore stack guard loads, otherwise the register that holds CSEed value may
 384   // be spilled and get loaded back with corrupted data.
 385   if (MI->getOpcode() == TargetOpcode::LOAD_STACK_GUARD)
 386     return false;
 387
 388   return true;
 389 }
 390
 391 /// isProfitableToCSE - Return true if it's profitable to eliminate MI with a
 392 /// common expression that defines Reg.
 393 bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
 394                                    MachineInstr *CSMI, MachineInstr *MI) {
 395   // FIXME: Heuristics that works around the lack the live range splitting.
 396
 397   // If CSReg is used at all uses of Reg, CSE should not increase register
 398   // pressure of CSReg.
 399   bool MayIncreasePressure = true;
 400   if (TargetRegisterInfo::isVirtualRegister(CSReg) &&
 401       TargetRegisterInfo::isVirtualRegister(Reg)) {
 402     MayIncreasePressure = false;
 403     SmallPtrSet<MachineInstr*, 8> CSUses;
 404     for (MachineInstr &MI : MRI->use_nodbg_instructions(CSReg)) {
 405       CSUses.insert(&MI);
 406     }
 407     for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
 408       if (!CSUses.count(&MI)) {
 409         MayIncreasePressure = true;
 410         break;
 411       }
 412     }
 413   }
 414   if (!MayIncreasePressure) return true;
 415
 416   // Heuristics #1: Don't CSE "cheap" computation if the def is not local or in
 417   // an immediate predecessor. We don't want to increase register pressure and
 418   // end up causing other computation to be spilled.
 419   if (TII->isAsCheapAsAMove(*MI)) {
 420     MachineBasicBlock *CSBB = CSMI->getParent();
 421     MachineBasicBlock *BB = MI->getParent();
 422     if (CSBB != BB && !CSBB->isSuccessor(BB))
 423       return false;
 424   }
 425
 426   // Heuristics #2: If the expression doesn't not use a vr and the only use
 427   // of the redundant computation are copies, do not cse.
 428   bool HasVRegUse = false;
 429   for (const MachineOperand &MO : MI->operands()) {
 430     if (MO.isReg() && MO.isUse() &&
 431         TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
 432       HasVRegUse = true;
 433       break;
 434     }
 435   }
 436   if (!HasVRegUse) {
 437     bool HasNonCopyUse = false;
 438     for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
 439       // Ignore copies.
 440       if (!MI.isCopyLike()) {
 441         HasNonCopyUse = true;
 442         break;
 443       }
 444     }
 445     if (!HasNonCopyUse)
 446       return false;
 447   }
 448
 449   // Heuristics #3: If the common subexpression is used by PHIs, do not reuse
 450   // it unless the defined value is already used in the BB of the new use.
 451   bool HasPHI = false;
 452   for (MachineInstr &UseMI : MRI->use_nodbg_instructions(CSReg)) {
 453     HasPHI |= UseMI.isPHI();
 454     if (UseMI.getParent() == MI->getParent())
 455       return true;
 456   }
 457
 458   return !HasPHI;
 459 }
 460
 461 void MachineCSE::EnterScope(MachineBasicBlock *MBB) {
 462   LLVM_DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n');
 463   ScopeType *Scope = new ScopeType(VNT);
 464   ScopeMap[MBB] = Scope;
 465 }
 466
 467 void MachineCSE::ExitScope(MachineBasicBlock *MBB) {
 468   LLVM_DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n');
 469   DenseMap<MachineBasicBlock*, ScopeType*>::iterator SI = ScopeMap.find(MBB);
 470   assert(SI != ScopeMap.end());
 471   delete SI->second;
 472   ScopeMap.erase(SI);
 473 }
 474
 475 bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
 476   bool Changed = false;
 477
 478   SmallVector<std::pair<unsigned, unsigned>, 8> CSEPairs;
 479   SmallVector<unsigned, 2> ImplicitDefsToUpdate;
 480   SmallVector<unsigned, 2> ImplicitDefs;
 481   for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ) {
 482     MachineInstr *MI = &*I;
 483     ++I;
 484
 485     if (!isCSECandidate(MI))
 486       continue;
 487
 488     bool FoundCSE = VNT.count(MI);
 489     if (!FoundCSE) {
 490       // Using trivial copy propagation to find more CSE opportunities.
 491       if (PerformTrivialCopyPropagation(MI, MBB)) {
 492         Changed = true;
 493
 494         // After coalescing MI itself may become a copy.
 495         if (MI->isCopyLike())
 496           continue;
 497
 498         // Try again to see if CSE is possible.
 499         FoundCSE = VNT.count(MI);
 500       }
 501     }
 502
 503     // Commute commutable instructions.
 504     bool Commuted = false;
 505     if (!FoundCSE && MI->isCommutable()) {
 506       if (MachineInstr *NewMI = TII->commuteInstruction(*MI)) {
 507         Commuted = true;
 508         FoundCSE = VNT.count(NewMI);
 509         if (NewMI != MI) {
 510           // New instruction. It doesn't need to be kept.
 511           NewMI->eraseFromParent();
 512           Changed = true;
 513         } else if (!FoundCSE)
 514           // MI was changed but it didn't help, commute it back!
 515           (void)TII->commuteInstruction(*MI);
 516       }
 517     }
 518
 519     // If the instruction defines physical registers and the values *may* be
 520     // used, then it's not safe to replace it with a common subexpression.
 521     // It's also not safe if the instruction uses physical registers.
 522     bool CrossMBBPhysDef = false;
 523     SmallSet<unsigned, 8> PhysRefs;
 524     SmallVector<unsigned, 2> PhysDefs;
 525     bool PhysUseDef = false;
 526     if (FoundCSE && hasLivePhysRegDefUses(MI, MBB, PhysRefs,
 527                                           PhysDefs, PhysUseDef)) {
 528       FoundCSE = false;
 529
 530       // ... Unless the CS is local or is in the sole predecessor block
 531       // and it also defines the physical register which is not clobbered
 532       // in between and the physical register uses were not clobbered.
 533       // This can never be the case if the instruction both uses and
 534       // defines the same physical register, which was detected above.
 535       if (!PhysUseDef) {
 536         unsigned CSVN = VNT.lookup(MI);
 537         MachineInstr *CSMI = Exps[CSVN];
 538         if (PhysRegDefsReach(CSMI, MI, PhysRefs, PhysDefs, CrossMBBPhysDef))
 539           FoundCSE = true;
 540       }
 541     }
 542
 543     if (!FoundCSE) {
 544       VNT.insert(MI, CurrVN++);
 545       Exps.push_back(MI);
 546       continue;
 547     }
 548
 549     // Found a common subexpression, eliminate it.
 550     unsigned CSVN = VNT.lookup(MI);
 551     MachineInstr *CSMI = Exps[CSVN];
 552     LLVM_DEBUG(dbgs() << "Examining: " << *MI);
 553     LLVM_DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
 554
 555     // Check if it's profitable to perform this CSE.
 556     bool DoCSE = true;
 557     unsigned NumDefs = MI->getNumDefs();
 558
 559     for (unsigned i = 0, e = MI->getNumOperands(); NumDefs && i != e; ++i) {
 560       MachineOperand &MO = MI->getOperand(i);
 561       if (!MO.isReg() || !MO.isDef())
 562         continue;
 563       unsigned OldReg = MO.getReg();
 564       unsigned NewReg = CSMI->getOperand(i).getReg();
 565
 566       // Go through implicit defs of CSMI and MI, if a def is not dead at MI,
 567       // we should make sure it is not dead at CSMI.
 568       if (MO.isImplicit() && !MO.isDead() && CSMI->getOperand(i).isDead())
 569         ImplicitDefsToUpdate.push_back(i);
 570
 571       // Keep track of implicit defs of CSMI and MI, to clear possibly
 572       // made-redundant kill flags.
 573       if (MO.isImplicit() && !MO.isDead() && OldReg == NewReg)
 574         ImplicitDefs.push_back(OldReg);
 575
 576       if (OldReg == NewReg) {
 577         --NumDefs;
 578         continue;
 579       }
 580
 581       assert(TargetRegisterInfo::isVirtualRegister(OldReg) &&
 582              TargetRegisterInfo::isVirtualRegister(NewReg) &&
 583              "Do not CSE physical register defs!");
 584
 585       if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
 586         LLVM_DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
 587         DoCSE = false;
 588         break;
 589       }
 590
 591       // Don't perform CSE if the result of the new instruction cannot exist
 592       // within the constraints (register class, bank, or low-level type) of
 593       // the old instruction.
 594       if (!MRI->constrainRegAttrs(NewReg, OldReg)) {
 595         LLVM_DEBUG(
 596             dbgs() << "*** Not the same register constraints, avoid CSE!\n");
 597         DoCSE = false;
 598         break;
 599       }
 600
 601       CSEPairs.push_back(std::make_pair(OldReg, NewReg));
 602       --NumDefs;
 603     }
 604
 605     // Actually perform the elimination.
 606     if (DoCSE) {
 607       for (std::pair<unsigned, unsigned> &CSEPair : CSEPairs) {
 608         unsigned OldReg = CSEPair.first;
 609         unsigned NewReg = CSEPair.second;
 610         // OldReg may have been unused but is used now, clear the Dead flag
 611         MachineInstr *Def = MRI->getUniqueVRegDef(NewReg);
 612         assert(Def != nullptr && "CSEd register has no unique definition?");
 613         Def->clearRegisterDeads(NewReg);
 614         // Replace with NewReg and clear kill flags which may be wrong now.
 615         MRI->replaceRegWith(OldReg, NewReg);
 616         MRI->clearKillFlags(NewReg);
 617       }
 618
 619       // Go through implicit defs of CSMI and MI, if a def is not dead at MI,
 620       // we should make sure it is not dead at CSMI.
 621       for (unsigned ImplicitDefToUpdate : ImplicitDefsToUpdate)
 622         CSMI->getOperand(ImplicitDefToUpdate).setIsDead(false);
 623
 624       // Go through implicit defs of CSMI and MI, and clear the kill flags on
 625       // their uses in all the instructions between CSMI and MI.
 626       // We might have made some of the kill flags redundant, consider:
 627       //   subs  ... implicit-def %nzcv    <- CSMI
 628       //   csinc ... implicit killed %nzcv <- this kill flag isn't valid anymore
 629       //   subs  ... implicit-def %nzcv    <- MI, to be eliminated
 630       //   csinc ... implicit killed %nzcv
 631       // Since we eliminated MI, and reused a register imp-def'd by CSMI
 632       // (here %nzcv), that register, if it was killed before MI, should have
 633       // that kill flag removed, because it's lifetime was extended.
 634       if (CSMI->getParent() == MI->getParent()) {
 635         for (MachineBasicBlock::iterator II = CSMI, IE = MI; II != IE; ++II)
 636           for (auto ImplicitDef : ImplicitDefs)
 637             if (MachineOperand *MO = II->findRegisterUseOperand(
 638                     ImplicitDef, /*isKill=*/true, TRI))
 639               MO->setIsKill(false);
 640       } else {
 641         // If the instructions aren't in the same BB, bail out and clear the
 642         // kill flag on all uses of the imp-def'd register.
 643         for (auto ImplicitDef : ImplicitDefs)
 644           MRI->clearKillFlags(ImplicitDef);
 645       }
 646
 647       if (CrossMBBPhysDef) {
 648         // Add physical register defs now coming in from a predecessor to MBB
 649         // livein list.
 650         while (!PhysDefs.empty()) {
 651           unsigned LiveIn = PhysDefs.pop_back_val();
 652           if (!MBB->isLiveIn(LiveIn))
 653             MBB->addLiveIn(LiveIn);
 654         }
 655         ++NumCrossBBCSEs;
 656       }
 657
 658       MI->eraseFromParent();
 659       ++NumCSEs;
 660       if (!PhysRefs.empty())
 661         ++NumPhysCSEs;
 662       if (Commuted)
 663         ++NumCommutes;
 664       Changed = true;
 665     } else {
 666       VNT.insert(MI, CurrVN++);
 667       Exps.push_back(MI);
 668     }
 669     CSEPairs.clear();
 670     ImplicitDefsToUpdate.clear();
 671     ImplicitDefs.clear();
 672   }
 673
 674   return Changed;
 675 }
 676
 677 /// ExitScopeIfDone - Destroy scope for the MBB that corresponds to the given
 678 /// dominator tree node if its a leaf or all of its children are done. Walk
 679 /// up the dominator tree to destroy ancestors which are now done.
 680 void
 681 MachineCSE::ExitScopeIfDone(MachineDomTreeNode *Node,
 682                         DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren) {
 683   if (OpenChildren[Node])
 684     return;
 685
 686   // Pop scope.
 687   ExitScope(Node->getBlock());
 688
 689   // Now traverse upwards to pop ancestors whose offsprings are all done.
 690   while (MachineDomTreeNode *Parent = Node->getIDom()) {
 691     unsigned Left = --OpenChildren[Parent];
 692     if (Left != 0)
 693       break;
 694     ExitScope(Parent->getBlock());
 695     Node = Parent;
 696   }
 697 }
 698
 699 bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) {
 700   SmallVector<MachineDomTreeNode*, 32> Scopes;
 701   SmallVector<MachineDomTreeNode*, 8> WorkList;
 702   DenseMap<MachineDomTreeNode*, unsigned> OpenChildren;
 703
 704   CurrVN = 0;
 705
 706   // Perform a DFS walk to determine the order of visit.
 707   WorkList.push_back(Node);
 708   do {
 709     Node = WorkList.pop_back_val();
 710     Scopes.push_back(Node);
 711     const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
 712     OpenChildren[Node] = Children.size();
 713     for (MachineDomTreeNode *Child : Children)
 714       WorkList.push_back(Child);
 715   } while (!WorkList.empty());
 716
 717   // Now perform CSE.
 718   bool Changed = false;
 719   for (MachineDomTreeNode *Node : Scopes) {
 720     MachineBasicBlock *MBB = Node->getBlock();
 721     EnterScope(MBB);
 722     Changed |= ProcessBlock(MBB);
 723     // If it's a leaf node, it's done. Traverse upwards to pop ancestors.
 724     ExitScopeIfDone(Node, OpenChildren);
 725   }
 726
 727   return Changed;
 728 }
 729
 730 bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
 731   if (skipFunction(MF.getFunction()))
 732     return false;
 733
 734   TII = MF.getSubtarget().getInstrInfo();
 735   TRI = MF.getSubtarget().getRegisterInfo();
 736   MRI = &MF.getRegInfo();
 737   AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
 738   DT = &getAnalysis<MachineDominatorTree>();
 739   LookAheadLimit = TII->getMachineCSELookAheadLimit();
 740   return PerformCSE(DT->getRootNode());
 741 }