lib/CodeGen/RegUsageInfoCollector.cpp

   1 //===-- RegUsageInfoCollector.cpp - Register Usage Information Collector --===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 ///
  10 /// This pass is required to take advantage of the interprocedural register
  11 /// allocation infrastructure.
  12 ///
  13 /// This pass is simple MachineFunction pass which collects register usage
  14 /// details by iterating through each physical registers and checking
  15 /// MRI::isPhysRegUsed() then creates a RegMask based on this details.
  16 /// The pass then stores this RegMask in PhysicalRegisterUsageInfo.cpp
  17 ///
  18 //===----------------------------------------------------------------------===//
  19
  20 #include "llvm/ADT/Statistic.h"
  21 #include "llvm/CodeGen/MachineBasicBlock.h"
  22 #include "llvm/CodeGen/MachineFunctionPass.h"
  23 #include "llvm/CodeGen/MachineInstr.h"
  24 #include "llvm/CodeGen/MachineOperand.h"
  25 #include "llvm/CodeGen/MachineRegisterInfo.h"
  26 #include "llvm/CodeGen/Passes.h"
  27 #include "llvm/CodeGen/RegisterUsageInfo.h"
  28 #include "llvm/Support/Debug.h"
  29 #include "llvm/Support/raw_ostream.h"
  30 #include "llvm/CodeGen/TargetFrameLowering.h"
  31
  32 using namespace llvm;
  33
  34 #define DEBUG_TYPE "ip-regalloc"
  35
  36 STATISTIC(NumCSROpt,
  37           "Number of functions optimized for callee saved registers");
  38
  39 namespace {
  40
  41 class RegUsageInfoCollector : public MachineFunctionPass {
  42 public:
  43   RegUsageInfoCollector() : MachineFunctionPass(ID) {
  44     PassRegistry &Registry = *PassRegistry::getPassRegistry();
  45     initializeRegUsageInfoCollectorPass(Registry);
  46   }
  47
  48   StringRef getPassName() const override {
  49     return "Register Usage Information Collector Pass";
  50   }
  51
  52   void getAnalysisUsage(AnalysisUsage &AU) const override {
  53     AU.addRequired<PhysicalRegisterUsageInfo>();
  54     AU.setPreservesAll();
  55     MachineFunctionPass::getAnalysisUsage(AU);
  56   }
  57
  58   bool runOnMachineFunction(MachineFunction &MF) override;
  59
  60   // Call determineCalleeSaves and then also set the bits for subregs and
  61   // fully saved superregs.
  62   static void computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF);
  63
  64   static char ID;
  65 };
  66
  67 } // end of anonymous namespace
  68
  69 char RegUsageInfoCollector::ID = 0;
  70
  71 INITIALIZE_PASS_BEGIN(RegUsageInfoCollector, "RegUsageInfoCollector",
  72                       "Register Usage Information Collector", false, false)
  73 INITIALIZE_PASS_DEPENDENCY(PhysicalRegisterUsageInfo)
  74 INITIALIZE_PASS_END(RegUsageInfoCollector, "RegUsageInfoCollector",
  75                     "Register Usage Information Collector", false, false)
  76
  77 FunctionPass *llvm::createRegUsageInfoCollector() {
  78   return new RegUsageInfoCollector();
  79 }
  80
  81 bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) {
  82   MachineRegisterInfo *MRI = &MF.getRegInfo();
  83   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
  84   const TargetMachine &TM = MF.getTarget();
  85
  86   LLVM_DEBUG(dbgs() << " -------------------- " << getPassName()
  87                     << " -------------------- \n");
  88   LLVM_DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n");
  89
  90   std::vector<uint32_t> RegMask;
  91
  92   // Compute the size of the bit vector to represent all the registers.
  93   // The bit vector is broken into 32-bit chunks, thus takes the ceil of
  94   // the number of registers divided by 32 for the size.
  95   unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
  96   RegMask.resize(RegMaskSize, ~((uint32_t)0));
  97
  98   const Function &F = MF.getFunction();
  99
 100   PhysicalRegisterUsageInfo &PRUI = getAnalysis<PhysicalRegisterUsageInfo>();
 101   PRUI.setTargetMachine(TM);
 102
 103   LLVM_DEBUG(dbgs() << "Clobbered Registers: ");
 104
 105   BitVector SavedRegs;
 106   computeCalleeSavedRegs(SavedRegs, MF);
 107
 108   const BitVector &UsedPhysRegsMask = MRI->getUsedPhysRegsMask();
 109   auto SetRegAsDefined = [&RegMask] (unsigned Reg) {
 110     RegMask[Reg / 32] &= ~(1u << Reg % 32);
 111   };
 112   // Scan all the physical registers. When a register is defined in the current
 113   // function set it and all the aliasing registers as defined in the regmask.
 114   for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
 115     // Don't count registers that are saved and restored.
 116     if (SavedRegs.test(PReg))
 117       continue;
 118     // If a register is defined by an instruction mark it as defined together
 119     // with all it's unsaved aliases.
 120     if (!MRI->def_empty(PReg)) {
 121       for (MCRegAliasIterator AI(PReg, TRI, true); AI.isValid(); ++AI)
 122         if (!SavedRegs.test(*AI))
 123           SetRegAsDefined(*AI);
 124       continue;
 125     }
 126     // If a register is in the UsedPhysRegsMask set then mark it as defined.
 127     // All clobbered aliases will also be in the set, so we can skip setting
 128     // as defined all the aliases here.
 129     if (UsedPhysRegsMask.test(PReg))
 130       SetRegAsDefined(PReg);
 131   }
 132
 133   if (TargetFrameLowering::isSafeForNoCSROpt(F)) {
 134     ++NumCSROpt;
 135     LLVM_DEBUG(dbgs() << MF.getName()
 136                       << " function optimized for not having CSR.\n");
 137   }
 138
 139   for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg)
 140     if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg))
 141       LLVM_DEBUG(dbgs() << printReg(PReg, TRI) << " ");
 142
 143   LLVM_DEBUG(dbgs() << " \n----------------------------------------\n");
 144
 145   PRUI.storeUpdateRegUsageInfo(F, RegMask);
 146
 147   return false;
 148 }
 149
 150 void RegUsageInfoCollector::
 151 computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF) {
 152   const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
 153   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
 154
 155   // Target will return the set of registers that it saves/restores as needed.
 156   SavedRegs.clear();
 157   TFI.determineCalleeSaves(MF, SavedRegs);
 158
 159   // Insert subregs.
 160   const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
 161   for (unsigned i = 0; CSRegs[i]; ++i) {
 162     unsigned Reg = CSRegs[i];
 163     if (SavedRegs.test(Reg))
 164       for (MCSubRegIterator SR(Reg, &TRI, false); SR.isValid(); ++SR)
 165         SavedRegs.set(*SR);
 166   }
 167
 168   // Insert any register fully saved via subregisters.
 169   for (const TargetRegisterClass *RC : TRI.regclasses()) {
 170     if (!RC->CoveredBySubRegs)
 171        continue;
 172
 173     for (unsigned PReg = 1, PRegE = TRI.getNumRegs(); PReg < PRegE; ++PReg) {
 174       if (SavedRegs.test(PReg))
 175         continue;
 176
 177       // Check if PReg is fully covered by its subregs.
 178       if (!RC->contains(PReg))
 179         continue;
 180
 181       // Add PReg to SavedRegs if all subregs are saved.
 182       bool AllSubRegsSaved = true;
 183       for (MCSubRegIterator SR(PReg, &TRI, false); SR.isValid(); ++SR)
 184         if (!SavedRegs.test(*SR)) {
 185           AllSubRegsSaved = false;
 186           break;
 187         }
 188       if (AllSubRegsSaved)
 189         SavedRegs.set(PReg);
 190     }
 191   }
 192 }