lib/Target/AVR/AVRInstrInfo.cpp

   1 //===-- AVRInstrInfo.cpp - AVR Instruction Information --------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the AVR implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "AVRInstrInfo.h"
  15
  16 #include "llvm/ADT/STLExtras.h"
  17 #include "llvm/CodeGen/MachineConstantPool.h"
  18 #include "llvm/CodeGen/MachineFrameInfo.h"
  19 #include "llvm/CodeGen/MachineInstrBuilder.h"
  20 #include "llvm/CodeGen/MachineMemOperand.h"
  21 #include "llvm/IR/Constants.h"
  22 #include "llvm/IR/Function.h"
  23 #include "llvm/MC/MCContext.h"
  24 #include "llvm/Support/Debug.h"
  25 #include "llvm/Support/ErrorHandling.h"
  26 #include "llvm/Support/TargetRegistry.h"
  27
  28 #include "AVR.h"
  29 #include "AVRMachineFunctionInfo.h"
  30 #include "AVRRegisterInfo.h"
  31 #include "AVRTargetMachine.h"
  32 #include "MCTargetDesc/AVRMCTargetDesc.h"
  33
  34 #define GET_INSTRINFO_CTOR_DTOR
  35 #include "AVRGenInstrInfo.inc"
  36
  37 namespace llvm {
  38
  39 AVRInstrInfo::AVRInstrInfo()
  40     : AVRGenInstrInfo(AVR::ADJCALLSTACKDOWN, AVR::ADJCALLSTACKUP), RI() {}
  41
  42 void AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
  43                                MachineBasicBlock::iterator MI,
  44                                const DebugLoc &DL, unsigned DestReg,
  45                                unsigned SrcReg, bool KillSrc) const {
  46   const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
  47   const AVRRegisterInfo &TRI = *STI.getRegisterInfo();
  48   unsigned Opc;
  49
  50   // Not all AVR devices support the 16-bit `MOVW` instruction.
  51   if (AVR::DREGSRegClass.contains(DestReg, SrcReg)) {
  52     if (STI.hasMOVW()) {
  53       BuildMI(MBB, MI, DL, get(AVR::MOVWRdRr), DestReg)
  54           .addReg(SrcReg, getKillRegState(KillSrc));
  55     } else {
  56       unsigned DestLo, DestHi, SrcLo, SrcHi;
  57
  58       TRI.splitReg(DestReg, DestLo, DestHi);
  59       TRI.splitReg(SrcReg,  SrcLo,  SrcHi);
  60
  61       // Copy each individual register with the `MOV` instruction.
  62       BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestLo)
  63         .addReg(SrcLo, getKillRegState(KillSrc));
  64       BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestHi)
  65         .addReg(SrcHi, getKillRegState(KillSrc));
  66     }
  67   } else {
  68     if (AVR::GPR8RegClass.contains(DestReg, SrcReg)) {
  69       Opc = AVR::MOVRdRr;
  70     } else if (SrcReg == AVR::SP && AVR::DREGSRegClass.contains(DestReg)) {
  71       Opc = AVR::SPREAD;
  72     } else if (DestReg == AVR::SP && AVR::DREGSRegClass.contains(SrcReg)) {
  73       Opc = AVR::SPWRITE;
  74     } else {
  75       llvm_unreachable("Impossible reg-to-reg copy");
  76     }
  77
  78     BuildMI(MBB, MI, DL, get(Opc), DestReg)
  79         .addReg(SrcReg, getKillRegState(KillSrc));
  80   }
  81 }
  82
  83 unsigned AVRInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
  84                                            int &FrameIndex) const {
  85   switch (MI.getOpcode()) {
  86   case AVR::LDDRdPtrQ:
  87   case AVR::LDDWRdYQ: { //:FIXME: remove this once PR13375 gets fixed
  88     if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
  89         MI.getOperand(2).getImm() == 0) {
  90       FrameIndex = MI.getOperand(1).getIndex();
  91       return MI.getOperand(0).getReg();
  92     }
  93     break;
  94   }
  95   default:
  96     break;
  97   }
  98
  99   return 0;
 100 }
 101
 102 unsigned AVRInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
 103                                           int &FrameIndex) const {
 104   switch (MI.getOpcode()) {
 105   case AVR::STDPtrQRr:
 106   case AVR::STDWPtrQRr: {
 107     if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
 108         MI.getOperand(1).getImm() == 0) {
 109       FrameIndex = MI.getOperand(0).getIndex();
 110       return MI.getOperand(2).getReg();
 111     }
 112     break;
 113   }
 114   default:
 115     break;
 116   }
 117
 118   return 0;
 119 }
 120
 121 void AVRInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
 122                                        MachineBasicBlock::iterator MI,
 123                                        unsigned SrcReg, bool isKill,
 124                                        int FrameIndex,
 125                                        const TargetRegisterClass *RC,
 126                                        const TargetRegisterInfo *TRI) const {
 127   MachineFunction &MF = *MBB.getParent();
 128   AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
 129
 130   AFI->setHasSpills(true);
 131
 132   DebugLoc DL;
 133   if (MI != MBB.end()) {
 134     DL = MI->getDebugLoc();
 135   }
 136
 137   const MachineFrameInfo &MFI = MF.getFrameInfo();
 138
 139   MachineMemOperand *MMO = MF.getMachineMemOperand(
 140       MachinePointerInfo::getFixedStack(MF, FrameIndex),
 141       MachineMemOperand::MOStore, MFI.getObjectSize(FrameIndex),
 142       MFI.getObjectAlignment(FrameIndex));
 143
 144   unsigned Opcode = 0;
 145   if (TRI->isTypeLegalForClass(*RC, MVT::i8)) {
 146     Opcode = AVR::STDPtrQRr;
 147   } else if (TRI->isTypeLegalForClass(*RC, MVT::i16)) {
 148     Opcode = AVR::STDWPtrQRr;
 149   } else {
 150     llvm_unreachable("Cannot store this register into a stack slot!");
 151   }
 152
 153   BuildMI(MBB, MI, DL, get(Opcode))
 154       .addFrameIndex(FrameIndex)
 155       .addImm(0)
 156       .addReg(SrcReg, getKillRegState(isKill))
 157       .addMemOperand(MMO);
 158 }
 159
 160 void AVRInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
 161                                         MachineBasicBlock::iterator MI,
 162                                         unsigned DestReg, int FrameIndex,
 163                                         const TargetRegisterClass *RC,
 164                                         const TargetRegisterInfo *TRI) const {
 165   DebugLoc DL;
 166   if (MI != MBB.end()) {
 167     DL = MI->getDebugLoc();
 168   }
 169
 170   MachineFunction &MF = *MBB.getParent();
 171   const MachineFrameInfo &MFI = MF.getFrameInfo();
 172
 173   MachineMemOperand *MMO = MF.getMachineMemOperand(
 174       MachinePointerInfo::getFixedStack(MF, FrameIndex),
 175       MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIndex),
 176       MFI.getObjectAlignment(FrameIndex));
 177
 178   unsigned Opcode = 0;
 179   if (TRI->isTypeLegalForClass(*RC, MVT::i8)) {
 180     Opcode = AVR::LDDRdPtrQ;
 181   } else if (TRI->isTypeLegalForClass(*RC, MVT::i16)) {
 182     // Opcode = AVR::LDDWRdPtrQ;
 183     //:FIXME: remove this once PR13375 gets fixed
 184     Opcode = AVR::LDDWRdYQ;
 185   } else {
 186     llvm_unreachable("Cannot load this register from a stack slot!");
 187   }
 188
 189   BuildMI(MBB, MI, DL, get(Opcode), DestReg)
 190       .addFrameIndex(FrameIndex)
 191       .addImm(0)
 192       .addMemOperand(MMO);
 193 }
 194
 195 const MCInstrDesc &AVRInstrInfo::getBrCond(AVRCC::CondCodes CC) const {
 196   switch (CC) {
 197   default:
 198     llvm_unreachable("Unknown condition code!");
 199   case AVRCC::COND_EQ:
 200     return get(AVR::BREQk);
 201   case AVRCC::COND_NE:
 202     return get(AVR::BRNEk);
 203   case AVRCC::COND_GE:
 204     return get(AVR::BRGEk);
 205   case AVRCC::COND_LT:
 206     return get(AVR::BRLTk);
 207   case AVRCC::COND_SH:
 208     return get(AVR::BRSHk);
 209   case AVRCC::COND_LO:
 210     return get(AVR::BRLOk);
 211   case AVRCC::COND_MI:
 212     return get(AVR::BRMIk);
 213   case AVRCC::COND_PL:
 214     return get(AVR::BRPLk);
 215   }
 216 }
 217
 218 AVRCC::CondCodes AVRInstrInfo::getCondFromBranchOpc(unsigned Opc) const {
 219   switch (Opc) {
 220   default:
 221     return AVRCC::COND_INVALID;
 222   case AVR::BREQk:
 223     return AVRCC::COND_EQ;
 224   case AVR::BRNEk:
 225     return AVRCC::COND_NE;
 226   case AVR::BRSHk:
 227     return AVRCC::COND_SH;
 228   case AVR::BRLOk:
 229     return AVRCC::COND_LO;
 230   case AVR::BRMIk:
 231     return AVRCC::COND_MI;
 232   case AVR::BRPLk:
 233     return AVRCC::COND_PL;
 234   case AVR::BRGEk:
 235     return AVRCC::COND_GE;
 236   case AVR::BRLTk:
 237     return AVRCC::COND_LT;
 238   }
 239 }
 240
 241 AVRCC::CondCodes AVRInstrInfo::getOppositeCondition(AVRCC::CondCodes CC) const {
 242   switch (CC) {
 243   default:
 244     llvm_unreachable("Invalid condition!");
 245   case AVRCC::COND_EQ:
 246     return AVRCC::COND_NE;
 247   case AVRCC::COND_NE:
 248     return AVRCC::COND_EQ;
 249   case AVRCC::COND_SH:
 250     return AVRCC::COND_LO;
 251   case AVRCC::COND_LO:
 252     return AVRCC::COND_SH;
 253   case AVRCC::COND_GE:
 254     return AVRCC::COND_LT;
 255   case AVRCC::COND_LT:
 256     return AVRCC::COND_GE;
 257   case AVRCC::COND_MI:
 258     return AVRCC::COND_PL;
 259   case AVRCC::COND_PL:
 260     return AVRCC::COND_MI;
 261   }
 262 }
 263
 264 bool AVRInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
 265                                  MachineBasicBlock *&TBB,
 266                                  MachineBasicBlock *&FBB,
 267                                  SmallVectorImpl<MachineOperand> &Cond,
 268                                  bool AllowModify) const {
 269   // Start from the bottom of the block and work up, examining the
 270   // terminator instructions.
 271   MachineBasicBlock::iterator I = MBB.end();
 272   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
 273
 274   while (I != MBB.begin()) {
 275     --I;
 276     if (I->isDebugInstr()) {
 277       continue;
 278     }
 279
 280     // Working from the bottom, when we see a non-terminator
 281     // instruction, we're done.
 282     if (!isUnpredicatedTerminator(*I)) {
 283       break;
 284     }
 285
 286     // A terminator that isn't a branch can't easily be handled
 287     // by this analysis.
 288     if (!I->getDesc().isBranch()) {
 289       return true;
 290     }
 291
 292     // Handle unconditional branches.
 293     //:TODO: add here jmp
 294     if (I->getOpcode() == AVR::RJMPk) {
 295       UnCondBrIter = I;
 296
 297       if (!AllowModify) {
 298         TBB = I->getOperand(0).getMBB();
 299         continue;
 300       }
 301
 302       // If the block has any instructions after a JMP, delete them.
 303       while (std::next(I) != MBB.end()) {
 304         std::next(I)->eraseFromParent();
 305       }
 306
 307       Cond.clear();
 308       FBB = 0;
 309
 310       // Delete the JMP if it's equivalent to a fall-through.
 311       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
 312         TBB = 0;
 313         I->eraseFromParent();
 314         I = MBB.end();
 315         UnCondBrIter = MBB.end();
 316         continue;
 317       }
 318
 319       // TBB is used to indicate the unconditinal destination.
 320       TBB = I->getOperand(0).getMBB();
 321       continue;
 322     }
 323
 324     // Handle conditional branches.
 325     AVRCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode());
 326     if (BranchCode == AVRCC::COND_INVALID) {
 327       return true; // Can't handle indirect branch.
 328     }
 329
 330     // Working from the bottom, handle the first conditional branch.
 331     if (Cond.empty()) {
 332       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
 333       if (AllowModify && UnCondBrIter != MBB.end() &&
 334           MBB.isLayoutSuccessor(TargetBB)) {
 335         // If we can modify the code and it ends in something like:
 336         //
 337         //     jCC L1
 338         //     jmp L2
 339         //   L1:
 340         //     ...
 341         //   L2:
 342         //
 343         // Then we can change this to:
 344         //
 345         //     jnCC L2
 346         //   L1:
 347         //     ...
 348         //   L2:
 349         //
 350         // Which is a bit more efficient.
 351         // We conditionally jump to the fall-through block.
 352         BranchCode = getOppositeCondition(BranchCode);
 353         unsigned JNCC = getBrCond(BranchCode).getOpcode();
 354         MachineBasicBlock::iterator OldInst = I;
 355
 356         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
 357             .addMBB(UnCondBrIter->getOperand(0).getMBB());
 358         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(AVR::RJMPk))
 359             .addMBB(TargetBB);
 360
 361         OldInst->eraseFromParent();
 362         UnCondBrIter->eraseFromParent();
 363
 364         // Restart the analysis.
 365         UnCondBrIter = MBB.end();
 366         I = MBB.end();
 367         continue;
 368       }
 369
 370       FBB = TBB;
 371       TBB = I->getOperand(0).getMBB();
 372       Cond.push_back(MachineOperand::CreateImm(BranchCode));
 373       continue;
 374     }
 375
 376     // Handle subsequent conditional branches. Only handle the case where all
 377     // conditional branches branch to the same destination.
 378     assert(Cond.size() == 1);
 379     assert(TBB);
 380
 381     // Only handle the case where all conditional branches branch to
 382     // the same destination.
 383     if (TBB != I->getOperand(0).getMBB()) {
 384       return true;
 385     }
 386
 387     AVRCC::CondCodes OldBranchCode = (AVRCC::CondCodes)Cond[0].getImm();
 388     // If the conditions are the same, we can leave them alone.
 389     if (OldBranchCode == BranchCode) {
 390       continue;
 391     }
 392
 393     return true;
 394   }
 395
 396   return false;
 397 }
 398
 399 unsigned AVRInstrInfo::insertBranch(MachineBasicBlock &MBB,
 400                                     MachineBasicBlock *TBB,
 401                                     MachineBasicBlock *FBB,
 402                                     ArrayRef<MachineOperand> Cond,
 403                                     const DebugLoc &DL,
 404                                     int *BytesAdded) const {
 405   if (BytesAdded) *BytesAdded = 0;
 406
 407   // Shouldn't be a fall through.
 408   assert(TBB && "insertBranch must not be told to insert a fallthrough");
 409   assert((Cond.size() == 1 || Cond.size() == 0) &&
 410          "AVR branch conditions have one component!");
 411
 412   if (Cond.empty()) {
 413     assert(!FBB && "Unconditional branch with multiple successors!");
 414     auto &MI = *BuildMI(&MBB, DL, get(AVR::RJMPk)).addMBB(TBB);
 415     if (BytesAdded)
 416       *BytesAdded += getInstSizeInBytes(MI);
 417     return 1;
 418   }
 419
 420   // Conditional branch.
 421   unsigned Count = 0;
 422   AVRCC::CondCodes CC = (AVRCC::CondCodes)Cond[0].getImm();
 423   auto &CondMI = *BuildMI(&MBB, DL, getBrCond(CC)).addMBB(TBB);
 424
 425   if (BytesAdded) *BytesAdded += getInstSizeInBytes(CondMI);
 426   ++Count;
 427
 428   if (FBB) {
 429     // Two-way Conditional branch. Insert the second branch.
 430     auto &MI = *BuildMI(&MBB, DL, get(AVR::RJMPk)).addMBB(FBB);
 431     if (BytesAdded) *BytesAdded += getInstSizeInBytes(MI);
 432     ++Count;
 433   }
 434
 435   return Count;
 436 }
 437
 438 unsigned AVRInstrInfo::removeBranch(MachineBasicBlock &MBB,
 439                                     int *BytesRemoved) const {
 440   if (BytesRemoved) *BytesRemoved = 0;
 441
 442   MachineBasicBlock::iterator I = MBB.end();
 443   unsigned Count = 0;
 444
 445   while (I != MBB.begin()) {
 446     --I;
 447     if (I->isDebugInstr()) {
 448       continue;
 449     }
 450     //:TODO: add here the missing jmp instructions once they are implemented
 451     // like jmp, {e}ijmp, and other cond branches, ...
 452     if (I->getOpcode() != AVR::RJMPk &&
 453         getCondFromBranchOpc(I->getOpcode()) == AVRCC::COND_INVALID) {
 454       break;
 455     }
 456
 457     // Remove the branch.
 458     if (BytesRemoved) *BytesRemoved += getInstSizeInBytes(*I);
 459     I->eraseFromParent();
 460     I = MBB.end();
 461     ++Count;
 462   }
 463
 464   return Count;
 465 }
 466
 467 bool AVRInstrInfo::reverseBranchCondition(
 468     SmallVectorImpl<MachineOperand> &Cond) const {
 469   assert(Cond.size() == 1 && "Invalid AVR branch condition!");
 470
 471   AVRCC::CondCodes CC = static_cast<AVRCC::CondCodes>(Cond[0].getImm());
 472   Cond[0].setImm(getOppositeCondition(CC));
 473
 474   return false;
 475 }
 476
 477 unsigned AVRInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
 478   unsigned Opcode = MI.getOpcode();
 479
 480   switch (Opcode) {
 481   // A regular instruction
 482   default: {
 483     const MCInstrDesc &Desc = get(Opcode);
 484     return Desc.getSize();
 485   }
 486   case TargetOpcode::EH_LABEL:
 487   case TargetOpcode::IMPLICIT_DEF:
 488   case TargetOpcode::KILL:
 489   case TargetOpcode::DBG_VALUE:
 490     return 0;
 491   case TargetOpcode::INLINEASM: {
 492     const MachineFunction &MF = *MI.getParent()->getParent();
 493     const AVRTargetMachine &TM = static_cast<const AVRTargetMachine&>(MF.getTarget());
 494     const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
 495     const TargetInstrInfo &TII = *STI.getInstrInfo();
 496
 497     return TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
 498                                   *TM.getMCAsmInfo());
 499   }
 500   }
 501 }
 502
 503 MachineBasicBlock *
 504 AVRInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
 505   switch (MI.getOpcode()) {
 506   default:
 507     llvm_unreachable("unexpected opcode!");
 508   case AVR::JMPk:
 509   case AVR::CALLk:
 510   case AVR::RCALLk:
 511   case AVR::RJMPk:
 512   case AVR::BREQk:
 513   case AVR::BRNEk:
 514   case AVR::BRSHk:
 515   case AVR::BRLOk:
 516   case AVR::BRMIk:
 517   case AVR::BRPLk:
 518   case AVR::BRGEk:
 519   case AVR::BRLTk:
 520     return MI.getOperand(0).getMBB();
 521   case AVR::BRBSsk:
 522   case AVR::BRBCsk:
 523     return MI.getOperand(1).getMBB();
 524   case AVR::SBRCRrB:
 525   case AVR::SBRSRrB:
 526   case AVR::SBICAb:
 527   case AVR::SBISAb:
 528     llvm_unreachable("unimplemented branch instructions");
 529   }
 530 }
 531
 532 bool AVRInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
 533                                          int64_t BrOffset) const {
 534
 535   switch (BranchOp) {
 536   default:
 537     llvm_unreachable("unexpected opcode!");
 538   case AVR::JMPk:
 539   case AVR::CALLk:
 540     return true;
 541   case AVR::RCALLk:
 542   case AVR::RJMPk:
 543     return isIntN(13, BrOffset);
 544   case AVR::BRBSsk:
 545   case AVR::BRBCsk:
 546   case AVR::BREQk:
 547   case AVR::BRNEk:
 548   case AVR::BRSHk:
 549   case AVR::BRLOk:
 550   case AVR::BRMIk:
 551   case AVR::BRPLk:
 552   case AVR::BRGEk:
 553   case AVR::BRLTk:
 554     return isIntN(7, BrOffset);
 555   }
 556 }
 557
 558 unsigned AVRInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
 559                                             MachineBasicBlock &NewDestBB,
 560                                             const DebugLoc &DL,
 561                                             int64_t BrOffset,
 562                                             RegScavenger *RS) const {
 563     // This method inserts a *direct* branch (JMP), despite its name.
 564     // LLVM calls this method to fixup unconditional branches; it never calls
 565     // insertBranch or some hypothetical "insertDirectBranch".
 566     // See lib/CodeGen/RegisterRelaxation.cpp for details.
 567     // We end up here when a jump is too long for a RJMP instruction.
 568     auto &MI = *BuildMI(&MBB, DL, get(AVR::JMPk)).addMBB(&NewDestBB);
 569
 570     return getInstSizeInBytes(MI);
 571 }
 572
 573 } // end of namespace llvm
 574