| blob | 62f3d96af847b00bc86c506344de62f0fcda3456 |
1 //===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes the Sparc instructions in TableGen format.
11 //
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "SparcInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Feature predicates.
22 //===----------------------------------------------------------------------===//
24 // True when generating 32-bit code.
25 def Is32Bit : Predicate<"!Subtarget->is64Bit()">;
27 // True when generating 64-bit code. This also implies HasV9.
28 def Is64Bit : Predicate<"Subtarget->is64Bit()">;
30 def UseSoftMulDiv : Predicate<"Subtarget->useSoftMulDiv()">,
31 AssemblerPredicate<"FeatureSoftMulDiv">;
33 // HasV9 - This predicate is true when the target processor supports V9
34 // instructions. Note that the machine may be running in 32-bit mode.
35 def HasV9 : Predicate<"Subtarget->isV9()">,
36 AssemblerPredicate<"FeatureV9">;
38 // HasNoV9 - This predicate is true when the target doesn't have V9
39 // instructions. Use of this is just a hack for the isel not having proper
40 // costs for V8 instructions that are more expensive than their V9 ones.
41 def HasNoV9 : Predicate<"!Subtarget->isV9()">;
43 // HasVIS - This is true when the target processor has VIS extensions.
44 def HasVIS : Predicate<"Subtarget->isVIS()">,
45 AssemblerPredicate<"FeatureVIS">;
46 def HasVIS2 : Predicate<"Subtarget->isVIS2()">,
47 AssemblerPredicate<"FeatureVIS2">;
48 def HasVIS3 : Predicate<"Subtarget->isVIS3()">,
49 AssemblerPredicate<"FeatureVIS3">;
51 // HasHardQuad - This is true when the target processor supports quad floating
52 // point instructions.
53 def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">;
55 // HasLeonCASA - This is true when the target processor supports the CASA
56 // instruction
57 def HasLeonCASA : Predicate<"Subtarget->hasLeonCasa()">;
59 // HasPWRPSR - This is true when the target processor supports partial
60 // writes to the PSR register that only affects the ET field.
61 def HasPWRPSR : Predicate<"Subtarget->hasPWRPSR()">,
62 AssemblerPredicate<"FeaturePWRPSR">;
64 // HasUMAC_SMAC - This is true when the target processor supports the
65 // UMAC and SMAC instructions
66 def HasUMAC_SMAC : Predicate<"Subtarget->hasUmacSmac()">;
68 def HasNoFdivSqrtFix : Predicate<"!Subtarget->fixAllFDIVSQRT()">;
69 def HasFMULS : Predicate<"!Subtarget->hasNoFMULS()">;
70 def HasFSMULD : Predicate<"!Subtarget->hasNoFSMULD()">;
72 // UseDeprecatedInsts - This predicate is true when the target processor is a
73 // V8, or when it is V9 but the V8 deprecated instructions are efficient enough
74 // to use when appropriate. In either of these cases, the instruction selector
75 // will pick deprecated instructions.
76 def UseDeprecatedInsts : Predicate<"Subtarget->useDeprecatedV8Instructions()">;
78 //===----------------------------------------------------------------------===//
79 // Instruction Pattern Stuff
80 //===----------------------------------------------------------------------===//
82 def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
84 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
86 def LO10 : SDNodeXForm<imm, [{
87 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, SDLoc(N),
88 MVT::i32);
89 }]>;
91 def HI22 : SDNodeXForm<imm, [{
92 // Transformation function: shift the immediate value down into the low bits.
93 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, SDLoc(N),
94 MVT::i32);
95 }]>;
97 // Return the complement of a HI22 immediate value.
98 def HI22_not : SDNodeXForm<imm, [{
99 return CurDAG->getTargetConstant(~(unsigned)N->getZExtValue() >> 10, SDLoc(N),
100 MVT::i32);
101 }]>;
103 def SETHIimm : PatLeaf<(imm), [{
104 return isShiftedUInt<22, 10>(N->getZExtValue());
105 }], HI22>;
107 // The N->hasOneUse() prevents the immediate from being instantiated in both
108 // normal and complement form.
109 def SETHIimm_not : PatLeaf<(i32 imm), [{
110 return N->hasOneUse() && isShiftedUInt<22, 10>(~(unsigned)N->getZExtValue());
111 }], HI22_not>;
113 // Addressing modes.
114 def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
115 def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
117 // Address operands
118 def SparcMEMrrAsmOperand : AsmOperandClass {
119 let Name = "MEMrr";
120 let ParserMethod = "parseMEMOperand";
121 }
123 def SparcMEMriAsmOperand : AsmOperandClass {
124 let Name = "MEMri";
125 let ParserMethod = "parseMEMOperand";
126 }
128 def MEMrr : Operand<iPTR> {
129 let PrintMethod = "printMemOperand";
130 let MIOperandInfo = (ops ptr_rc, ptr_rc);
131 let ParserMatchClass = SparcMEMrrAsmOperand;
132 }
133 def MEMri : Operand<iPTR> {
134 let PrintMethod = "printMemOperand";
135 let MIOperandInfo = (ops ptr_rc, i32imm);
136 let ParserMatchClass = SparcMEMriAsmOperand;
137 }
139 def TLSSym : Operand<iPTR>;
141 // Branch targets have OtherVT type.
142 def brtarget : Operand<OtherVT> {
143 let EncoderMethod = "getBranchTargetOpValue";
144 }
146 def bprtarget : Operand<OtherVT> {
147 let EncoderMethod = "getBranchPredTargetOpValue";
148 }
150 def bprtarget16 : Operand<OtherVT> {
151 let EncoderMethod = "getBranchOnRegTargetOpValue";
152 }
154 def calltarget : Operand<i32> {
155 let EncoderMethod = "getCallTargetOpValue";
156 let DecoderMethod = "DecodeCall";
157 }
159 def simm13Op : Operand<i32> {
160 let DecoderMethod = "DecodeSIMM13";
161 }
163 // Operand for printing out a condition code.
164 let PrintMethod = "printCCOperand" in
165 def CCOp : Operand<i32>;
167 def SDTSPcmpicc :
168 SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
169 def SDTSPcmpfcc :
170 SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
171 def SDTSPbrcc :
172 SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
173 def SDTSPselectcc :
174 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
175 def SDTSPFTOI :
176 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
177 def SDTSPITOF :
178 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
179 def SDTSPFTOX :
180 SDTypeProfile<1, 1, [SDTCisVT<0, f64>, SDTCisFP<1>]>;
181 def SDTSPXTOF :
182 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f64>]>;
184 def SDTSPtlsadd :
185 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
186 def SDTSPtlsld :
187 SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
189 def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>;
190 def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
191 def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
192 def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
193 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
195 def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
196 def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
198 def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
199 def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
200 def SPftox : SDNode<"SPISD::FTOX", SDTSPFTOX>;
201 def SPxtof : SDNode<"SPISD::XTOF", SDTSPXTOF>;
203 def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>;
204 def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>;
205 def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>;
207 // These are target-independent nodes, but have target-specific formats.
208 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,
209 SDTCisVT<1, i32> ]>;
210 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
211 SDTCisVT<1, i32> ]>;
213 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
214 [SDNPHasChain, SDNPOutGlue]>;
215 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
216 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
218 def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
219 def call : SDNode<"SPISD::CALL", SDT_SPCall,
220 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
221 SDNPVariadic]>;
223 def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
224 def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet,
225 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
227 def flushw : SDNode<"SPISD::FLUSHW", SDTNone,
228 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;
230 def tlsadd : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>;
231 def tlsld : SDNode<"SPISD::TLS_LD", SDTSPtlsld>;
232 def tlscall : SDNode<"SPISD::TLS_CALL", SDT_SPCall,
233 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
234 SDNPVariadic]>;
236 def getPCX : Operand<iPTR> {
237 let PrintMethod = "printGetPCX";
238 }
240 //===----------------------------------------------------------------------===//
241 // SPARC Flag Conditions
242 //===----------------------------------------------------------------------===//
244 // Note that these values must be kept in sync with the CCOp::CondCode enum
245 // values.
246 class ICC_VAL<int N> : PatLeaf<(i32 N)>;
247 def ICC_NE : ICC_VAL< 9>; // Not Equal
248 def ICC_E : ICC_VAL< 1>; // Equal
249 def ICC_G : ICC_VAL<10>; // Greater
250 def ICC_LE : ICC_VAL< 2>; // Less or Equal
251 def ICC_GE : ICC_VAL<11>; // Greater or Equal
252 def ICC_L : ICC_VAL< 3>; // Less
253 def ICC_GU : ICC_VAL<12>; // Greater Unsigned
254 def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
255 def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
256 def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
257 def ICC_POS : ICC_VAL<14>; // Positive
258 def ICC_NEG : ICC_VAL< 6>; // Negative
259 def ICC_VC : ICC_VAL<15>; // Overflow Clear
260 def ICC_VS : ICC_VAL< 7>; // Overflow Set
262 class FCC_VAL<int N> : PatLeaf<(i32 N)>;
263 def FCC_U : FCC_VAL<23>; // Unordered
264 def FCC_G : FCC_VAL<22>; // Greater
265 def FCC_UG : FCC_VAL<21>; // Unordered or Greater
266 def FCC_L : FCC_VAL<20>; // Less
267 def FCC_UL : FCC_VAL<19>; // Unordered or Less
268 def FCC_LG : FCC_VAL<18>; // Less or Greater
269 def FCC_NE : FCC_VAL<17>; // Not Equal
270 def FCC_E : FCC_VAL<25>; // Equal
271 def FCC_UE : FCC_VAL<26>; // Unordered or Equal
272 def FCC_GE : FCC_VAL<27>; // Greater or Equal
273 def FCC_UGE : FCC_VAL<28>; // Unordered or Greater or Equal
274 def FCC_LE : FCC_VAL<29>; // Less or Equal
275 def FCC_ULE : FCC_VAL<30>; // Unordered or Less or Equal
276 def FCC_O : FCC_VAL<31>; // Ordered
278 class CPCC_VAL<int N> : PatLeaf<(i32 N)>;
279 def CPCC_3 : CPCC_VAL<39>; // 3
280 def CPCC_2 : CPCC_VAL<38>; // 2
281 def CPCC_23 : CPCC_VAL<37>; // 2 or 3
282 def CPCC_1 : CPCC_VAL<36>; // 1
283 def CPCC_13 : CPCC_VAL<35>; // 1 or 3
284 def CPCC_12 : CPCC_VAL<34>; // 1 or 2
285 def CPCC_123 : CPCC_VAL<33>; // 1 or 2 or 3
286 def CPCC_0 : CPCC_VAL<41>; // 0
287 def CPCC_03 : CPCC_VAL<42>; // 0 or 3
288 def CPCC_02 : CPCC_VAL<43>; // 0 or 2
289 def CPCC_023 : CPCC_VAL<44>; // 0 or 2 or 3
290 def CPCC_01 : CPCC_VAL<45>; // 0 or 1
291 def CPCC_013 : CPCC_VAL<46>; // 0 or 1 or 3
292 def CPCC_012 : CPCC_VAL<47>; // 0 or 1 or 2
294 //===----------------------------------------------------------------------===//
295 // Instruction Class Templates
296 //===----------------------------------------------------------------------===//
298 /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
299 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
300 RegisterClass RC, ValueType Ty, Operand immOp,
301 InstrItinClass itin = IIC_iu_instr> {
302 def rr : F3_1<2, Op3Val,
303 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
304 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
305 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))],
306 itin>;
307 def ri : F3_2<2, Op3Val,
308 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
309 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
310 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))],
311 itin>;
312 }
314 /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
315 /// pattern.
316 multiclass F3_12np<string OpcStr, bits<6> Op3Val, InstrItinClass itin = IIC_iu_instr> {
317 def rr : F3_1<2, Op3Val,
318 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
319 !strconcat(OpcStr, " $rs1, $rs2, $rd"), [],
320 itin>;
321 def ri : F3_2<2, Op3Val,
322 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
323 !strconcat(OpcStr, " $rs1, $simm13, $rd"), [],
324 itin>;
325 }
327 // Load multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
328 multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
329 RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_iu_instr> {
330 def rr : F3_1<3, Op3Val,
331 (outs RC:$dst), (ins MEMrr:$addr),
332 !strconcat(OpcStr, " [$addr], $dst"),
333 [(set Ty:$dst, (OpNode ADDRrr:$addr))],
334 itin>;
335 def ri : F3_2<3, Op3Val,
336 (outs RC:$dst), (ins MEMri:$addr),
337 !strconcat(OpcStr, " [$addr], $dst"),
338 [(set Ty:$dst, (OpNode ADDRri:$addr))],
339 itin>;
340 }
342 // TODO: Instructions of the LoadASI class are currently asm only; hooking up
343 // CodeGen's address spaces to use these is a future task.
344 class LoadASI<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
345 RegisterClass RC, ValueType Ty, InstrItinClass itin = NoItinerary> :
346 F3_1_asi<3, Op3Val, (outs RC:$dst), (ins MEMrr:$addr, i8imm:$asi),
347 !strconcat(OpcStr, "a [$addr] $asi, $dst"),
348 []>;
350 // LoadA multiclass - As above, but also define alternate address space variant
351 multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val,
352 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty,
353 InstrItinClass itin = NoItinerary> :
354 Load<OpcStr, Op3Val, OpNode, RC, Ty, itin> {
355 def Arr : LoadASI<OpcStr, LoadAOp3Val, OpNode, RC, Ty>;
356 }
358 // The LDSTUB instruction is supported for asm only.
359 // It is unlikely that general-purpose code could make use of it.
360 // CAS is preferred for sparc v9.
361 def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$dst), (ins MEMrr:$addr),
362 "ldstub [$addr], $dst", []>;
363 def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$dst), (ins MEMri:$addr),
364 "ldstub [$addr], $dst", []>;
365 def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$dst),
366 (ins MEMrr:$addr, i8imm:$asi),
367 "ldstuba [$addr] $asi, $dst", []>;
369 // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
370 multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
371 RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_st> {
372 def rr : F3_1<3, Op3Val,
373 (outs), (ins MEMrr:$addr, RC:$rd),
374 !strconcat(OpcStr, " $rd, [$addr]"),
375 [(OpNode Ty:$rd, ADDRrr:$addr)],
376 itin>;
377 def ri : F3_2<3, Op3Val,
378 (outs), (ins MEMri:$addr, RC:$rd),
379 !strconcat(OpcStr, " $rd, [$addr]"),
380 [(OpNode Ty:$rd, ADDRri:$addr)],
381 itin>;
382 }
384 // TODO: Instructions of the StoreASI class are currently asm only; hooking up
385 // CodeGen's address spaces to use these is a future task.
386 class StoreASI<string OpcStr, bits<6> Op3Val,
387 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty,
388 InstrItinClass itin = IIC_st> :
389 F3_1_asi<3, Op3Val, (outs), (ins MEMrr:$addr, RC:$rd, i8imm:$asi),
390 !strconcat(OpcStr, "a $rd, [$addr] $asi"),
391 [],
392 itin>;
394 multiclass StoreA<string OpcStr, bits<6> Op3Val, bits<6> StoreAOp3Val,
395 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty,
396 InstrItinClass itin = IIC_st> :
397 Store<OpcStr, Op3Val, OpNode, RC, Ty> {
398 def Arr : StoreASI<OpcStr, StoreAOp3Val, OpNode, RC, Ty, itin>;
399 }
401 //===----------------------------------------------------------------------===//
402 // Instructions
403 //===----------------------------------------------------------------------===//
405 // Pseudo instructions.
406 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
407 : InstSP<outs, ins, asmstr, pattern> {
408 let isCodeGenOnly = 1;
409 let isPseudo = 1;
410 }
412 // GETPCX for PIC
413 let Defs = [O7] in {
414 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
415 }
417 let Defs = [O6], Uses = [O6] in {
418 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
419 "!ADJCALLSTACKDOWN $amt1, $amt2",
420 [(callseq_start timm:$amt1, timm:$amt2)]>;
421 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
422 "!ADJCALLSTACKUP $amt1",
423 [(callseq_end timm:$amt1, timm:$amt2)]>;
424 }
426 let hasSideEffects = 1, mayStore = 1 in {
427 let rd = 0, rs1 = 0, rs2 = 0 in
428 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins),
429 "flushw",
430 [(flushw)]>, Requires<[HasV9]>;
431 let rd = 8, rs1 = 0, simm13 = 3 in
432 def TA3 : F3_2<0b10, 0b111010, (outs), (ins),
433 "ta 3",
434 [(flushw)]>;
435 }
437 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
438 // instruction selection into a branch sequence. This has to handle all
439 // permutations of selection between i32/f32/f64 on ICC and FCC.
440 // Expanded after instruction selection.
441 let Uses = [ICC], usesCustomInserter = 1 in {
442 def SELECT_CC_Int_ICC
443 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
444 "; SELECT_CC_Int_ICC PSEUDO!",
445 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>;
446 def SELECT_CC_FP_ICC
447 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
448 "; SELECT_CC_FP_ICC PSEUDO!",
449 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>;
451 def SELECT_CC_DFP_ICC
452 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
453 "; SELECT_CC_DFP_ICC PSEUDO!",
454 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>;
456 def SELECT_CC_QFP_ICC
457 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
458 "; SELECT_CC_QFP_ICC PSEUDO!",
459 [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
460 }
462 let usesCustomInserter = 1, Uses = [FCC0] in {
464 def SELECT_CC_Int_FCC
465 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
466 "; SELECT_CC_Int_FCC PSEUDO!",
467 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>;
469 def SELECT_CC_FP_FCC
470 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
471 "; SELECT_CC_FP_FCC PSEUDO!",
472 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>;
473 def SELECT_CC_DFP_FCC
474 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
475 "; SELECT_CC_DFP_FCC PSEUDO!",
476 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>;
477 def SELECT_CC_QFP_FCC
478 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
479 "; SELECT_CC_QFP_FCC PSEUDO!",
480 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
481 }
483 // Section B.1 - Load Integer Instructions, p. 90
484 let DecoderMethod = "DecodeLoadInt" in {
485 defm LDSB : LoadA<"ldsb", 0b001001, 0b011001, sextloadi8, IntRegs, i32>;
486 defm LDSH : LoadA<"ldsh", 0b001010, 0b011010, sextloadi16, IntRegs, i32>;
487 defm LDUB : LoadA<"ldub", 0b000001, 0b010001, zextloadi8, IntRegs, i32>;
488 defm LDUH : LoadA<"lduh", 0b000010, 0b010010, zextloadi16, IntRegs, i32>;
489 defm LD : LoadA<"ld", 0b000000, 0b010000, load, IntRegs, i32>;
490 }
492 let DecoderMethod = "DecodeLoadIntPair" in
493 defm LDD : LoadA<"ldd", 0b000011, 0b010011, load, IntPair, v2i32, IIC_ldd>;
495 // Section B.2 - Load Floating-point Instructions, p. 92
496 let DecoderMethod = "DecodeLoadFP" in {
497 defm LDF : Load<"ld", 0b100000, load, FPRegs, f32, IIC_iu_or_fpu_instr>;
498 def LDFArr : LoadASI<"ld", 0b110000, load, FPRegs, f32, IIC_iu_or_fpu_instr>,
499 Requires<[HasV9]>;
500 }
501 let DecoderMethod = "DecodeLoadDFP" in {
502 defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64, IIC_ldd>;
503 def LDDFArr : LoadASI<"ldd", 0b110011, load, DFPRegs, f64>,
504 Requires<[HasV9]>;
505 }
506 let DecoderMethod = "DecodeLoadQFP" in
507 defm LDQF : LoadA<"ldq", 0b100010, 0b110010, load, QFPRegs, f128>,
508 Requires<[HasV9, HasHardQuad]>;
510 let DecoderMethod = "DecodeLoadCP" in
511 defm LDC : Load<"ld", 0b110000, load, CoprocRegs, i32>;
512 let DecoderMethod = "DecodeLoadCPPair" in
513 defm LDDC : Load<"ldd", 0b110011, load, CoprocPair, v2i32, IIC_ldd>;
515 let DecoderMethod = "DecodeLoadCP", Defs = [CPSR] in {
516 let rd = 0 in {
517 def LDCSRrr : F3_1<3, 0b110001, (outs), (ins MEMrr:$addr),
518 "ld [$addr], %csr", []>;
519 def LDCSRri : F3_2<3, 0b110001, (outs), (ins MEMri:$addr),
520 "ld [$addr], %csr", []>;
521 }
522 }
524 let DecoderMethod = "DecodeLoadFP" in
525 let Defs = [FSR] in {
526 let rd = 0 in {
527 def LDFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr),
528 "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>;
529 def LDFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr),
530 "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>;
531 }
532 let rd = 1 in {
533 def LDXFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr),
534 "ldx [$addr], %fsr", []>, Requires<[HasV9]>;
535 def LDXFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr),
536 "ldx [$addr], %fsr", []>, Requires<[HasV9]>;
537 }
538 }
540 // Section B.4 - Store Integer Instructions, p. 95
541 let DecoderMethod = "DecodeStoreInt" in {
542 defm STB : StoreA<"stb", 0b000101, 0b010101, truncstorei8, IntRegs, i32>;
543 defm STH : StoreA<"sth", 0b000110, 0b010110, truncstorei16, IntRegs, i32>;
544 defm ST : StoreA<"st", 0b000100, 0b010100, store, IntRegs, i32>;
545 }
547 let DecoderMethod = "DecodeStoreIntPair" in
548 defm STD : StoreA<"std", 0b000111, 0b010111, store, IntPair, v2i32, IIC_std>;
550 // Section B.5 - Store Floating-point Instructions, p. 97
551 let DecoderMethod = "DecodeStoreFP" in {
552 defm STF : Store<"st", 0b100100, store, FPRegs, f32>;
553 def STFArr : StoreASI<"st", 0b110100, store, FPRegs, f32>,
554 Requires<[HasV9]>;
555 }
556 let DecoderMethod = "DecodeStoreDFP" in {
557 defm STDF : Store<"std", 0b100111, store, DFPRegs, f64, IIC_std>;
558 def STDFArr : StoreASI<"std", 0b110111, store, DFPRegs, f64>,
559 Requires<[HasV9]>;
560 }
561 let DecoderMethod = "DecodeStoreQFP" in
562 defm STQF : StoreA<"stq", 0b100110, 0b110110, store, QFPRegs, f128>,
563 Requires<[HasV9, HasHardQuad]>;
565 let DecoderMethod = "DecodeStoreCP" in
566 defm STC : Store<"st", 0b110100, store, CoprocRegs, i32>;
568 let DecoderMethod = "DecodeStoreCPPair" in
569 defm STDC : Store<"std", 0b110111, store, CoprocPair, v2i32, IIC_std>;
571 let DecoderMethod = "DecodeStoreCP", rd = 0 in {
572 let Defs = [CPSR] in {
573 def STCSRrr : F3_1<3, 0b110101, (outs MEMrr:$addr), (ins),
574 "st %csr, [$addr]", [], IIC_st>;
575 def STCSRri : F3_2<3, 0b110101, (outs MEMri:$addr), (ins),
576 "st %csr, [$addr]", [], IIC_st>;
577 }
578 let Defs = [CPQ] in {
579 def STDCQrr : F3_1<3, 0b110110, (outs MEMrr:$addr), (ins),
580 "std %cq, [$addr]", [], IIC_std>;
581 def STDCQri : F3_2<3, 0b110110, (outs MEMri:$addr), (ins),
582 "std %cq, [$addr]", [], IIC_std>;
583 }
584 }
586 let DecoderMethod = "DecodeStoreFP" in {
587 let rd = 0 in {
588 let Defs = [FSR] in {
589 def STFSRrr : F3_1<3, 0b100101, (outs MEMrr:$addr), (ins),
590 "st %fsr, [$addr]", [], IIC_st>;
591 def STFSRri : F3_2<3, 0b100101, (outs MEMri:$addr), (ins),
592 "st %fsr, [$addr]", [], IIC_st>;
593 }
594 let Defs = [FQ] in {
595 def STDFQrr : F3_1<3, 0b100110, (outs MEMrr:$addr), (ins),
596 "std %fq, [$addr]", [], IIC_std>;
597 def STDFQri : F3_2<3, 0b100110, (outs MEMri:$addr), (ins),
598 "std %fq, [$addr]", [], IIC_std>;
599 }
600 }
601 let rd = 1, Defs = [FSR] in {
602 def STXFSRrr : F3_1<3, 0b100101, (outs MEMrr:$addr), (ins),
603 "stx %fsr, [$addr]", []>, Requires<[HasV9]>;
604 def STXFSRri : F3_2<3, 0b100101, (outs MEMri:$addr), (ins),
605 "stx %fsr, [$addr]", []>, Requires<[HasV9]>;
606 }
607 }
609 // Section B.8 - SWAP Register with Memory Instruction
610 // (Atomic swap)
611 let Constraints = "$val = $dst", DecoderMethod = "DecodeSWAP" in {
612 def SWAPrr : F3_1<3, 0b001111,
613 (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val),
614 "swap [$addr], $dst",
615 [(set i32:$dst, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>;
616 def SWAPri : F3_2<3, 0b001111,
617 (outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val),
618 "swap [$addr], $dst",
619 [(set i32:$dst, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
620 def SWAPArr : F3_1_asi<3, 0b011111,
621 (outs IntRegs:$dst), (ins MEMrr:$addr, i8imm:$asi, IntRegs:$val),
622 "swapa [$addr] $asi, $dst",
623 [/*FIXME: pattern?*/]>;
624 }
627 // Section B.9 - SETHI Instruction, p. 104
628 def SETHIi: F2_1<0b100,
629 (outs IntRegs:$rd), (ins i32imm:$imm22),
630 "sethi $imm22, $rd",
631 [(set i32:$rd, SETHIimm:$imm22)],
632 IIC_iu_instr>;
634 // Section B.10 - NOP Instruction, p. 105
635 // (It's a special case of SETHI)
636 let rd = 0, imm22 = 0 in
637 def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
639 // Section B.11 - Logical Instructions, p. 106
640 defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, simm13Op>;
642 def ANDNrr : F3_1<2, 0b000101,
643 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
644 "andn $rs1, $rs2, $rd",
645 [(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>;
646 def ANDNri : F3_2<2, 0b000101,
647 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
648 "andn $rs1, $simm13, $rd", []>;
650 defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, simm13Op>;
652 def ORNrr : F3_1<2, 0b000110,
653 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
654 "orn $rs1, $rs2, $rd",
655 [(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>;
656 def ORNri : F3_2<2, 0b000110,
657 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
658 "orn $rs1, $simm13, $rd", []>;
659 defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, simm13Op>;
661 def XNORrr : F3_1<2, 0b000111,
662 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
663 "xnor $rs1, $rs2, $rd",
664 [(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>;
665 def XNORri : F3_2<2, 0b000111,
666 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
667 "xnor $rs1, $simm13, $rd", []>;
669 def : Pat<(and IntRegs:$rs1, SETHIimm_not:$rs2),
670 (ANDNrr i32:$rs1, (SETHIi SETHIimm_not:$rs2))>;
672 def : Pat<(or IntRegs:$rs1, SETHIimm_not:$rs2),
673 (ORNrr i32:$rs1, (SETHIi SETHIimm_not:$rs2))>;
675 let Defs = [ICC] in {
676 defm ANDCC : F3_12np<"andcc", 0b010001>;
677 defm ANDNCC : F3_12np<"andncc", 0b010101>;
678 defm ORCC : F3_12np<"orcc", 0b010010>;
679 defm ORNCC : F3_12np<"orncc", 0b010110>;
680 defm XORCC : F3_12np<"xorcc", 0b010011>;
681 defm XNORCC : F3_12np<"xnorcc", 0b010111>;
682 }
684 // Section B.12 - Shift Instructions, p. 107
685 defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, simm13Op>;
686 defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, simm13Op>;
687 defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, simm13Op>;
689 // Section B.13 - Add Instructions, p. 108
690 defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, simm13Op>;
692 // "LEA" forms of add (patterns to make tblgen happy)
693 let Predicates = [Is32Bit], isCodeGenOnly = 1 in
694 def LEA_ADDri : F3_2<2, 0b000000,
695 (outs IntRegs:$dst), (ins MEMri:$addr),
696 "add ${addr:arith}, $dst",
697 [(set iPTR:$dst, ADDRri:$addr)]>;
699 let Defs = [ICC] in
700 defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, simm13Op>;
702 let Uses = [ICC] in
703 defm ADDC : F3_12np<"addx", 0b001000>;
705 let Uses = [ICC], Defs = [ICC] in
706 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>;
708 // Section B.15 - Subtract Instructions, p. 110
709 defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, simm13Op>;
710 let Uses = [ICC], Defs = [ICC] in
711 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>;
713 let Defs = [ICC] in
714 defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, simm13Op>;
716 let Uses = [ICC] in
717 defm SUBC : F3_12np <"subx", 0b001100>;
719 // cmp (from Section A.3) is a specialized alias for subcc
720 let Defs = [ICC], rd = 0 in {
721 def CMPrr : F3_1<2, 0b010100,
722 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
723 "cmp $rs1, $rs2",
724 [(SPcmpicc i32:$rs1, i32:$rs2)]>;
725 def CMPri : F3_2<2, 0b010100,
726 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
727 "cmp $rs1, $simm13",
728 [(SPcmpicc i32:$rs1, (i32 simm13:$simm13))]>;
729 }
731 // Section B.18 - Multiply Instructions, p. 113
732 let Defs = [Y] in {
733 defm UMUL : F3_12<"umul", 0b001010, umullohi, IntRegs, i32, simm13Op, IIC_iu_umul>;
734 defm SMUL : F3_12<"smul", 0b001011, smullohi, IntRegs, i32, simm13Op, IIC_iu_smul>;
735 }
737 let Defs = [Y, ICC] in {
738 defm UMULCC : F3_12np<"umulcc", 0b011010, IIC_iu_umul>;
739 defm SMULCC : F3_12np<"smulcc", 0b011011, IIC_iu_smul>;
740 }
742 let Defs = [Y, ICC], Uses = [Y, ICC] in {
743 defm MULSCC : F3_12np<"mulscc", 0b100100>;
744 }
746 // Section B.19 - Divide Instructions, p. 115
747 let Uses = [Y], Defs = [Y] in {
748 defm UDIV : F3_12np<"udiv", 0b001110, IIC_iu_div>;
749 defm SDIV : F3_12np<"sdiv", 0b001111, IIC_iu_div>;
750 }
752 let Uses = [Y], Defs = [Y, ICC] in {
753 defm UDIVCC : F3_12np<"udivcc", 0b011110, IIC_iu_div>;
754 defm SDIVCC : F3_12np<"sdivcc", 0b011111, IIC_iu_div>;
755 }
757 // Section B.20 - SAVE and RESTORE, p. 117
758 defm SAVE : F3_12np<"save" , 0b111100>;
759 defm RESTORE : F3_12np<"restore", 0b111101>;
761 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
763 // unconditional branch class.
764 class BranchAlways<dag ins, string asmstr, list<dag> pattern>
765 : F2_2<0b010, 0, (outs), ins, asmstr, pattern> {
766 let isBranch = 1;
767 let isTerminator = 1;
768 let hasDelaySlot = 1;
769 let isBarrier = 1;
770 }
772 let cond = 8 in
773 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
776 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
778 // conditional branch class:
779 class BranchSP<dag ins, string asmstr, list<dag> pattern>
780 : F2_2<0b010, 0, (outs), ins, asmstr, pattern, IIC_iu_instr>;
782 // conditional branch with annul class:
783 class BranchSPA<dag ins, string asmstr, list<dag> pattern>
784 : F2_2<0b010, 1, (outs), ins, asmstr, pattern, IIC_iu_instr>;
786 // Conditional branch class on %icc|%xcc with predication:
787 multiclass IPredBranch<string regstr, list<dag> CCPattern> {
788 def CC : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
789 !strconcat("b$cond ", !strconcat(regstr, ", $imm19")),
790 CCPattern,
791 IIC_iu_instr>;
792 def CCA : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
793 !strconcat("b$cond,a ", !strconcat(regstr, ", $imm19")),
794 [],
795 IIC_iu_instr>;
796 def CCNT : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
797 !strconcat("b$cond,pn ", !strconcat(regstr, ", $imm19")),
798 [],
799 IIC_iu_instr>;
800 def CCANT : F2_3<0b001, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
801 !strconcat("b$cond,a,pn ", !strconcat(regstr, ", $imm19")),
802 [],
803 IIC_iu_instr>;
804 }
806 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
809 // Indirect branch instructions.
810 let isTerminator = 1, isBarrier = 1, hasDelaySlot = 1, isBranch =1,
811 isIndirectBranch = 1, rd = 0, isCodeGenOnly = 1 in {
812 def BINDrr : F3_1<2, 0b111000,
813 (outs), (ins MEMrr:$ptr),
814 "jmp $ptr",
815 [(brind ADDRrr:$ptr)]>;
816 def BINDri : F3_2<2, 0b111000,
817 (outs), (ins MEMri:$ptr),
818 "jmp $ptr",
819 [(brind ADDRri:$ptr)]>;
820 }
822 let Uses = [ICC] in {
823 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
824 "b$cond $imm22",
825 [(SPbricc bb:$imm22, imm:$cond)]>;
826 def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond),
827 "b$cond,a $imm22", []>;
829 let Predicates = [HasV9], cc = 0b00 in
830 defm BPI : IPredBranch<"%icc", []>;
831 }
833 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
835 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
837 // floating-point conditional branch class:
838 class FPBranchSP<dag ins, string asmstr, list<dag> pattern>
839 : F2_2<0b110, 0, (outs), ins, asmstr, pattern, IIC_fpu_normal_instr>;
841 // floating-point conditional branch with annul class:
842 class FPBranchSPA<dag ins, string asmstr, list<dag> pattern>
843 : F2_2<0b110, 1, (outs), ins, asmstr, pattern, IIC_fpu_normal_instr>;
845 // Conditional branch class on %fcc0-%fcc3 with predication:
846 multiclass FPredBranch {
847 def CC : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
848 FCCRegs:$cc),
849 "fb$cond $cc, $imm19", [], IIC_fpu_normal_instr>;
850 def CCA : F2_3<0b101, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
851 FCCRegs:$cc),
852 "fb$cond,a $cc, $imm19", [], IIC_fpu_normal_instr>;
853 def CCNT : F2_3<0b101, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
854 FCCRegs:$cc),
855 "fb$cond,pn $cc, $imm19", [], IIC_fpu_normal_instr>;
856 def CCANT : F2_3<0b101, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
857 FCCRegs:$cc),
858 "fb$cond,a,pn $cc, $imm19", [], IIC_fpu_normal_instr>;
859 }
860 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
862 let Uses = [FCC0] in {
863 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
864 "fb$cond $imm22",
865 [(SPbrfcc bb:$imm22, imm:$cond)]>;
866 def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
867 "fb$cond,a $imm22", []>;
868 }
870 let Predicates = [HasV9] in
871 defm BPF : FPredBranch;
873 // Section B.22 - Branch on Co-processor Condition Codes Instructions, p. 123
874 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
876 // co-processor conditional branch class:
877 class CPBranchSP<dag ins, string asmstr, list<dag> pattern>
878 : F2_2<0b111, 0, (outs), ins, asmstr, pattern>;
880 // co-processor conditional branch with annul class:
881 class CPBranchSPA<dag ins, string asmstr, list<dag> pattern>
882 : F2_2<0b111, 1, (outs), ins, asmstr, pattern>;
884 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
886 def CBCOND : CPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
887 "cb$cond $imm22",
888 [(SPbrfcc bb:$imm22, imm:$cond)]>;
889 def CBCONDA : CPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
890 "cb$cond,a $imm22", []>;
892 // Section B.24 - Call and Link Instruction, p. 125
893 // This is the only Format 1 instruction
894 let Uses = [O6],
895 hasDelaySlot = 1, isCall = 1 in {
896 def CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops),
897 "call $disp",
898 [],
899 IIC_jmp_or_call> {
900 bits<30> disp;
901 let op = 1;
902 let Inst{29-0} = disp;
903 }
905 // indirect calls: special cases of JMPL.
906 let isCodeGenOnly = 1, rd = 15 in {
907 def CALLrr : F3_1<2, 0b111000,
908 (outs), (ins MEMrr:$ptr, variable_ops),
909 "call $ptr",
910 [(call ADDRrr:$ptr)],
911 IIC_jmp_or_call>;
912 def CALLri : F3_2<2, 0b111000,
913 (outs), (ins MEMri:$ptr, variable_ops),
914 "call $ptr",
915 [(call ADDRri:$ptr)],
916 IIC_jmp_or_call>;
917 }
918 }
920 // Section B.25 - Jump and Link Instruction
922 // JMPL Instruction.
923 let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
924 DecoderMethod = "DecodeJMPL" in {
925 def JMPLrr: F3_1<2, 0b111000,
926 (outs IntRegs:$dst), (ins MEMrr:$addr),
927 "jmpl $addr, $dst",
928 [],
929 IIC_jmp_or_call>;
930 def JMPLri: F3_2<2, 0b111000,
931 (outs IntRegs:$dst), (ins MEMri:$addr),
932 "jmpl $addr, $dst",
933 [],
934 IIC_jmp_or_call>;
935 }
937 // Section A.3 - Synthetic Instructions, p. 85
938 // special cases of JMPL:
939 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
940 isCodeGenOnly = 1 in {
941 let rd = 0, rs1 = 15 in
942 def RETL: F3_2<2, 0b111000,
943 (outs), (ins i32imm:$val),
944 "jmp %o7+$val",
945 [(retflag simm13:$val)],
946 IIC_jmp_or_call>;
948 let rd = 0, rs1 = 31 in
949 def RET: F3_2<2, 0b111000,
950 (outs), (ins i32imm:$val),
951 "jmp %i7+$val",
952 [],
953 IIC_jmp_or_call>;
954 }
956 // Section B.26 - Return from Trap Instruction
957 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1,
958 isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in {
959 def RETTrr : F3_1<2, 0b111001,
960 (outs), (ins MEMrr:$addr),
961 "rett $addr",
962 [],
963 IIC_jmp_or_call>;
964 def RETTri : F3_2<2, 0b111001,
965 (outs), (ins MEMri:$addr),
966 "rett $addr",
967 [],
968 IIC_jmp_or_call>;
969 }
972 // Section B.27 - Trap on Integer Condition Codes Instruction
973 // conditional branch class:
974 let DecoderNamespace = "SparcV8", DecoderMethod = "DecodeTRAP", hasSideEffects = 1, Uses = [ICC], cc = 0b00 in
975 {
976 def TRAPrr : TRAPSPrr<0b111010,
977 (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond),
978 "t$cond $rs1 + $rs2",
979 []>;
980 def TRAPri : TRAPSPri<0b111010,
981 (outs), (ins IntRegs:$rs1, i32imm:$imm, CCOp:$cond),
982 "t$cond $rs1 + $imm",
983 []>;
984 }
986 multiclass TRAP<string regStr> {
987 def rr : TRAPSPrr<0b111010,
988 (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond),
989 !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $rs2"),
990 []>;
991 def ri : TRAPSPri<0b111010,
992 (outs), (ins IntRegs:$rs1, i32imm:$imm, CCOp:$cond),
993 !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $imm"),
994 []>;
995 }
997 let DecoderNamespace = "SparcV9", DecoderMethod = "DecodeTRAP", Predicates = [HasV9], hasSideEffects = 1, Uses = [ICC], cc = 0b00 in
998 defm TICC : TRAP<"%icc">;
1001 let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in
1002 def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>;
1004 let hasSideEffects = 1, rd = 0b01000, rs1 = 0, simm13 = 1 in
1005 def TA1 : F3_2<0b10, 0b111010, (outs), (ins), "ta 1", [(debugtrap)]>;
1007 // Section B.28 - Read State Register Instructions
1008 let rs2 = 0 in
1009 def RDASR : F3_1<2, 0b101000,
1010 (outs IntRegs:$rd), (ins ASRRegs:$rs1),
1011 "rd $rs1, $rd", []>;
1013 // PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
1014 let Predicates = [HasNoV9] in {
1015 let rs2 = 0, rs1 = 0, Uses=[PSR] in
1016 def RDPSR : F3_1<2, 0b101001,
1017 (outs IntRegs:$rd), (ins),
1018 "rd %psr, $rd", []>;
1020 let rs2 = 0, rs1 = 0, Uses=[WIM] in
1021 def RDWIM : F3_1<2, 0b101010,
1022 (outs IntRegs:$rd), (ins),
1023 "rd %wim, $rd", []>;
1025 let rs2 = 0, rs1 = 0, Uses=[TBR] in
1026 def RDTBR : F3_1<2, 0b101011,
1027 (outs IntRegs:$rd), (ins),
1028 "rd %tbr, $rd", []>;
1029 }
1031 // Section B.29 - Write State Register Instructions
1032 def WRASRrr : F3_1<2, 0b110000,
1033 (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
1034 "wr $rs1, $rs2, $rd", []>;
1035 def WRASRri : F3_2<2, 0b110000,
1036 (outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
1037 "wr $rs1, $simm13, $rd", []>;
1039 // PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
1040 let Predicates = [HasNoV9] in {
1041 let Defs = [PSR], rd=0 in {
1042 def WRPSRrr : F3_1<2, 0b110001,
1043 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
1044 "wr $rs1, $rs2, %psr", []>;
1045 def WRPSRri : F3_2<2, 0b110001,
1046 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
1047 "wr $rs1, $simm13, %psr", []>;
1048 }
1050 let Defs = [WIM], rd=0 in {
1051 def WRWIMrr : F3_1<2, 0b110010,
1052 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
1053 "wr $rs1, $rs2, %wim", []>;
1054 def WRWIMri : F3_2<2, 0b110010,
1055 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
1056 "wr $rs1, $simm13, %wim", []>;
1057 }
1059 let Defs = [TBR], rd=0 in {
1060 def WRTBRrr : F3_1<2, 0b110011,
1061 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
1062 "wr $rs1, $rs2, %tbr", []>;
1063 def WRTBRri : F3_2<2, 0b110011,
1064 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
1065 "wr $rs1, $simm13, %tbr", []>;
1066 }
1067 }
1069 // Section B.30 - STBAR Instruction
1070 let hasSideEffects = 1, rd = 0, rs1 = 0b01111, rs2 = 0 in
1071 def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>;
1074 // Section B.31 - Unimplmented Instruction
1075 let rd = 0 in
1076 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$imm22),
1077 "unimp $imm22", []>;
1079 // Section B.32 - Flush Instruction Memory
1080 let rd = 0 in {
1081 def FLUSHrr : F3_1<2, 0b111011, (outs), (ins MEMrr:$addr),
1082 "flush $addr", []>;
1083 def FLUSHri : F3_2<2, 0b111011, (outs), (ins MEMri:$addr),
1084 "flush $addr", []>;
1086 // The no-arg FLUSH is only here for the benefit of the InstAlias
1087 // "flush", which cannot seem to use FLUSHrr, due to the inability
1088 // to construct a MEMrr with fixed G0 registers.
1089 let rs1 = 0, rs2 = 0 in
1090 def FLUSH : F3_1<2, 0b111011, (outs), (ins), "flush %g0", []>;
1091 }
1093 // Section B.33 - Floating-point Operate (FPop) Instructions
1095 // Convert Integer to Floating-point Instructions, p. 141
1096 def FITOS : F3_3u<2, 0b110100, 0b011000100,
1097 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1098 "fitos $rs2, $rd",
1099 [(set FPRegs:$rd, (SPitof FPRegs:$rs2))],
1100 IIC_fpu_fast_instr>;
1101 def FITOD : F3_3u<2, 0b110100, 0b011001000,
1102 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
1103 "fitod $rs2, $rd",
1104 [(set DFPRegs:$rd, (SPitof FPRegs:$rs2))],
1105 IIC_fpu_fast_instr>;
1106 def FITOQ : F3_3u<2, 0b110100, 0b011001100,
1107 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
1108 "fitoq $rs2, $rd",
1109 [(set QFPRegs:$rd, (SPitof FPRegs:$rs2))]>,
1110 Requires<[HasHardQuad]>;
1112 // Convert Floating-point to Integer Instructions, p. 142
1113 def FSTOI : F3_3u<2, 0b110100, 0b011010001,
1114 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1115 "fstoi $rs2, $rd",
1116 [(set FPRegs:$rd, (SPftoi FPRegs:$rs2))],
1117 IIC_fpu_fast_instr>;
1118 def FDTOI : F3_3u<2, 0b110100, 0b011010010,
1119 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
1120 "fdtoi $rs2, $rd",
1121 [(set FPRegs:$rd, (SPftoi DFPRegs:$rs2))],
1122 IIC_fpu_fast_instr>;
1123 def FQTOI : F3_3u<2, 0b110100, 0b011010011,
1124 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
1125 "fqtoi $rs2, $rd",
1126 [(set FPRegs:$rd, (SPftoi QFPRegs:$rs2))]>,
1127 Requires<[HasHardQuad]>;
1129 // Convert between Floating-point Formats Instructions, p. 143
1130 def FSTOD : F3_3u<2, 0b110100, 0b011001001,
1131 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
1132 "fstod $rs2, $rd",
1133 [(set f64:$rd, (fpextend f32:$rs2))],
1134 IIC_fpu_stod>;
1135 def FSTOQ : F3_3u<2, 0b110100, 0b011001101,
1136 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
1137 "fstoq $rs2, $rd",
1138 [(set f128:$rd, (fpextend f32:$rs2))]>,
1139 Requires<[HasHardQuad]>;
1140 def FDTOS : F3_3u<2, 0b110100, 0b011000110,
1141 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
1142 "fdtos $rs2, $rd",
1143 [(set f32:$rd, (fpround f64:$rs2))],
1144 IIC_fpu_fast_instr>;
1145 def FDTOQ : F3_3u<2, 0b110100, 0b011001110,
1146 (outs QFPRegs:$rd), (ins DFPRegs:$rs2),
1147 "fdtoq $rs2, $rd",
1148 [(set f128:$rd, (fpextend f64:$rs2))]>,
1149 Requires<[HasHardQuad]>;
1150 def FQTOS : F3_3u<2, 0b110100, 0b011000111,
1151 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
1152 "fqtos $rs2, $rd",
1153 [(set f32:$rd, (fpround f128:$rs2))]>,
1154 Requires<[HasHardQuad]>;
1155 def FQTOD : F3_3u<2, 0b110100, 0b011001011,
1156 (outs DFPRegs:$rd), (ins QFPRegs:$rs2),
1157 "fqtod $rs2, $rd",
1158 [(set f64:$rd, (fpround f128:$rs2))]>,
1159 Requires<[HasHardQuad]>;
1161 // Floating-point Move Instructions, p. 144
1162 def FMOVS : F3_3u<2, 0b110100, 0b000000001,
1163 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1164 "fmovs $rs2, $rd", []>;
1165 def FNEGS : F3_3u<2, 0b110100, 0b000000101,
1166 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1167 "fnegs $rs2, $rd",
1168 [(set f32:$rd, (fneg f32:$rs2))],
1169 IIC_fpu_negs>;
1170 def FABSS : F3_3u<2, 0b110100, 0b000001001,
1171 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1172 "fabss $rs2, $rd",
1173 [(set f32:$rd, (fabs f32:$rs2))],
1174 IIC_fpu_abs>;
1177 // Floating-point Square Root Instructions, p.145
1178 // FSQRTS generates an erratum on LEON processors, so by disabling this instruction
1179 // this will be promoted to use FSQRTD with doubles instead.
1180 let Predicates = [HasNoFdivSqrtFix] in
1181 def FSQRTS : F3_3u<2, 0b110100, 0b000101001,
1182 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1183 "fsqrts $rs2, $rd",
1184 [(set f32:$rd, (fsqrt f32:$rs2))],
1185 IIC_fpu_sqrts>;
1186 def FSQRTD : F3_3u<2, 0b110100, 0b000101010,
1187 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1188 "fsqrtd $rs2, $rd",
1189 [(set f64:$rd, (fsqrt f64:$rs2))],
1190 IIC_fpu_sqrtd>;
1191 def FSQRTQ : F3_3u<2, 0b110100, 0b000101011,
1192 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1193 "fsqrtq $rs2, $rd",
1194 [(set f128:$rd, (fsqrt f128:$rs2))]>,
1195 Requires<[HasHardQuad]>;
1199 // Floating-point Add and Subtract Instructions, p. 146
1200 def FADDS : F3_3<2, 0b110100, 0b001000001,
1201 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1202 "fadds $rs1, $rs2, $rd",
1203 [(set f32:$rd, (fadd f32:$rs1, f32:$rs2))],
1204 IIC_fpu_fast_instr>;
1205 def FADDD : F3_3<2, 0b110100, 0b001000010,
1206 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1207 "faddd $rs1, $rs2, $rd",
1208 [(set f64:$rd, (fadd f64:$rs1, f64:$rs2))],
1209 IIC_fpu_fast_instr>;
1210 def FADDQ : F3_3<2, 0b110100, 0b001000011,
1211 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1212 "faddq $rs1, $rs2, $rd",
1213 [(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>,
1214 Requires<[HasHardQuad]>;
1216 def FSUBS : F3_3<2, 0b110100, 0b001000101,
1217 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1218 "fsubs $rs1, $rs2, $rd",
1219 [(set f32:$rd, (fsub f32:$rs1, f32:$rs2))],
1220 IIC_fpu_fast_instr>;
1221 def FSUBD : F3_3<2, 0b110100, 0b001000110,
1222 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1223 "fsubd $rs1, $rs2, $rd",
1224 [(set f64:$rd, (fsub f64:$rs1, f64:$rs2))],
1225 IIC_fpu_fast_instr>;
1226 def FSUBQ : F3_3<2, 0b110100, 0b001000111,
1227 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1228 "fsubq $rs1, $rs2, $rd",
1229 [(set f128:$rd, (fsub f128:$rs1, f128:$rs2))]>,
1230 Requires<[HasHardQuad]>;
1233 // Floating-point Multiply and Divide Instructions, p. 147
1234 def FMULS : F3_3<2, 0b110100, 0b001001001,
1235 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1236 "fmuls $rs1, $rs2, $rd",
1237 [(set f32:$rd, (fmul f32:$rs1, f32:$rs2))],
1238 IIC_fpu_muls>,
1239 Requires<[HasFMULS]>;
1240 def FMULD : F3_3<2, 0b110100, 0b001001010,
1241 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1242 "fmuld $rs1, $rs2, $rd",
1243 [(set f64:$rd, (fmul f64:$rs1, f64:$rs2))],
1244 IIC_fpu_muld>;
1245 def FMULQ : F3_3<2, 0b110100, 0b001001011,
1246 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1247 "fmulq $rs1, $rs2, $rd",
1248 [(set f128:$rd, (fmul f128:$rs1, f128:$rs2))]>,
1249 Requires<[HasHardQuad]>;
1251 def FSMULD : F3_3<2, 0b110100, 0b001101001,
1252 (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1253 "fsmuld $rs1, $rs2, $rd",
1254 [(set f64:$rd, (fmul (fpextend f32:$rs1),
1255 (fpextend f32:$rs2)))],
1256 IIC_fpu_muld>,
1257 Requires<[HasFSMULD]>;
1258 def FDMULQ : F3_3<2, 0b110100, 0b001101110,
1259 (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1260 "fdmulq $rs1, $rs2, $rd",
1261 [(set f128:$rd, (fmul (fpextend f64:$rs1),
1262 (fpextend f64:$rs2)))]>,
1263 Requires<[HasHardQuad]>;
1265 // FDIVS generates an erratum on LEON processors, so by disabling this instruction
1266 // this will be promoted to use FDIVD with doubles instead.
1267 def FDIVS : F3_3<2, 0b110100, 0b001001101,
1268 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1269 "fdivs $rs1, $rs2, $rd",
1270 [(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))],
1271 IIC_fpu_divs>;
1272 def FDIVD : F3_3<2, 0b110100, 0b001001110,
1273 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1274 "fdivd $rs1, $rs2, $rd",
1275 [(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))],
1276 IIC_fpu_divd>;
1277 def FDIVQ : F3_3<2, 0b110100, 0b001001111,
1278 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1279 "fdivq $rs1, $rs2, $rd",
1280 [(set f128:$rd, (fdiv f128:$rs1, f128:$rs2))]>,
1281 Requires<[HasHardQuad]>;
1283 // Floating-point Compare Instructions, p. 148
1284 // Note: the 2nd template arg is different for these guys.
1285 // Note 2: the result of a FCMP is not available until the 2nd cycle
1286 // after the instr is retired, but there is no interlock in Sparc V8.
1287 // This behavior is modeled with a forced noop after the instruction in
1288 // DelaySlotFiller.
1290 let Defs = [FCC0], rd = 0, isCodeGenOnly = 1 in {
1291 def FCMPS : F3_3c<2, 0b110101, 0b001010001,
1292 (outs), (ins FPRegs:$rs1, FPRegs:$rs2),
1293 "fcmps $rs1, $rs2",
1294 [(SPcmpfcc f32:$rs1, f32:$rs2)],
1295 IIC_fpu_fast_instr>;
1296 def FCMPD : F3_3c<2, 0b110101, 0b001010010,
1297 (outs), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1298 "fcmpd $rs1, $rs2",
1299 [(SPcmpfcc f64:$rs1, f64:$rs2)],
1300 IIC_fpu_fast_instr>;
1301 def FCMPQ : F3_3c<2, 0b110101, 0b001010011,
1302 (outs), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1303 "fcmpq $rs1, $rs2",
1304 [(SPcmpfcc f128:$rs1, f128:$rs2)]>,
1305 Requires<[HasHardQuad]>;
1306 }
1308 //===----------------------------------------------------------------------===//
1309 // Instructions for Thread Local Storage(TLS).
1310 //===----------------------------------------------------------------------===//
1311 let isAsmParserOnly = 1 in {
1312 def TLS_ADDrr : F3_1<2, 0b000000,
1313 (outs IntRegs:$rd),
1314 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym),
1315 "add $rs1, $rs2, $rd, $sym",
1316 [(set i32:$rd,
1317 (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>;
1319 let mayLoad = 1 in
1320 def TLS_LDrr : F3_1<3, 0b000000,
1321 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
1322 "ld [$addr], $dst, $sym",
1323 [(set i32:$dst,
1324 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;
1326 let Uses = [O6], isCall = 1, hasDelaySlot = 1 in
1327 def TLS_CALL : InstSP<(outs),
1328 (ins calltarget:$disp, TLSSym:$sym, variable_ops),
1329 "call $disp, $sym",
1330 [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)],
1331 IIC_jmp_or_call> {
1332 bits<30> disp;
1333 let op = 1;
1334 let Inst{29-0} = disp;
1335 }
1336 }
1338 //===----------------------------------------------------------------------===//
1339 // V9 Instructions
1340 //===----------------------------------------------------------------------===//
1342 // V9 Conditional Moves.
1343 let Predicates = [HasV9], Constraints = "$f = $rd" in {
1344 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
1345 let Uses = [ICC], intcc = 1, cc = 0b00 in {
1346 def MOVICCrr
1347 : F4_1<0b101100, (outs IntRegs:$rd),
1348 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1349 "mov$cond %icc, $rs2, $rd",
1350 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cond))]>;
1352 def MOVICCri
1353 : F4_2<0b101100, (outs IntRegs:$rd),
1354 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1355 "mov$cond %icc, $simm11, $rd",
1356 [(set i32:$rd,
1357 (SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>;
1358 }
1360 let Uses = [FCC0], intcc = 0, cc = 0b00 in {
1361 def MOVFCCrr
1362 : F4_1<0b101100, (outs IntRegs:$rd),
1363 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1364 "mov$cond %fcc0, $rs2, $rd",
1365 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cond))]>;
1366 def MOVFCCri
1367 : F4_2<0b101100, (outs IntRegs:$rd),
1368 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1369 "mov$cond %fcc0, $simm11, $rd",
1370 [(set i32:$rd,
1371 (SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>;
1372 }
1374 let Uses = [ICC], intcc = 1, opf_cc = 0b00 in {
1375 def FMOVS_ICC
1376 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
1377 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1378 "fmovs$cond %icc, $rs2, $rd",
1379 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cond))]>;
1380 def FMOVD_ICC
1381 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
1382 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1383 "fmovd$cond %icc, $rs2, $rd",
1384 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>;
1385 def FMOVQ_ICC
1386 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1387 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1388 "fmovq$cond %icc, $rs2, $rd",
1389 [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>,
1390 Requires<[HasHardQuad]>;
1391 }
1393 let Uses = [FCC0], intcc = 0, opf_cc = 0b00 in {
1394 def FMOVS_FCC
1395 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
1396 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1397 "fmovs$cond %fcc0, $rs2, $rd",
1398 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>;
1399 def FMOVD_FCC
1400 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
1401 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1402 "fmovd$cond %fcc0, $rs2, $rd",
1403 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>;
1404 def FMOVQ_FCC
1405 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1406 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1407 "fmovq$cond %fcc0, $rs2, $rd",
1408 [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>,
1409 Requires<[HasHardQuad]>;
1410 }
1412 }
1414 // Floating-Point Move Instructions, p. 164 of the V9 manual.
1415 let Predicates = [HasV9] in {
1416 def FMOVD : F3_3u<2, 0b110100, 0b000000010,
1417 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1418 "fmovd $rs2, $rd", []>;
1419 def FMOVQ : F3_3u<2, 0b110100, 0b000000011,
1420 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1421 "fmovq $rs2, $rd", []>,
1422 Requires<[HasHardQuad]>;
1423 def FNEGD : F3_3u<2, 0b110100, 0b000000110,
1424 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1425 "fnegd $rs2, $rd",
1426 [(set f64:$rd, (fneg f64:$rs2))]>;
1427 def FNEGQ : F3_3u<2, 0b110100, 0b000000111,
1428 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1429 "fnegq $rs2, $rd",
1430 [(set f128:$rd, (fneg f128:$rs2))]>,
1431 Requires<[HasHardQuad]>;
1432 def FABSD : F3_3u<2, 0b110100, 0b000001010,
1433 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1434 "fabsd $rs2, $rd",
1435 [(set f64:$rd, (fabs f64:$rs2))]>;
1436 def FABSQ : F3_3u<2, 0b110100, 0b000001011,
1437 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1438 "fabsq $rs2, $rd",
1439 [(set f128:$rd, (fabs f128:$rs2))]>,
1440 Requires<[HasHardQuad]>;
1441 }
1443 // Floating-point compare instruction with %fcc0-%fcc3.
1444 def V9FCMPS : F3_3c<2, 0b110101, 0b001010001,
1445 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1446 "fcmps $rd, $rs1, $rs2", []>;
1447 def V9FCMPD : F3_3c<2, 0b110101, 0b001010010,
1448 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1449 "fcmpd $rd, $rs1, $rs2", []>;
1450 def V9FCMPQ : F3_3c<2, 0b110101, 0b001010011,
1451 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1452 "fcmpq $rd, $rs1, $rs2", []>,
1453 Requires<[HasHardQuad]>;
1455 let hasSideEffects = 1 in {
1456 def V9FCMPES : F3_3c<2, 0b110101, 0b001010101,
1457 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1458 "fcmpes $rd, $rs1, $rs2", []>;
1459 def V9FCMPED : F3_3c<2, 0b110101, 0b001010110,
1460 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1461 "fcmped $rd, $rs1, $rs2", []>;
1462 def V9FCMPEQ : F3_3c<2, 0b110101, 0b001010111,
1463 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1464 "fcmpeq $rd, $rs1, $rs2", []>,
1465 Requires<[HasHardQuad]>;
1466 }
1468 // Floating point conditional move instrucitons with %fcc0-%fcc3.
1469 let Predicates = [HasV9] in {
1470 let Constraints = "$f = $rd", intcc = 0 in {
1471 def V9MOVFCCrr
1472 : F4_1<0b101100, (outs IntRegs:$rd),
1473 (ins FCCRegs:$cc, IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1474 "mov$cond $cc, $rs2, $rd", []>;
1475 def V9MOVFCCri
1476 : F4_2<0b101100, (outs IntRegs:$rd),
1477 (ins FCCRegs:$cc, i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1478 "mov$cond $cc, $simm11, $rd", []>;
1479 def V9FMOVS_FCC
1480 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
1481 (ins FCCRegs:$opf_cc, FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1482 "fmovs$cond $opf_cc, $rs2, $rd", []>;
1483 def V9FMOVD_FCC
1484 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
1485 (ins FCCRegs:$opf_cc, DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1486 "fmovd$cond $opf_cc, $rs2, $rd", []>;
1487 def V9FMOVQ_FCC
1488 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1489 (ins FCCRegs:$opf_cc, QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1490 "fmovq$cond $opf_cc, $rs2, $rd", []>,
1491 Requires<[HasHardQuad]>;
1492 } // Constraints = "$f = $rd", ...
1493 } // let Predicates = [hasV9]
1496 // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
1497 // the top 32-bits before using it. To do this clearing, we use a SRLri X,0.
1498 let rs1 = 0 in
1499 def POPCrr : F3_1<2, 0b101110,
1500 (outs IntRegs:$rd), (ins IntRegs:$rs2),
1501 "popc $rs2, $rd", []>, Requires<[HasV9]>;
1502 def : Pat<(ctpop i32:$src),
1503 (POPCrr (SRLri $src, 0))>;
1505 let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
1506 def MEMBARi : F3_2<2, 0b101000, (outs), (ins simm13Op:$simm13),
1507 "membar $simm13", []>;
1509 // The CAS instruction, unlike other instructions, only comes in a
1510 // form which requires an ASI be provided. The ASI value hardcoded
1511 // here is ASI_PRIMARY, the default unprivileged ASI for SparcV9.
1512 let Predicates = [HasV9], Constraints = "$swap = $rd", asi = 0b10000000 in
1513 def CASrr: F3_1_asi<3, 0b111100,
1514 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1515 IntRegs:$swap),
1516 "cas [$rs1], $rs2, $rd",
1517 [(set i32:$rd,
1518 (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>;
1521 // CASA is supported as an instruction on some LEON3 and all LEON4 processors.
1522 // This version can be automatically lowered from C code, selecting ASI 10
1523 let Predicates = [HasLeonCASA], Constraints = "$swap = $rd", asi = 0b00001010 in
1524 def CASAasi10: F3_1_asi<3, 0b111100,
1525 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1526 IntRegs:$swap),
1527 "casa [$rs1] 10, $rs2, $rd",
1528 [(set i32:$rd,
1529 (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>;
1531 // CASA supported on some LEON3 and all LEON4 processors. Same pattern as
1532 // CASrr, above, but with a different ASI. This version is supported for
1533 // inline assembly lowering only.
1534 let Predicates = [HasLeonCASA], Constraints = "$swap = $rd" in
1535 def CASArr: F3_1_asi<3, 0b111100,
1536 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1537 IntRegs:$swap, i8imm:$asi),
1538 "casa [$rs1] $asi, $rs2, $rd", []>;
1540 // TODO: Add DAG sequence to lower these instructions. Currently, only provided
1541 // as inline assembler-supported instructions.
1542 let Predicates = [HasUMAC_SMAC], Defs = [Y, ASR18], Uses = [Y, ASR18] in {
1543 def SMACrr : F3_1<2, 0b111111,
1544 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18),
1545 "smac $rs1, $rs2, $rd",
1546 [], IIC_smac_umac>;
1548 def SMACri : F3_2<2, 0b111111,
1549 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13, ASRRegs:$asr18),
1550 "smac $rs1, $simm13, $rd",
1551 [], IIC_smac_umac>;
1553 def UMACrr : F3_1<2, 0b111110,
1554 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18),
1555 "umac $rs1, $rs2, $rd",
1556 [], IIC_smac_umac>;
1558 def UMACri : F3_2<2, 0b111110,
1559 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13, ASRRegs:$asr18),
1560 "umac $rs1, $simm13, $rd",
1561 [], IIC_smac_umac>;
1562 }
1564 // The partial write WRPSR instruction has a non-zero destination
1565 // register value to separate it from the standard instruction.
1566 let Predicates = [HasPWRPSR], Defs = [PSR], rd=1 in {
1567 def PWRPSRrr : F3_1<2, 0b110001,
1568 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
1569 "pwr $rs1, $rs2, %psr", []>;
1570 def PWRPSRri : F3_2<2, 0b110001,
1571 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
1572 "pwr $rs1, $simm13, %psr", []>;
1573 }
1575 let Defs = [ICC] in {
1576 defm TADDCC : F3_12np<"taddcc", 0b100000>;
1577 defm TSUBCC : F3_12np<"tsubcc", 0b100001>;
1579 let hasSideEffects = 1 in {
1580 defm TADDCCTV : F3_12np<"taddcctv", 0b100010>;
1581 defm TSUBCCTV : F3_12np<"tsubcctv", 0b100011>;
1582 }
1583 }
1586 // Section A.43 - Read Privileged Register Instructions
1587 let Predicates = [HasV9] in {
1588 let rs2 = 0 in
1589 def RDPR : F3_1<2, 0b101010,
1590 (outs IntRegs:$rd), (ins PRRegs:$rs1),
1591 "rdpr $rs1, $rd", []>;
1592 }
1594 // Section A.62 - Write Privileged Register Instructions
1595 let Predicates = [HasV9] in {
1596 def WRPRrr : F3_1<2, 0b110010,
1597 (outs PRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
1598 "wrpr $rs1, $rs2, $rd", []>;
1599 def WRPRri : F3_2<2, 0b110010,
1600 (outs PRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
1601 "wrpr $rs1, $simm13, $rd", []>;
1602 }
1604 //===----------------------------------------------------------------------===//
1605 // Non-Instruction Patterns
1606 //===----------------------------------------------------------------------===//
1608 // Zero immediate.
1609 def : Pat<(i32 0),
1610 (ORrr (i32 G0), (i32 G0))>;
1611 // Small immediates.
1612 def : Pat<(i32 simm13:$val),
1613 (ORri (i32 G0), imm:$val)>;
1614 // Arbitrary immediates.
1615 def : Pat<(i32 imm:$val),
1616 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
1619 // Global addresses, constant pool entries
1620 let Predicates = [Is32Bit] in {
1622 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
1623 def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>;
1624 def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
1625 def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>;
1627 // GlobalTLS addresses
1628 def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>;
1629 def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i32 G0), tglobaltlsaddr:$in)>;
1630 def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
1631 (ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
1632 def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
1633 (XORri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
1635 // Blockaddress
1636 def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;
1637 def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>;
1639 // Add reg, lo. This is used when taking the addr of a global/constpool entry.
1640 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
1641 def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>;
1642 def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
1643 (ADDri $r, tblockaddress:$in)>;
1644 }
1646 // Calls:
1647 def : Pat<(call tglobaladdr:$dst),
1648 (CALL tglobaladdr:$dst)>;
1649 def : Pat<(call texternalsym:$dst),
1650 (CALL texternalsym:$dst)>;
1652 // Map integer extload's to zextloads.
1653 def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1654 def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1655 def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1656 def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1657 def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
1658 def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
1660 // zextload bool -> zextload byte
1661 def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1662 def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1664 // store 0, addr -> store %g0, addr
1665 def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>;
1666 def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;
1668 // store bar for all atomic_fence in V8.
1669 let Predicates = [HasNoV9] in
1670 def : Pat<(atomic_fence imm, imm), (STBAR)>;
1672 // atomic_load addr -> load addr
1673 def : Pat<(i32 (atomic_load_8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1674 def : Pat<(i32 (atomic_load_8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1675 def : Pat<(i32 (atomic_load_16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
1676 def : Pat<(i32 (atomic_load_16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
1677 def : Pat<(i32 (atomic_load_32 ADDRrr:$src)), (LDrr ADDRrr:$src)>;
1678 def : Pat<(i32 (atomic_load_32 ADDRri:$src)), (LDri ADDRri:$src)>;
1680 // atomic_store val, addr -> store val, addr
1681 def : Pat<(atomic_store_8 ADDRrr:$dst, i32:$val), (STBrr ADDRrr:$dst, $val)>;
1682 def : Pat<(atomic_store_8 ADDRri:$dst, i32:$val), (STBri ADDRri:$dst, $val)>;
1683 def : Pat<(atomic_store_16 ADDRrr:$dst, i32:$val), (STHrr ADDRrr:$dst, $val)>;
1684 def : Pat<(atomic_store_16 ADDRri:$dst, i32:$val), (STHri ADDRri:$dst, $val)>;
1685 def : Pat<(atomic_store_32 ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>;
1686 def : Pat<(atomic_store_32 ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>;
1688 // extract_vector
1689 def : Pat<(extractelt (v2i32 IntPair:$Rn), 0),
1690 (i32 (EXTRACT_SUBREG IntPair:$Rn, sub_even))>;
1691 def : Pat<(extractelt (v2i32 IntPair:$Rn), 1),
1692 (i32 (EXTRACT_SUBREG IntPair:$Rn, sub_odd))>;
1694 // build_vector
1695 def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)),
1696 (INSERT_SUBREG
1697 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), (i32 IntRegs:$a1), sub_even),
1698 (i32 IntRegs:$a2), sub_odd)>;
1701 include "SparcInstr64Bit.td"
1702 include "SparcInstrVIS.td"
1703 include "SparcInstrAliases.td"