[ARM] MVE predicate store patterns
[llvm-complete.git] / unittests / tools / llvm-exegesis / X86 / RegisterAliasingTest.cpp
blobb65b2a9315462f45239f298dfc07568e47b354d6
1 //===-- RegisterAliasingTest.cpp --------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
10 #include "RegisterAliasing.h"
12 #include <cassert>
13 #include <memory>
15 #include "X86InstrInfo.h"
16 #include "llvm/Support/TargetRegistry.h"
17 #include "llvm/Support/TargetSelect.h"
18 #include "gmock/gmock.h"
19 #include "gtest/gtest.h"
21 namespace llvm {
22 namespace exegesis {
23 namespace {
25 class RegisterAliasingTest : public ::testing::Test {
26 protected:
27 RegisterAliasingTest() {
28 const std::string TT = "x86_64-unknown-linux";
29 std::string error;
30 const llvm::Target *const TheTarget =
31 llvm::TargetRegistry::lookupTarget(TT, error);
32 if (!TheTarget) {
33 llvm::errs() << error << "\n";
34 return;
36 MCRegInfo.reset(TheTarget->createMCRegInfo(TT));
39 static void SetUpTestCase() {
40 LLVMInitializeX86TargetInfo();
41 LLVMInitializeX86Target();
42 LLVMInitializeX86TargetMC();
45 const llvm::MCRegisterInfo &getMCRegInfo() {
46 assert(MCRegInfo);
47 return *MCRegInfo;
50 private:
51 std::unique_ptr<const llvm::MCRegisterInfo> MCRegInfo;
54 TEST_F(RegisterAliasingTest, TrackSimpleRegister) {
55 const auto &RegInfo = getMCRegInfo();
56 const RegisterAliasingTracker tracker(RegInfo, llvm::X86::EAX);
57 std::set<llvm::MCPhysReg> ActualAliasedRegisters;
58 for (unsigned I : tracker.aliasedBits().set_bits())
59 ActualAliasedRegisters.insert(static_cast<llvm::MCPhysReg>(I));
60 const std::set<llvm::MCPhysReg> ExpectedAliasedRegisters = {
61 llvm::X86::AL, llvm::X86::AH, llvm::X86::AX,
62 llvm::X86::EAX, llvm::X86::HAX, llvm::X86::RAX};
63 ASSERT_THAT(ActualAliasedRegisters, ExpectedAliasedRegisters);
64 for (llvm::MCPhysReg aliased : ExpectedAliasedRegisters) {
65 ASSERT_THAT(tracker.getOrigin(aliased), llvm::X86::EAX);
69 TEST_F(RegisterAliasingTest, TrackRegisterClass) {
70 // The alias bits for GR8_ABCD_LRegClassID are the union of the alias bits for
71 // AL, BL, CL and DL.
72 const auto &RegInfo = getMCRegInfo();
73 const llvm::BitVector NoReservedReg(RegInfo.getNumRegs());
75 const RegisterAliasingTracker RegClassTracker(
76 RegInfo, NoReservedReg,
77 RegInfo.getRegClass(llvm::X86::GR8_ABCD_LRegClassID));
79 llvm::BitVector sum(RegInfo.getNumRegs());
80 sum |= RegisterAliasingTracker(RegInfo, llvm::X86::AL).aliasedBits();
81 sum |= RegisterAliasingTracker(RegInfo, llvm::X86::BL).aliasedBits();
82 sum |= RegisterAliasingTracker(RegInfo, llvm::X86::CL).aliasedBits();
83 sum |= RegisterAliasingTracker(RegInfo, llvm::X86::DL).aliasedBits();
85 ASSERT_THAT(RegClassTracker.aliasedBits(), sum);
88 TEST_F(RegisterAliasingTest, TrackRegisterClassCache) {
89 // Fetching twice the same tracker yields the same pointers.
90 const auto &RegInfo = getMCRegInfo();
91 const llvm::BitVector NoReservedReg(RegInfo.getNumRegs());
92 RegisterAliasingTrackerCache Cache(RegInfo, NoReservedReg);
93 ASSERT_THAT(&Cache.getRegister(llvm::X86::AX),
94 &Cache.getRegister(llvm::X86::AX));
96 ASSERT_THAT(&Cache.getRegisterClass(llvm::X86::GR8_ABCD_LRegClassID),
97 &Cache.getRegisterClass(llvm::X86::GR8_ABCD_LRegClassID));
100 } // namespace
101 } // namespace exegesis
102 } // namespace llvm