[ARM] MVE predicate store patterns
[llvm-complete.git] / unittests / tools / llvm-exegesis / X86 / SchedClassResolutionTest.cpp
blob9e745461142d40b7eb42229b866bccc9e000d966
1 //===-- SchedClassResolutionTest.cpp ----------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
9 #include "SchedClassResolution.h"
11 #include <cassert>
12 #include <memory>
14 #include "llvm/Support/TargetRegistry.h"
15 #include "llvm/Support/TargetSelect.h"
16 #include "gmock/gmock.h"
17 #include "gtest/gtest.h"
19 namespace llvm {
20 namespace exegesis {
21 namespace {
23 using testing::Pair;
24 using testing::UnorderedElementsAre;
26 class SchedClassResolutionTest : public ::testing::Test {
27 protected:
28 SchedClassResolutionTest() {
29 const std::string TT = "x86_64-unknown-linux";
30 std::string error;
31 const llvm::Target *const TheTarget =
32 llvm::TargetRegistry::lookupTarget(TT, error);
33 if (!TheTarget) {
34 llvm::errs() << error << "\n";
35 return;
37 STI.reset(TheTarget->createMCSubtargetInfo(TT, "haswell", ""));
39 // Compute the ProxResIdx of ports uses in tests.
40 const auto &SM = STI->getSchedModel();
41 for (unsigned I = 0, E = SM.getNumProcResourceKinds(); I < E; ++I) {
42 const std::string Name = SM.getProcResource(I)->Name;
43 if (Name == "HWPort0") {
44 P0Idx = I;
45 } else if (Name == "HWPort1") {
46 P1Idx = I;
47 } else if (Name == "HWPort5") {
48 P5Idx = I;
49 } else if (Name == "HWPort6") {
50 P6Idx = I;
51 } else if (Name == "HWPort05") {
52 P05Idx = I;
53 } else if (Name == "HWPort0156") {
54 P0156Idx = I;
57 EXPECT_NE(P0Idx, 0);
58 EXPECT_NE(P1Idx, 0);
59 EXPECT_NE(P5Idx, 0);
60 EXPECT_NE(P6Idx, 0);
61 EXPECT_NE(P05Idx, 0);
62 EXPECT_NE(P0156Idx, 0);
65 static void SetUpTestCase() {
66 LLVMInitializeX86TargetInfo();
67 LLVMInitializeX86Target();
68 LLVMInitializeX86TargetMC();
71 protected:
72 std::unique_ptr<const llvm::MCSubtargetInfo> STI;
73 uint16_t P0Idx = 0;
74 uint16_t P1Idx = 0;
75 uint16_t P5Idx = 0;
76 uint16_t P6Idx = 0;
77 uint16_t P05Idx = 0;
78 uint16_t P0156Idx = 0;
81 TEST_F(SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P0) {
82 const auto Pressure =
83 computeIdealizedProcResPressure(STI->getSchedModel(), {{P0Idx, 2}});
84 EXPECT_THAT(Pressure, UnorderedElementsAre(Pair(P0Idx, 2.0)));
87 TEST_F(SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P05) {
88 const auto Pressure =
89 computeIdealizedProcResPressure(STI->getSchedModel(), {{P05Idx, 2}});
90 EXPECT_THAT(Pressure,
91 UnorderedElementsAre(Pair(P0Idx, 1.0), Pair(P5Idx, 1.0)));
94 TEST_F(SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P05_2P0156) {
95 const auto Pressure = computeIdealizedProcResPressure(
96 STI->getSchedModel(), {{P05Idx, 2}, {P0156Idx, 2}});
97 EXPECT_THAT(Pressure,
98 UnorderedElementsAre(Pair(P0Idx, 1.0), Pair(P1Idx, 1.0),
99 Pair(P5Idx, 1.0), Pair(P6Idx, 1.0)));
102 TEST_F(SchedClassResolutionTest,
103 ComputeIdealizedProcResPressure_1P1_1P05_2P0156) {
104 const auto Pressure = computeIdealizedProcResPressure(
105 STI->getSchedModel(), {{P1Idx, 1}, {P05Idx, 1}, {P0156Idx, 2}});
106 EXPECT_THAT(Pressure,
107 UnorderedElementsAre(Pair(P0Idx, 1.0), Pair(P1Idx, 1.0),
108 Pair(P5Idx, 1.0), Pair(P6Idx, 1.0)));
111 } // namespace
112 } // namespace exegesis
113 } // namespace llvm