utils/TableGen/CodeEmitterGen.cpp

   1 //===- CodeEmitterGen.cpp - Code Emitter Generator ------------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // CodeEmitterGen uses the descriptions of instructions and their fields to
  10 // construct an automated code emitter: a function that, given a MachineInstr,
  11 // returns the (currently, 32-bit unsigned) value of the instruction.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "CodeGenInstruction.h"
  16 #include "CodeGenTarget.h"
  17 #include "SubtargetFeatureInfo.h"
  18 #include "Types.h"
  19 #include "llvm/ADT/ArrayRef.h"
  20 #include "llvm/ADT/StringExtras.h"
  21 #include "llvm/Support/Casting.h"
  22 #include "llvm/Support/raw_ostream.h"
  23 #include "llvm/TableGen/Record.h"
  24 #include "llvm/TableGen/TableGenBackend.h"
  25 #include <cassert>
  26 #include <cstdint>
  27 #include <map>
  28 #include <set>
  29 #include <string>
  30 #include <utility>
  31 #include <vector>
  32
  33 using namespace llvm;
  34
  35 namespace {
  36
  37 class CodeEmitterGen {
  38   RecordKeeper &Records;
  39
  40 public:
  41   CodeEmitterGen(RecordKeeper &R) : Records(R) {}
  42
  43   void run(raw_ostream &o);
  44
  45 private:
  46   int getVariableBit(const std::string &VarName, BitsInit *BI, int bit);
  47   std::string getInstructionCase(Record *R, CodeGenTarget &Target);
  48   void AddCodeToMergeInOperand(Record *R, BitsInit *BI,
  49                                const std::string &VarName,
  50                                unsigned &NumberedOp,
  51                                std::set<unsigned> &NamedOpIndices,
  52                                std::string &Case, CodeGenTarget &Target);
  53
  54 };
  55
  56 // If the VarBitInit at position 'bit' matches the specified variable then
  57 // return the variable bit position.  Otherwise return -1.
  58 int CodeEmitterGen::getVariableBit(const std::string &VarName,
  59                                    BitsInit *BI, int bit) {
  60   if (VarBitInit *VBI = dyn_cast<VarBitInit>(BI->getBit(bit))) {
  61     if (VarInit *VI = dyn_cast<VarInit>(VBI->getBitVar()))
  62       if (VI->getName() == VarName)
  63         return VBI->getBitNum();
  64   } else if (VarInit *VI = dyn_cast<VarInit>(BI->getBit(bit))) {
  65     if (VI->getName() == VarName)
  66       return 0;
  67   }
  68
  69   return -1;
  70 }
  71
  72 void CodeEmitterGen::
  73 AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName,
  74                         unsigned &NumberedOp,
  75                         std::set<unsigned> &NamedOpIndices,
  76                         std::string &Case, CodeGenTarget &Target) {
  77   CodeGenInstruction &CGI = Target.getInstruction(R);
  78
  79   // Determine if VarName actually contributes to the Inst encoding.
  80   int bit = BI->getNumBits()-1;
  81
  82   // Scan for a bit that this contributed to.
  83   for (; bit >= 0; ) {
  84     if (getVariableBit(VarName, BI, bit) != -1)
  85       break;
  86
  87     --bit;
  88   }
  89
  90   // If we found no bits, ignore this value, otherwise emit the call to get the
  91   // operand encoding.
  92   if (bit < 0) return;
  93
  94   // If the operand matches by name, reference according to that
  95   // operand number. Non-matching operands are assumed to be in
  96   // order.
  97   unsigned OpIdx;
  98   if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) {
  99     // Get the machine operand number for the indicated operand.
 100     OpIdx = CGI.Operands[OpIdx].MIOperandNo;
 101     assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) &&
 102            "Explicitly used operand also marked as not emitted!");
 103   } else {
 104     unsigned NumberOps = CGI.Operands.size();
 105     /// If this operand is not supposed to be emitted by the
 106     /// generated emitter, skip it.
 107     while (NumberedOp < NumberOps &&
 108            (CGI.Operands.isFlatOperandNotEmitted(NumberedOp) ||
 109               (!NamedOpIndices.empty() && NamedOpIndices.count(
 110                 CGI.Operands.getSubOperandNumber(NumberedOp).first)))) {
 111       ++NumberedOp;
 112
 113       if (NumberedOp >= CGI.Operands.back().MIOperandNo +
 114                         CGI.Operands.back().MINumOperands) {
 115         errs() << "Too few operands in record " << R->getName() <<
 116                   " (no match for variable " << VarName << "):\n";
 117         errs() << *R;
 118         errs() << '\n';
 119
 120         return;
 121       }
 122     }
 123
 124     OpIdx = NumberedOp++;
 125   }
 126
 127   std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx);
 128   std::string &EncoderMethodName = CGI.Operands[SO.first].EncoderMethodName;
 129
 130   // If the source operand has a custom encoder, use it. This will
 131   // get the encoding for all of the suboperands.
 132   if (!EncoderMethodName.empty()) {
 133     // A custom encoder has all of the information for the
 134     // sub-operands, if there are more than one, so only
 135     // query the encoder once per source operand.
 136     if (SO.second == 0) {
 137       Case += "      // op: " + VarName + "\n" +
 138               "      op = " + EncoderMethodName + "(MI, " + utostr(OpIdx);
 139       Case += ", Fixups, STI";
 140       Case += ");\n";
 141     }
 142   } else {
 143     Case += "      // op: " + VarName + "\n" +
 144       "      op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")";
 145     Case += ", Fixups, STI";
 146     Case += ");\n";
 147   }
 148
 149   for (; bit >= 0; ) {
 150     int varBit = getVariableBit(VarName, BI, bit);
 151
 152     // If this bit isn't from a variable, skip it.
 153     if (varBit == -1) {
 154       --bit;
 155       continue;
 156     }
 157
 158     // Figure out the consecutive range of bits covered by this operand, in
 159     // order to generate better encoding code.
 160     int beginInstBit = bit;
 161     int beginVarBit = varBit;
 162     int N = 1;
 163     for (--bit; bit >= 0;) {
 164       varBit = getVariableBit(VarName, BI, bit);
 165       if (varBit == -1 || varBit != (beginVarBit - N)) break;
 166       ++N;
 167       --bit;
 168     }
 169
 170     uint64_t opMask = ~(uint64_t)0 >> (64-N);
 171     int opShift = beginVarBit - N + 1;
 172     opMask <<= opShift;
 173     opShift = beginInstBit - beginVarBit;
 174
 175     if (opShift > 0) {
 176       Case += "      Value |= (op & UINT64_C(" + utostr(opMask) + ")) << " +
 177               itostr(opShift) + ";\n";
 178     } else if (opShift < 0) {
 179       Case += "      Value |= (op & UINT64_C(" + utostr(opMask) + ")) >> " +
 180               itostr(-opShift) + ";\n";
 181     } else {
 182       Case += "      Value |= op & UINT64_C(" + utostr(opMask) + ");\n";
 183     }
 184   }
 185 }
 186
 187 std::string CodeEmitterGen::getInstructionCase(Record *R,
 188                                                CodeGenTarget &Target) {
 189   std::string Case;
 190   BitsInit *BI = R->getValueAsBitsInit("Inst");
 191   unsigned NumberedOp = 0;
 192   std::set<unsigned> NamedOpIndices;
 193
 194   // Collect the set of operand indices that might correspond to named
 195   // operand, and skip these when assigning operands based on position.
 196   if (Target.getInstructionSet()->
 197        getValueAsBit("noNamedPositionallyEncodedOperands")) {
 198     CodeGenInstruction &CGI = Target.getInstruction(R);
 199     for (const RecordVal &RV : R->getValues()) {
 200       unsigned OpIdx;
 201       if (!CGI.Operands.hasOperandNamed(RV.getName(), OpIdx))
 202         continue;
 203
 204       NamedOpIndices.insert(OpIdx);
 205     }
 206   }
 207
 208   // Loop over all of the fields in the instruction, determining which are the
 209   // operands to the instruction.
 210   for (const RecordVal &RV : R->getValues()) {
 211     // Ignore fixed fields in the record, we're looking for values like:
 212     //    bits<5> RST = { ?, ?, ?, ?, ? };
 213     if (RV.getPrefix() || RV.getValue()->isComplete())
 214       continue;
 215
 216     AddCodeToMergeInOperand(R, BI, RV.getName(), NumberedOp,
 217                             NamedOpIndices, Case, Target);
 218   }
 219
 220   StringRef PostEmitter = R->getValueAsString("PostEncoderMethod");
 221   if (!PostEmitter.empty()) {
 222     Case += "      Value = ";
 223     Case += PostEmitter;
 224     Case += "(MI, Value";
 225     Case += ", STI";
 226     Case += ");\n";
 227   }
 228
 229   return Case;
 230 }
 231
 232 static std::string
 233 getNameForFeatureBitset(const std::vector<Record *> &FeatureBitset) {
 234   std::string Name = "CEFBS";
 235   for (const auto &Feature : FeatureBitset)
 236     Name += ("_" + Feature->getName()).str();
 237   return Name;
 238 }
 239
 240 void CodeEmitterGen::run(raw_ostream &o) {
 241   CodeGenTarget Target(Records);
 242   std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
 243
 244   // For little-endian instruction bit encodings, reverse the bit order
 245   Target.reverseBitsForLittleEndianEncoding();
 246
 247   ArrayRef<const CodeGenInstruction*> NumberedInstructions =
 248     Target.getInstructionsByEnumValue();
 249
 250   // Emit function declaration
 251   o << "uint64_t " << Target.getName();
 252   o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n"
 253     << "    SmallVectorImpl<MCFixup> &Fixups,\n"
 254     << "    const MCSubtargetInfo &STI) const {\n";
 255
 256   // Emit instruction base values
 257   o << "  static const uint64_t InstBits[] = {\n";
 258   for (const CodeGenInstruction *CGI : NumberedInstructions) {
 259     Record *R = CGI->TheDef;
 260
 261     if (R->getValueAsString("Namespace") == "TargetOpcode" ||
 262         R->getValueAsBit("isPseudo")) {
 263       o << "    UINT64_C(0),\n";
 264       continue;
 265     }
 266
 267     BitsInit *BI = R->getValueAsBitsInit("Inst");
 268
 269     // Start by filling in fixed values.
 270     uint64_t Value = 0;
 271     for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
 272       if (BitInit *B = dyn_cast<BitInit>(BI->getBit(e-i-1)))
 273         Value |= (uint64_t)B->getValue() << (e-i-1);
 274     }
 275     o << "    UINT64_C(" << Value << ")," << '\t' << "// " << R->getName() << "\n";
 276   }
 277   o << "    UINT64_C(0)\n  };\n";
 278
 279   // Map to accumulate all the cases.
 280   std::map<std::string, std::vector<std::string>> CaseMap;
 281
 282   // Construct all cases statement for each opcode
 283   for (std::vector<Record*>::iterator IC = Insts.begin(), EC = Insts.end();
 284         IC != EC; ++IC) {
 285     Record *R = *IC;
 286     if (R->getValueAsString("Namespace") == "TargetOpcode" ||
 287         R->getValueAsBit("isPseudo"))
 288       continue;
 289     std::string InstName =
 290         (R->getValueAsString("Namespace") + "::" + R->getName()).str();
 291     std::string Case = getInstructionCase(R, Target);
 292
 293     CaseMap[Case].push_back(std::move(InstName));
 294   }
 295
 296   // Emit initial function code
 297   o << "  const unsigned opcode = MI.getOpcode();\n"
 298     << "  uint64_t Value = InstBits[opcode];\n"
 299     << "  uint64_t op = 0;\n"
 300     << "  (void)op;  // suppress warning\n"
 301     << "  switch (opcode) {\n";
 302
 303   // Emit each case statement
 304   std::map<std::string, std::vector<std::string>>::iterator IE, EE;
 305   for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) {
 306     const std::string &Case = IE->first;
 307     std::vector<std::string> &InstList = IE->second;
 308
 309     for (int i = 0, N = InstList.size(); i < N; i++) {
 310       if (i) o << "\n";
 311       o << "    case " << InstList[i]  << ":";
 312     }
 313     o << " {\n";
 314     o << Case;
 315     o << "      break;\n"
 316       << "    }\n";
 317   }
 318
 319   // Default case: unhandled opcode
 320   o << "  default:\n"
 321     << "    std::string msg;\n"
 322     << "    raw_string_ostream Msg(msg);\n"
 323     << "    Msg << \"Not supported instr: \" << MI;\n"
 324     << "    report_fatal_error(Msg.str());\n"
 325     << "  }\n"
 326     << "  return Value;\n"
 327     << "}\n\n";
 328
 329   const auto &All = SubtargetFeatureInfo::getAll(Records);
 330   std::map<Record *, SubtargetFeatureInfo, LessRecordByID> SubtargetFeatures;
 331   SubtargetFeatures.insert(All.begin(), All.end());
 332
 333   o << "#ifdef ENABLE_INSTR_PREDICATE_VERIFIER\n"
 334     << "#undef ENABLE_INSTR_PREDICATE_VERIFIER\n"
 335     << "#include <sstream>\n\n";
 336
 337   // Emit the subtarget feature enumeration.
 338   SubtargetFeatureInfo::emitSubtargetFeatureBitEnumeration(SubtargetFeatures,
 339                                                            o);
 340
 341   // Emit the name table for error messages.
 342   o << "#ifndef NDEBUG\n";
 343   SubtargetFeatureInfo::emitNameTable(SubtargetFeatures, o);
 344   o << "#endif // NDEBUG\n";
 345
 346   // Emit the available features compute function.
 347   SubtargetFeatureInfo::emitComputeAssemblerAvailableFeatures(
 348       Target.getName(), "MCCodeEmitter", "computeAvailableFeatures",
 349       SubtargetFeatures, o);
 350
 351   std::vector<std::vector<Record *>> FeatureBitsets;
 352   for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
 353     FeatureBitsets.emplace_back();
 354     for (Record *Predicate : Inst->TheDef->getValueAsListOfDefs("Predicates")) {
 355       const auto &I = SubtargetFeatures.find(Predicate);
 356       if (I != SubtargetFeatures.end())
 357         FeatureBitsets.back().push_back(I->second.TheDef);
 358     }
 359   }
 360
 361   llvm::sort(FeatureBitsets, [&](const std::vector<Record *> &A,
 362                                  const std::vector<Record *> &B) {
 363     if (A.size() < B.size())
 364       return true;
 365     if (A.size() > B.size())
 366       return false;
 367     for (const auto &Pair : zip(A, B)) {
 368       if (std::get<0>(Pair)->getName() < std::get<1>(Pair)->getName())
 369         return true;
 370       if (std::get<0>(Pair)->getName() > std::get<1>(Pair)->getName())
 371         return false;
 372     }
 373     return false;
 374   });
 375   FeatureBitsets.erase(
 376       std::unique(FeatureBitsets.begin(), FeatureBitsets.end()),
 377       FeatureBitsets.end());
 378   o << "#ifndef NDEBUG\n"
 379     << "// Feature bitsets.\n"
 380     << "enum : " << getMinimalTypeForRange(FeatureBitsets.size()) << " {\n"
 381     << "  CEFBS_None,\n";
 382   for (const auto &FeatureBitset : FeatureBitsets) {
 383     if (FeatureBitset.empty())
 384       continue;
 385     o << "  " << getNameForFeatureBitset(FeatureBitset) << ",\n";
 386   }
 387   o << "};\n\n"
 388      << "const static FeatureBitset FeatureBitsets[] {\n"
 389      << "  {}, // CEFBS_None\n";
 390   for (const auto &FeatureBitset : FeatureBitsets) {
 391     if (FeatureBitset.empty())
 392       continue;
 393     o << "  {";
 394     for (const auto &Feature : FeatureBitset) {
 395       const auto &I = SubtargetFeatures.find(Feature);
 396       assert(I != SubtargetFeatures.end() && "Didn't import predicate?");
 397       o << I->second.getEnumBitName() << ", ";
 398     }
 399     o << "},\n";
 400   }
 401   o << "};\n"
 402     << "#endif // NDEBUG\n\n";
 403
 404
 405   // Emit the predicate verifier.
 406   o << "void " << Target.getName()
 407     << "MCCodeEmitter::verifyInstructionPredicates(\n"
 408     << "    const MCInst &Inst, const FeatureBitset &AvailableFeatures) const {\n"
 409     << "#ifndef NDEBUG\n"
 410     << "  static " << getMinimalTypeForRange(FeatureBitsets.size())
 411     << " RequiredFeaturesRefs[] = {\n";
 412   unsigned InstIdx = 0;
 413   for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
 414     o << "    CEFBS";
 415     unsigned NumPredicates = 0;
 416     for (Record *Predicate : Inst->TheDef->getValueAsListOfDefs("Predicates")) {
 417       const auto &I = SubtargetFeatures.find(Predicate);
 418       if (I != SubtargetFeatures.end()) {
 419         o << '_' << I->second.TheDef->getName();
 420         NumPredicates++;
 421       }
 422     }
 423     if (!NumPredicates)
 424       o << "_None";
 425     o << ", // " << Inst->TheDef->getName() << " = " << InstIdx << "\n";
 426     InstIdx++;
 427   }
 428   o << "  };\n\n";
 429   o << "  assert(Inst.getOpcode() < " << InstIdx << ");\n";
 430   o << "  const FeatureBitset &RequiredFeatures = "
 431        "FeatureBitsets[RequiredFeaturesRefs[Inst.getOpcode()]];\n";
 432   o << "  FeatureBitset MissingFeatures =\n"
 433     << "      (AvailableFeatures & RequiredFeatures) ^\n"
 434     << "      RequiredFeatures;\n"
 435     << "  if (MissingFeatures.any()) {\n"
 436     << "    std::ostringstream Msg;\n"
 437     << "    Msg << \"Attempting to emit \" << "
 438        "MCII.getName(Inst.getOpcode()).str()\n"
 439     << "        << \" instruction but the \";\n"
 440     << "    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)\n"
 441     << "      if (MissingFeatures.test(i))\n"
 442     << "        Msg << SubtargetFeatureNames[i] << \" \";\n"
 443     << "    Msg << \"predicate(s) are not met\";\n"
 444     << "    report_fatal_error(Msg.str());\n"
 445     << "  }\n"
 446     << "#else\n"
 447     << "// Silence unused variable warning on targets that don't use MCII for "
 448        "other purposes (e.g. BPF).\n"
 449     << "(void)MCII;\n"
 450     << "#endif // NDEBUG\n";
 451   o << "}\n";
 452   o << "#endif\n";
 453 }
 454
 455 } // end anonymous namespace
 456
 457 namespace llvm {
 458
 459 void EmitCodeEmitter(RecordKeeper &RK, raw_ostream &OS) {
 460   emitSourceFileHeader("Machine Code Emitter", OS);
 461   CodeEmitterGen(RK).run(OS);
 462 }
 463
 464 } // end namespace llvm