utils/TableGen/X86EVEX2VEXTablesEmitter.cpp

   1 //===- utils/TableGen/X86EVEX2VEXTablesEmitter.cpp - X86 backend-*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 ///
   9 /// This tablegen backend is responsible for emitting the X86 backend EVEX2VEX
  10 /// compression tables.
  11 ///
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "CodeGenTarget.h"
  15 #include "llvm/TableGen/Error.h"
  16 #include "llvm/TableGen/TableGenBackend.h"
  17
  18 using namespace llvm;
  19
  20 namespace {
  21
  22 class X86EVEX2VEXTablesEmitter {
  23   RecordKeeper &Records;
  24   CodeGenTarget Target;
  25
  26   // Hold all non-masked & non-broadcasted EVEX encoded instructions
  27   std::vector<const CodeGenInstruction *> EVEXInsts;
  28   // Hold all VEX encoded instructions. Divided into groups with same opcodes
  29   // to make the search more efficient
  30   std::map<uint64_t, std::vector<const CodeGenInstruction *>> VEXInsts;
  31
  32   typedef std::pair<const CodeGenInstruction *, const CodeGenInstruction *> Entry;
  33
  34   // Represent both compress tables
  35   std::vector<Entry> EVEX2VEX128;
  36   std::vector<Entry> EVEX2VEX256;
  37
  38 public:
  39   X86EVEX2VEXTablesEmitter(RecordKeeper &R) : Records(R), Target(R) {}
  40
  41   // run - Output X86 EVEX2VEX tables.
  42   void run(raw_ostream &OS);
  43
  44 private:
  45   // Prints the given table as a C++ array of type
  46   // X86EvexToVexCompressTableEntry
  47   void printTable(const std::vector<Entry> &Table, raw_ostream &OS);
  48 };
  49
  50 void X86EVEX2VEXTablesEmitter::printTable(const std::vector<Entry> &Table,
  51                                           raw_ostream &OS) {
  52   StringRef Size = (Table == EVEX2VEX128) ? "128" : "256";
  53
  54   OS << "// X86 EVEX encoded instructions that have a VEX " << Size
  55      << " encoding\n"
  56      << "// (table format: <EVEX opcode, VEX-" << Size << " opcode>).\n"
  57      << "static const X86EvexToVexCompressTableEntry X86EvexToVex" << Size
  58      << "CompressTable[] = {\n"
  59      << "  // EVEX scalar with corresponding VEX.\n";
  60
  61   // Print all entries added to the table
  62   for (auto Pair : Table) {
  63     OS << "  { X86::" << Pair.first->TheDef->getName()
  64        << ", X86::" << Pair.second->TheDef->getName() << " },\n";
  65   }
  66
  67   OS << "};\n\n";
  68 }
  69
  70 // Return true if the 2 BitsInits are equal
  71 // Calculates the integer value residing BitsInit object
  72 static inline uint64_t getValueFromBitsInit(const BitsInit *B) {
  73   uint64_t Value = 0;
  74   for (unsigned i = 0, e = B->getNumBits(); i != e; ++i) {
  75     if (BitInit *Bit = dyn_cast<BitInit>(B->getBit(i)))
  76       Value |= uint64_t(Bit->getValue()) << i;
  77     else
  78       PrintFatalError("Invalid VectSize bit");
  79   }
  80   return Value;
  81 }
  82
  83 // Function object - Operator() returns true if the given VEX instruction
  84 // matches the EVEX instruction of this object.
  85 class IsMatch {
  86   const CodeGenInstruction *EVEXInst;
  87
  88 public:
  89   IsMatch(const CodeGenInstruction *EVEXInst) : EVEXInst(EVEXInst) {}
  90
  91   bool operator()(const CodeGenInstruction *VEXInst) {
  92     Record *RecE = EVEXInst->TheDef;
  93     Record *RecV = VEXInst->TheDef;
  94     bool EVEX_W = RecE->getValueAsBit("HasVEX_W");
  95     bool VEX_W  = RecV->getValueAsBit("HasVEX_W");
  96     bool VEX_WIG  = RecV->getValueAsBit("IgnoresVEX_W");
  97     bool EVEX_WIG = RecE->getValueAsBit("IgnoresVEX_W");
  98     bool EVEX_W1_VEX_W0 = RecE->getValueAsBit("EVEX_W1_VEX_W0");
  99
 100     if (RecV->getValueAsDef("OpEnc")->getName().str() != "EncVEX" ||
 101         // VEX/EVEX fields
 102         RecV->getValueAsDef("OpPrefix") != RecE->getValueAsDef("OpPrefix") ||
 103         RecV->getValueAsDef("OpMap") != RecE->getValueAsDef("OpMap") ||
 104         RecV->getValueAsBit("hasVEX_4V") != RecE->getValueAsBit("hasVEX_4V") ||
 105         RecV->getValueAsBit("hasEVEX_L2") != RecE->getValueAsBit("hasEVEX_L2") ||
 106         RecV->getValueAsBit("hasVEX_L") != RecE->getValueAsBit("hasVEX_L") ||
 107         // Match is allowed if either is VEX_WIG, or they match, or EVEX
 108         // is VEX_W1X and VEX is VEX_W0.
 109         (!(VEX_WIG || (!EVEX_WIG && EVEX_W == VEX_W) ||
 110            (EVEX_W1_VEX_W0 && EVEX_W && !VEX_W))) ||
 111         // Instruction's format
 112         RecV->getValueAsDef("Form") != RecE->getValueAsDef("Form"))
 113       return false;
 114
 115     // This is needed for instructions with intrinsic version (_Int).
 116     // Where the only difference is the size of the operands.
 117     // For example: VUCOMISDZrm and Int_VUCOMISDrm
 118     // Also for instructions that their EVEX version was upgraded to work with
 119     // k-registers. For example VPCMPEQBrm (xmm output register) and
 120     // VPCMPEQBZ128rm (k register output register).
 121     for (unsigned i = 0, e = EVEXInst->Operands.size(); i < e; i++) {
 122       Record *OpRec1 = EVEXInst->Operands[i].Rec;
 123       Record *OpRec2 = VEXInst->Operands[i].Rec;
 124
 125       if (OpRec1 == OpRec2)
 126         continue;
 127
 128       if (isRegisterOperand(OpRec1) && isRegisterOperand(OpRec2)) {
 129         if (getRegOperandSize(OpRec1) != getRegOperandSize(OpRec2))
 130           return false;
 131       } else if (isMemoryOperand(OpRec1) && isMemoryOperand(OpRec2)) {
 132         return false;
 133       } else if (isImmediateOperand(OpRec1) && isImmediateOperand(OpRec2)) {
 134         if (OpRec1->getValueAsDef("Type") != OpRec2->getValueAsDef("Type")) {
 135           return false;
 136         }
 137       } else
 138         return false;
 139     }
 140
 141     return true;
 142   }
 143
 144 private:
 145   static inline bool isRegisterOperand(const Record *Rec) {
 146     return Rec->isSubClassOf("RegisterClass") ||
 147            Rec->isSubClassOf("RegisterOperand");
 148   }
 149
 150   static inline bool isMemoryOperand(const Record *Rec) {
 151     return Rec->isSubClassOf("Operand") &&
 152            Rec->getValueAsString("OperandType") == "OPERAND_MEMORY";
 153   }
 154
 155   static inline bool isImmediateOperand(const Record *Rec) {
 156     return Rec->isSubClassOf("Operand") &&
 157            Rec->getValueAsString("OperandType") == "OPERAND_IMMEDIATE";
 158   }
 159
 160   static inline unsigned int getRegOperandSize(const Record *RegRec) {
 161     if (RegRec->isSubClassOf("RegisterClass"))
 162       return RegRec->getValueAsInt("Alignment");
 163     if (RegRec->isSubClassOf("RegisterOperand"))
 164       return RegRec->getValueAsDef("RegClass")->getValueAsInt("Alignment");
 165
 166     llvm_unreachable("Register operand's size not known!");
 167   }
 168 };
 169
 170 void X86EVEX2VEXTablesEmitter::run(raw_ostream &OS) {
 171   emitSourceFileHeader("X86 EVEX2VEX tables", OS);
 172
 173   ArrayRef<const CodeGenInstruction *> NumberedInstructions =
 174       Target.getInstructionsByEnumValue();
 175
 176   for (const CodeGenInstruction *Inst : NumberedInstructions) {
 177     // Filter non-X86 instructions.
 178     if (!Inst->TheDef->isSubClassOf("X86Inst"))
 179       continue;
 180
 181     // Add VEX encoded instructions to one of VEXInsts vectors according to
 182     // it's opcode.
 183     if (Inst->TheDef->getValueAsDef("OpEnc")->getName() == "EncVEX") {
 184       uint64_t Opcode = getValueFromBitsInit(Inst->TheDef->
 185                                              getValueAsBitsInit("Opcode"));
 186       VEXInsts[Opcode].push_back(Inst);
 187     }
 188     // Add relevant EVEX encoded instructions to EVEXInsts
 189     else if (Inst->TheDef->getValueAsDef("OpEnc")->getName() == "EncEVEX" &&
 190              !Inst->TheDef->getValueAsBit("hasEVEX_K") &&
 191              !Inst->TheDef->getValueAsBit("hasEVEX_B") &&
 192              !Inst->TheDef->getValueAsBit("hasEVEX_L2") &&
 193              !Inst->TheDef->getValueAsBit("notEVEX2VEXConvertible"))
 194       EVEXInsts.push_back(Inst);
 195   }
 196
 197   for (const CodeGenInstruction *EVEXInst : EVEXInsts) {
 198     uint64_t Opcode = getValueFromBitsInit(EVEXInst->TheDef->
 199                                            getValueAsBitsInit("Opcode"));
 200     // For each EVEX instruction look for a VEX match in the appropriate vector
 201     // (instructions with the same opcode) using function object IsMatch.
 202     // Allow EVEX2VEXOverride to explicitly specify a match.
 203     const CodeGenInstruction *VEXInst = nullptr;
 204     if (!EVEXInst->TheDef->isValueUnset("EVEX2VEXOverride")) {
 205       StringRef AltInstStr =
 206         EVEXInst->TheDef->getValueAsString("EVEX2VEXOverride");
 207       Record *AltInstRec = Records.getDef(AltInstStr);
 208       assert(AltInstRec && "EVEX2VEXOverride instruction not found!");
 209       VEXInst = &Target.getInstruction(AltInstRec);
 210     } else {
 211       auto Match = llvm::find_if(VEXInsts[Opcode], IsMatch(EVEXInst));
 212       if (Match != VEXInsts[Opcode].end())
 213         VEXInst = *Match;
 214     }
 215
 216     if (!VEXInst)
 217       continue;
 218
 219     // In case a match is found add new entry to the appropriate table
 220     if (EVEXInst->TheDef->getValueAsBit("hasVEX_L"))
 221       EVEX2VEX256.push_back(std::make_pair(EVEXInst, VEXInst)); // {0,1}
 222     else
 223       EVEX2VEX128.push_back(std::make_pair(EVEXInst, VEXInst)); // {0,0}
 224   }
 225
 226   // Print both tables
 227   printTable(EVEX2VEX128, OS);
 228   printTable(EVEX2VEX256, OS);
 229 }
 230 }
 231
 232 namespace llvm {
 233 void EmitX86EVEX2VEXTables(RecordKeeper &RK, raw_ostream &OS) {
 234   X86EVEX2VEXTablesEmitter(RK).run(OS);
 235 }
 236 }