lib/Target/AArch64/AArch64CallLowering.cpp

   1 //===--- AArch64CallLowering.cpp - Call lowering --------------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 ///
   9 /// \file
  10 /// This file implements the lowering of LLVM calls to machine code calls for
  11 /// GlobalISel.
  12 ///
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "AArch64CallLowering.h"
  16 #include "AArch64ISelLowering.h"
  17 #include "AArch64MachineFunctionInfo.h"
  18 #include "AArch64Subtarget.h"
  19 #include "llvm/ADT/ArrayRef.h"
  20 #include "llvm/ADT/SmallVector.h"
  21 #include "llvm/CodeGen/Analysis.h"
  22 #include "llvm/CodeGen/CallingConvLower.h"
  23 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
  24 #include "llvm/CodeGen/GlobalISel/Utils.h"
  25 #include "llvm/CodeGen/LowLevelType.h"
  26 #include "llvm/CodeGen/MachineBasicBlock.h"
  27 #include "llvm/CodeGen/MachineFrameInfo.h"
  28 #include "llvm/CodeGen/MachineFunction.h"
  29 #include "llvm/CodeGen/MachineInstrBuilder.h"
  30 #include "llvm/CodeGen/MachineMemOperand.h"
  31 #include "llvm/CodeGen/MachineOperand.h"
  32 #include "llvm/CodeGen/MachineRegisterInfo.h"
  33 #include "llvm/CodeGen/TargetRegisterInfo.h"
  34 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  35 #include "llvm/CodeGen/ValueTypes.h"
  36 #include "llvm/IR/Argument.h"
  37 #include "llvm/IR/Attributes.h"
  38 #include "llvm/IR/Function.h"
  39 #include "llvm/IR/Type.h"
  40 #include "llvm/IR/Value.h"
  41 #include "llvm/Support/MachineValueType.h"
  42 #include <algorithm>
  43 #include <cassert>
  44 #include <cstdint>
  45 #include <iterator>
  46
  47 #define DEBUG_TYPE "aarch64-call-lowering"
  48
  49 using namespace llvm;
  50
  51 AArch64CallLowering::AArch64CallLowering(const AArch64TargetLowering &TLI)
  52   : CallLowering(&TLI) {}
  53
  54 namespace {
  55 struct IncomingArgHandler : public CallLowering::ValueHandler {
  56   IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
  57                      CCAssignFn *AssignFn)
  58       : ValueHandler(MIRBuilder, MRI, AssignFn), StackUsed(0) {}
  59
  60   Register getStackAddress(uint64_t Size, int64_t Offset,
  61                            MachinePointerInfo &MPO) override {
  62     auto &MFI = MIRBuilder.getMF().getFrameInfo();
  63     int FI = MFI.CreateFixedObject(Size, Offset, true);
  64     MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
  65     Register AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 64));
  66     MIRBuilder.buildFrameIndex(AddrReg, FI);
  67     StackUsed = std::max(StackUsed, Size + Offset);
  68     return AddrReg;
  69   }
  70
  71   void assignValueToReg(Register ValVReg, Register PhysReg,
  72                         CCValAssign &VA) override {
  73     markPhysRegUsed(PhysReg);
  74     switch (VA.getLocInfo()) {
  75     default:
  76       MIRBuilder.buildCopy(ValVReg, PhysReg);
  77       break;
  78     case CCValAssign::LocInfo::SExt:
  79     case CCValAssign::LocInfo::ZExt:
  80     case CCValAssign::LocInfo::AExt: {
  81       auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
  82       MIRBuilder.buildTrunc(ValVReg, Copy);
  83       break;
  84     }
  85     }
  86   }
  87
  88   void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
  89                             MachinePointerInfo &MPO, CCValAssign &VA) override {
  90     // FIXME: Get alignment
  91     auto MMO = MIRBuilder.getMF().getMachineMemOperand(
  92         MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, Size,
  93         1);
  94     MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
  95   }
  96
  97   /// How the physical register gets marked varies between formal
  98   /// parameters (it's a basic-block live-in), and a call instruction
  99   /// (it's an implicit-def of the BL).
 100   virtual void markPhysRegUsed(unsigned PhysReg) = 0;
 101
 102   bool isIncomingArgumentHandler() const override { return true; }
 103
 104   uint64_t StackUsed;
 105 };
 106
 107 struct FormalArgHandler : public IncomingArgHandler {
 108   FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
 109                    CCAssignFn *AssignFn)
 110     : IncomingArgHandler(MIRBuilder, MRI, AssignFn) {}
 111
 112   void markPhysRegUsed(unsigned PhysReg) override {
 113     MIRBuilder.getMRI()->addLiveIn(PhysReg);
 114     MIRBuilder.getMBB().addLiveIn(PhysReg);
 115   }
 116 };
 117
 118 struct CallReturnHandler : public IncomingArgHandler {
 119   CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
 120                     MachineInstrBuilder MIB, CCAssignFn *AssignFn)
 121     : IncomingArgHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
 122
 123   void markPhysRegUsed(unsigned PhysReg) override {
 124     MIB.addDef(PhysReg, RegState::Implicit);
 125   }
 126
 127   MachineInstrBuilder MIB;
 128 };
 129
 130 struct OutgoingArgHandler : public CallLowering::ValueHandler {
 131   OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
 132                      MachineInstrBuilder MIB, CCAssignFn *AssignFn,
 133                      CCAssignFn *AssignFnVarArg)
 134       : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
 135         AssignFnVarArg(AssignFnVarArg), StackSize(0) {}
 136
 137   Register getStackAddress(uint64_t Size, int64_t Offset,
 138                            MachinePointerInfo &MPO) override {
 139     LLT p0 = LLT::pointer(0, 64);
 140     LLT s64 = LLT::scalar(64);
 141     Register SPReg = MRI.createGenericVirtualRegister(p0);
 142     MIRBuilder.buildCopy(SPReg, Register(AArch64::SP));
 143
 144     Register OffsetReg = MRI.createGenericVirtualRegister(s64);
 145     MIRBuilder.buildConstant(OffsetReg, Offset);
 146
 147     Register AddrReg = MRI.createGenericVirtualRegister(p0);
 148     MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
 149
 150     MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
 151     return AddrReg;
 152   }
 153
 154   void assignValueToReg(Register ValVReg, Register PhysReg,
 155                         CCValAssign &VA) override {
 156     MIB.addUse(PhysReg, RegState::Implicit);
 157     Register ExtReg = extendRegister(ValVReg, VA);
 158     MIRBuilder.buildCopy(PhysReg, ExtReg);
 159   }
 160
 161   void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
 162                             MachinePointerInfo &MPO, CCValAssign &VA) override {
 163     if (VA.getLocInfo() == CCValAssign::LocInfo::AExt) {
 164       Size = VA.getLocVT().getSizeInBits() / 8;
 165       ValVReg = MIRBuilder.buildAnyExt(LLT::scalar(Size * 8), ValVReg)
 166                     ->getOperand(0)
 167                     .getReg();
 168     }
 169     auto MMO = MIRBuilder.getMF().getMachineMemOperand(
 170         MPO, MachineMemOperand::MOStore, Size, 1);
 171     MIRBuilder.buildStore(ValVReg, Addr, *MMO);
 172   }
 173
 174   bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
 175                  CCValAssign::LocInfo LocInfo,
 176                  const CallLowering::ArgInfo &Info,
 177                  ISD::ArgFlagsTy Flags,
 178                  CCState &State) override {
 179     bool Res;
 180     if (Info.IsFixed)
 181       Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State);
 182     else
 183       Res = AssignFnVarArg(ValNo, ValVT, LocVT, LocInfo, Flags, State);
 184
 185     StackSize = State.getNextStackOffset();
 186     return Res;
 187   }
 188
 189   MachineInstrBuilder MIB;
 190   CCAssignFn *AssignFnVarArg;
 191   uint64_t StackSize;
 192 };
 193 } // namespace
 194
 195 void AArch64CallLowering::splitToValueTypes(
 196     const ArgInfo &OrigArg, SmallVectorImpl<ArgInfo> &SplitArgs,
 197     const DataLayout &DL, MachineRegisterInfo &MRI, CallingConv::ID CallConv) const {
 198   const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
 199   LLVMContext &Ctx = OrigArg.Ty->getContext();
 200
 201   if (OrigArg.Ty->isVoidTy())
 202     return;
 203
 204   SmallVector<EVT, 4> SplitVTs;
 205   SmallVector<uint64_t, 4> Offsets;
 206   ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0);
 207
 208   if (SplitVTs.size() == 1) {
 209     // No splitting to do, but we want to replace the original type (e.g. [1 x
 210     // double] -> double).
 211     SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx),
 212                            OrigArg.Flags[0], OrigArg.IsFixed);
 213     return;
 214   }
 215
 216   // Create one ArgInfo for each virtual register in the original ArgInfo.
 217   assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch");
 218
 219   bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters(
 220       OrigArg.Ty, CallConv, false);
 221   for (unsigned i = 0, e = SplitVTs.size(); i < e; ++i) {
 222     Type *SplitTy = SplitVTs[i].getTypeForEVT(Ctx);
 223     SplitArgs.emplace_back(OrigArg.Regs[i], SplitTy, OrigArg.Flags[0],
 224                            OrigArg.IsFixed);
 225     if (NeedsRegBlock)
 226       SplitArgs.back().Flags[0].setInConsecutiveRegs();
 227   }
 228
 229   SplitArgs.back().Flags[0].setInConsecutiveRegsLast();
 230 }
 231
 232 bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
 233                                       const Value *Val,
 234                                       ArrayRef<Register> VRegs,
 235                                       Register SwiftErrorVReg) const {
 236
 237   // Check if a tail call was lowered in this block. If so, we already handled
 238   // the terminator.
 239   MachineFunction &MF = MIRBuilder.getMF();
 240   if (MF.getFrameInfo().hasTailCall()) {
 241     MachineBasicBlock &MBB = MIRBuilder.getMBB();
 242     auto FirstTerm = MBB.getFirstTerminator();
 243     if (FirstTerm != MBB.end() && FirstTerm->isCall())
 244       return true;
 245   }
 246
 247   auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR);
 248   assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
 249          "Return value without a vreg");
 250
 251   bool Success = true;
 252   if (!VRegs.empty()) {
 253     MachineFunction &MF = MIRBuilder.getMF();
 254     const Function &F = MF.getFunction();
 255
 256     MachineRegisterInfo &MRI = MF.getRegInfo();
 257     const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
 258     CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
 259     auto &DL = F.getParent()->getDataLayout();
 260     LLVMContext &Ctx = Val->getType()->getContext();
 261
 262     SmallVector<EVT, 4> SplitEVTs;
 263     ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
 264     assert(VRegs.size() == SplitEVTs.size() &&
 265            "For each split Type there should be exactly one VReg.");
 266
 267     SmallVector<ArgInfo, 8> SplitArgs;
 268     CallingConv::ID CC = F.getCallingConv();
 269
 270     for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
 271       if (TLI.getNumRegistersForCallingConv(Ctx, CC, SplitEVTs[i]) > 1) {
 272         LLVM_DEBUG(dbgs() << "Can't handle extended arg types which need split");
 273         return false;
 274       }
 275
 276       Register CurVReg = VRegs[i];
 277       ArgInfo CurArgInfo = ArgInfo{CurVReg, SplitEVTs[i].getTypeForEVT(Ctx)};
 278       setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
 279
 280       // i1 is a special case because SDAG i1 true is naturally zero extended
 281       // when widened using ANYEXT. We need to do it explicitly here.
 282       if (MRI.getType(CurVReg).getSizeInBits() == 1) {
 283         CurVReg = MIRBuilder.buildZExt(LLT::scalar(8), CurVReg).getReg(0);
 284       } else {
 285         // Some types will need extending as specified by the CC.
 286         MVT NewVT = TLI.getRegisterTypeForCallingConv(Ctx, CC, SplitEVTs[i]);
 287         if (EVT(NewVT) != SplitEVTs[i]) {
 288           unsigned ExtendOp = TargetOpcode::G_ANYEXT;
 289           if (F.getAttributes().hasAttribute(AttributeList::ReturnIndex,
 290                                              Attribute::SExt))
 291             ExtendOp = TargetOpcode::G_SEXT;
 292           else if (F.getAttributes().hasAttribute(AttributeList::ReturnIndex,
 293                                                   Attribute::ZExt))
 294             ExtendOp = TargetOpcode::G_ZEXT;
 295
 296           LLT NewLLT(NewVT);
 297           LLT OldLLT(MVT::getVT(CurArgInfo.Ty));
 298           CurArgInfo.Ty = EVT(NewVT).getTypeForEVT(Ctx);
 299           // Instead of an extend, we might have a vector type which needs
 300           // padding with more elements, e.g. <2 x half> -> <4 x half>.
 301           if (NewVT.isVector()) {
 302             if (OldLLT.isVector()) {
 303               if (NewLLT.getNumElements() > OldLLT.getNumElements()) {
 304                 // We don't handle VA types which are not exactly twice the
 305                 // size, but can easily be done in future.
 306                 if (NewLLT.getNumElements() != OldLLT.getNumElements() * 2) {
 307                   LLVM_DEBUG(dbgs() << "Outgoing vector ret has too many elts");
 308                   return false;
 309                 }
 310                 auto Undef = MIRBuilder.buildUndef({OldLLT});
 311                 CurVReg =
 312                     MIRBuilder.buildMerge({NewLLT}, {CurVReg, Undef.getReg(0)})
 313                         .getReg(0);
 314               } else {
 315                 // Just do a vector extend.
 316                 CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
 317                               .getReg(0);
 318               }
 319             } else if (NewLLT.getNumElements() == 2) {
 320               // We need to pad a <1 x S> type to <2 x S>. Since we don't have
 321               // <1 x S> vector types in GISel we use a build_vector instead
 322               // of a vector merge/concat.
 323               auto Undef = MIRBuilder.buildUndef({OldLLT});
 324               CurVReg =
 325                   MIRBuilder
 326                       .buildBuildVector({NewLLT}, {CurVReg, Undef.getReg(0)})
 327                       .getReg(0);
 328             } else {
 329               LLVM_DEBUG(dbgs() << "Could not handle ret ty");
 330               return false;
 331             }
 332           } else {
 333             // A scalar extend.
 334             CurVReg =
 335                 MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg}).getReg(0);
 336           }
 337         }
 338       }
 339       if (CurVReg != CurArgInfo.Regs[0]) {
 340         CurArgInfo.Regs[0] = CurVReg;
 341         // Reset the arg flags after modifying CurVReg.
 342         setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
 343       }
 344      splitToValueTypes(CurArgInfo, SplitArgs, DL, MRI, CC);
 345     }
 346
 347     OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFn, AssignFn);
 348     Success = handleAssignments(MIRBuilder, SplitArgs, Handler);
 349   }
 350
 351   if (SwiftErrorVReg) {
 352     MIB.addUse(AArch64::X21, RegState::Implicit);
 353     MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg);
 354   }
 355
 356   MIRBuilder.insertInstr(MIB);
 357   return Success;
 358 }
 359
 360 bool AArch64CallLowering::lowerFormalArguments(
 361     MachineIRBuilder &MIRBuilder, const Function &F,
 362     ArrayRef<ArrayRef<Register>> VRegs) const {
 363   MachineFunction &MF = MIRBuilder.getMF();
 364   MachineBasicBlock &MBB = MIRBuilder.getMBB();
 365   MachineRegisterInfo &MRI = MF.getRegInfo();
 366   auto &DL = F.getParent()->getDataLayout();
 367
 368   SmallVector<ArgInfo, 8> SplitArgs;
 369   unsigned i = 0;
 370   for (auto &Arg : F.args()) {
 371     if (DL.getTypeStoreSize(Arg.getType()) == 0)
 372       continue;
 373
 374     ArgInfo OrigArg{VRegs[i], Arg.getType()};
 375     setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, F);
 376
 377     splitToValueTypes(OrigArg, SplitArgs, DL, MRI, F.getCallingConv());
 378     ++i;
 379   }
 380
 381   if (!MBB.empty())
 382     MIRBuilder.setInstr(*MBB.begin());
 383
 384   const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
 385   CCAssignFn *AssignFn =
 386       TLI.CCAssignFnForCall(F.getCallingConv(), /*IsVarArg=*/false);
 387
 388   FormalArgHandler Handler(MIRBuilder, MRI, AssignFn);
 389   if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
 390     return false;
 391
 392   if (F.isVarArg()) {
 393     if (!MF.getSubtarget<AArch64Subtarget>().isTargetDarwin()) {
 394       // FIXME: we need to reimplement saveVarArgsRegisters from
 395       // AArch64ISelLowering.
 396       return false;
 397     }
 398
 399     // We currently pass all varargs at 8-byte alignment.
 400     uint64_t StackOffset = alignTo(Handler.StackUsed, 8);
 401
 402     auto &MFI = MIRBuilder.getMF().getFrameInfo();
 403     AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
 404     FuncInfo->setVarArgsStackIndex(MFI.CreateFixedObject(4, StackOffset, true));
 405   }
 406
 407   auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
 408   if (Subtarget.hasCustomCallingConv())
 409     Subtarget.getRegisterInfo()->UpdateCustomCalleeSavedRegs(MF);
 410
 411   // Move back to the end of the basic block.
 412   MIRBuilder.setMBB(MBB);
 413
 414   return true;
 415 }
 416
 417 /// Return true if the calling convention is one that we can guarantee TCO for.
 418 static bool canGuaranteeTCO(CallingConv::ID CC) {
 419   return CC == CallingConv::Fast;
 420 }
 421
 422 /// Return true if we might ever do TCO for calls with this calling convention.
 423 static bool mayTailCallThisCC(CallingConv::ID CC) {
 424   switch (CC) {
 425   case CallingConv::C:
 426   case CallingConv::PreserveMost:
 427   case CallingConv::Swift:
 428     return true;
 429   default:
 430     return canGuaranteeTCO(CC);
 431   }
 432 }
 433
 434 bool AArch64CallLowering::isEligibleForTailCallOptimization(
 435     MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const {
 436   CallingConv::ID CalleeCC = Info.CallConv;
 437   MachineFunction &MF = MIRBuilder.getMF();
 438   const Function &CallerF = MF.getFunction();
 439   CallingConv::ID CallerCC = CallerF.getCallingConv();
 440   bool CCMatch = CallerCC == CalleeCC;
 441
 442   LLVM_DEBUG(dbgs() << "Attempting to lower call as tail call\n");
 443
 444   if (Info.SwiftErrorVReg) {
 445     // TODO: We should handle this.
 446     // Note that this is also handled by the check for no outgoing arguments.
 447     // Proactively disabling this though, because the swifterror handling in
 448     // lowerCall inserts a COPY *after* the location of the call.
 449     LLVM_DEBUG(dbgs() << "... Cannot handle tail calls with swifterror yet.\n");
 450     return false;
 451   }
 452
 453   if (!Info.OrigRet.Ty->isVoidTy()) {
 454     // TODO: lowerCall will insert COPYs to handle the call's return value.
 455     // This needs some refactoring to avoid this with tail call returns. For
 456     // now, just don't handle that case.
 457     LLVM_DEBUG(dbgs() << "... Cannot handle non-void return types yet.\n");
 458     return false;
 459   }
 460
 461   if (!mayTailCallThisCC(CalleeCC)) {
 462     LLVM_DEBUG(dbgs() << "... Calling convention cannot be tail called.\n");
 463     return false;
 464   }
 465
 466   if (Info.IsVarArg) {
 467     LLVM_DEBUG(dbgs() << "... Tail calling varargs not supported yet.\n");
 468     return false;
 469   }
 470
 471   // Byval parameters hand the function a pointer directly into the stack area
 472   // we want to reuse during a tail call. Working around this *is* possible (see
 473   // X86).
 474   //
 475   // FIXME: In AArch64ISelLowering, this isn't worked around. Can/should we try
 476   // it?
 477   //
 478   // On Windows, "inreg" attributes signify non-aggregate indirect returns.
 479   // In this case, it is necessary to save/restore X0 in the callee. Tail
 480   // call opt interferes with this. So we disable tail call opt when the
 481   // caller has an argument with "inreg" attribute.
 482   //
 483   // FIXME: Check whether the callee also has an "inreg" argument.
 484   if (any_of(CallerF.args(), [](const Argument &A) {
 485         return A.hasByValAttr() || A.hasInRegAttr();
 486       })) {
 487     LLVM_DEBUG(dbgs() << "... Cannot tail call from callers with byval or "
 488                          "inreg arguments.\n");
 489     return false;
 490   }
 491
 492   // Externally-defined functions with weak linkage should not be
 493   // tail-called on AArch64 when the OS does not support dynamic
 494   // pre-emption of symbols, as the AAELF spec requires normal calls
 495   // to undefined weak functions to be replaced with a NOP or jump to the
 496   // next instruction. The behaviour of branch instructions in this
 497   // situation (as used for tail calls) is implementation-defined, so we
 498   // cannot rely on the linker replacing the tail call with a return.
 499   if (Info.Callee.isGlobal()) {
 500     const GlobalValue *GV = Info.Callee.getGlobal();
 501     const Triple &TT = MF.getTarget().getTargetTriple();
 502     if (GV->hasExternalWeakLinkage() &&
 503         (!TT.isOSWindows() || TT.isOSBinFormatELF() ||
 504          TT.isOSBinFormatMachO())) {
 505       LLVM_DEBUG(dbgs() << "... Cannot tail call externally-defined function "
 506                            "with weak linkage for this OS.\n");
 507       return false;
 508     }
 509   }
 510
 511   // If we have -tailcallopt and matching CCs, at this point, we could return
 512   // true. However, we don't have full tail call support yet. So, continue
 513   // checking. We want to emit a sibling call.
 514
 515   // I want anyone implementing a new calling convention to think long and hard
 516   // about this assert.
 517   assert((!Info.IsVarArg || CalleeCC == CallingConv::C) &&
 518          "Unexpected variadic calling convention");
 519
 520   // For now, only support the case where the calling conventions match.
 521   if (!CCMatch) {
 522     LLVM_DEBUG(
 523         dbgs()
 524         << "... Cannot tail call with mismatched calling conventions yet.\n");
 525     return false;
 526   }
 527
 528   // For now, only handle callees that take no arguments.
 529   if (!Info.OrigArgs.empty()) {
 530     LLVM_DEBUG(
 531         dbgs()
 532         << "... Cannot tail call callees with outgoing arguments yet.\n");
 533     return false;
 534   }
 535
 536   LLVM_DEBUG(
 537       dbgs() << "... Call is eligible for tail call optimization.\n");
 538   return true;
 539 }
 540
 541 static unsigned getCallOpcode(const Function &CallerF, bool IsIndirect,
 542                               bool IsTailCall) {
 543   if (!IsTailCall)
 544     return IsIndirect ? AArch64::BLR : AArch64::BL;
 545
 546   if (!IsIndirect)
 547     return AArch64::TCRETURNdi;
 548
 549   // When BTI is enabled, we need to use TCRETURNriBTI to make sure that we use
 550   // x16 or x17.
 551   if (CallerF.hasFnAttribute("branch-target-enforcement"))
 552     return AArch64::TCRETURNriBTI;
 553
 554   return AArch64::TCRETURNri;
 555 }
 556
 557 bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
 558                                     CallLoweringInfo &Info) const {
 559   MachineFunction &MF = MIRBuilder.getMF();
 560   const Function &F = MF.getFunction();
 561   MachineRegisterInfo &MRI = MF.getRegInfo();
 562   auto &DL = F.getParent()->getDataLayout();
 563
 564   if (Info.IsMustTailCall) {
 565     // TODO: Until we lower all tail calls, we should fall back on this.
 566     LLVM_DEBUG(dbgs() << "Cannot lower musttail calls yet.\n");
 567     return false;
 568   }
 569
 570   if (Info.IsTailCall && MF.getTarget().Options.GuaranteedTailCallOpt) {
 571     // TODO: Until we lower all tail calls, we should fall back on this.
 572     LLVM_DEBUG(dbgs() << "Cannot handle -tailcallopt yet.\n");
 573     return false;
 574   }
 575
 576   SmallVector<ArgInfo, 8> SplitArgs;
 577   for (auto &OrigArg : Info.OrigArgs) {
 578     splitToValueTypes(OrigArg, SplitArgs, DL, MRI, Info.CallConv);
 579     // AAPCS requires that we zero-extend i1 to 8 bits by the caller.
 580     if (OrigArg.Ty->isIntegerTy(1))
 581       SplitArgs.back().Flags[0].setZExt();
 582   }
 583
 584   bool IsSibCall =
 585       Info.IsTailCall && isEligibleForTailCallOptimization(MIRBuilder, Info);
 586   if (IsSibCall)
 587     MF.getFrameInfo().setHasTailCall();
 588
 589   // Find out which ABI gets to decide where things go.
 590   const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
 591   CCAssignFn *AssignFnFixed =
 592       TLI.CCAssignFnForCall(Info.CallConv, /*IsVarArg=*/false);
 593   CCAssignFn *AssignFnVarArg =
 594       TLI.CCAssignFnForCall(Info.CallConv, /*IsVarArg=*/true);
 595
 596   // If we have a sibling call, then we don't have to adjust the stack.
 597   // Otherwise, we need to adjust it.
 598   MachineInstrBuilder CallSeqStart;
 599   if (!IsSibCall)
 600     CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN);
 601
 602   // Create a temporarily-floating call instruction so we can add the implicit
 603   // uses of arg registers.
 604   unsigned Opc = getCallOpcode(F, Info.Callee.isReg(), IsSibCall);
 605
 606   // TODO: Right now, regbankselect doesn't know how to handle the rtcGPR64
 607   // register class. Until we can do that, we should fall back here.
 608   if (Opc == AArch64::TCRETURNriBTI) {
 609     LLVM_DEBUG(
 610         dbgs() << "Cannot lower indirect tail calls with BTI enabled yet.\n");
 611     return false;
 612   }
 613
 614   auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
 615   MIB.add(Info.Callee);
 616
 617   // Add the byte offset for the tail call. We only have sibling calls, so this
 618   // is always 0.
 619   // TODO: Handle tail calls where we will have a different value here.
 620   if (IsSibCall)
 621     MIB.addImm(0);
 622
 623   // Tell the call which registers are clobbered.
 624   auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
 625   const uint32_t *Mask = TRI->getCallPreservedMask(MF, F.getCallingConv());
 626   if (MF.getSubtarget<AArch64Subtarget>().hasCustomCallingConv())
 627     TRI->UpdateCustomCallPreservedMask(MF, &Mask);
 628   MIB.addRegMask(Mask);
 629
 630   if (TRI->isAnyArgRegReserved(MF))
 631     TRI->emitReservedArgRegCallError(MF);
 632
 633   // Do the actual argument marshalling.
 634   SmallVector<unsigned, 8> PhysRegs;
 635   OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFnFixed,
 636                              AssignFnVarArg);
 637   if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
 638     return false;
 639
 640   // Now we can add the actual call instruction to the correct basic block.
 641   MIRBuilder.insertInstr(MIB);
 642
 643   // If Callee is a reg, since it is used by a target specific
 644   // instruction, it must have a register class matching the
 645   // constraint of that instruction.
 646   if (Info.Callee.isReg())
 647     MIB->getOperand(0).setReg(constrainOperandRegClass(
 648         MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
 649         *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Info.Callee,
 650         0));
 651
 652   // Finally we can copy the returned value back into its virtual-register. In
 653   // symmetry with the arugments, the physical register must be an
 654   // implicit-define of the call instruction.
 655   CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
 656   if (!Info.OrigRet.Ty->isVoidTy()) {
 657     SplitArgs.clear();
 658
 659     splitToValueTypes(Info.OrigRet, SplitArgs, DL, MRI, F.getCallingConv());
 660
 661     CallReturnHandler Handler(MIRBuilder, MRI, MIB, RetAssignFn);
 662     if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
 663       return false;
 664   }
 665
 666   if (Info.SwiftErrorVReg) {
 667     MIB.addDef(AArch64::X21, RegState::Implicit);
 668     MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21));
 669   }
 670
 671   if (!IsSibCall) {
 672     // If we aren't sibcalling, we need to move the stack.
 673     CallSeqStart.addImm(Handler.StackSize).addImm(0);
 674     MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP)
 675         .addImm(Handler.StackSize)
 676         .addImm(0);
 677   }
 678
 679   return true;
 680 }