test/MC/AArch64/SVE/fmul-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Invalid immediates (must be 0.5 or 2.0)
   5
   6 fmul z0.h, p0/m, z0.h, #1.0
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.5 or 2.0.
   8 // CHECK-NEXT: fmul z0.h, p0/m, z0.h, #1.0
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 fmul z0.h, p0/m, z0.h, #0.0
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.5 or 2.0.
  13 // CHECK-NEXT: fmul z0.h, p0/m, z0.h, #0.0
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 fmul z0.h, p0/m, z0.h, #0.4999999999999999999999999
  17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.5 or 2.0.
  18 // CHECK-NEXT: fmul z0.h, p0/m, z0.h, #0.4999999999999999999999999
  19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  20
  21 fmul z0.h, p0/m, z0.h, #0.5000000000000000000000001
  22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.5 or 2.0.
  23 // CHECK-NEXT: fmul z0.h, p0/m, z0.h, #0.5000000000000000000000001
  24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  25
  26 fmul z0.h, p0/m, z0.h, #2.0000000000000000000000001
  27 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.5 or 2.0.
  28 // CHECK-NEXT: fmul z0.h, p0/m, z0.h, #2.0000000000000000000000001
  29 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  30
  31 fmul z0.h, p0/m, z0.h, #1.9999999999999999999999999
  32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.5 or 2.0.
  33 // CHECK-NEXT: fmul z0.h, p0/m, z0.h, #1.9999999999999999999999999
  34 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  35
  36
  37 // --------------------------------------------------------------------------//
  38 // Restricted ZPR range
  39
  40 fmul z0.h, z0.h, z8.b[0]
  41 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z7.h
  42 // CHECK-NEXT: fmul z0.h, z0.h, z8.b[0]
  43 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  44
  45 fmul z0.h, z0.h, z8.h[0]
  46 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  47 // CHECK-NEXT: fmul z0.h, z0.h, z8.h[0]
  48 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  49
  50 fmul z0.s, z0.s, z8.s[0]
  51 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  52 // CHECK-NEXT: fmul z0.s, z0.s, z8.s[0]
  53 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  54
  55 fmul z0.d, z0.d, z16.d[0]
  56 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  57 // CHECK-NEXT: fmul z0.d, z0.d, z16.d[0]
  58 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  59
  60
  61 // --------------------------------------------------------------------------//
  62 // Index out of bounds
  63
  64 fmul z0.h, z0.h, z0.h[-1]
  65 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
  66 // CHECK-NEXT: fmul z0.h, z0.h, z0.h[-1]
  67 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  68
  69 fmul z0.h, z0.h, z0.h[8]
  70 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
  71 // CHECK-NEXT: fmul z0.h, z0.h, z0.h[8]
  72 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  73
  74 fmul z0.s, z0.s, z0.s[-1]
  75 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
  76 // CHECK-NEXT: fmul z0.s, z0.s, z0.s[-1]
  77 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  78
  79 fmul z0.s, z0.s, z0.s[4]
  80 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
  81 // CHECK-NEXT: fmul z0.s, z0.s, z0.s[4]
  82 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  83
  84 fmul z0.d, z0.d, z0.d[-1]
  85 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
  86 // CHECK-NEXT: fmul z0.d, z0.d, z0.d[-1]
  87 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  88
  89 fmul z0.d, z0.d, z0.d[2]
  90 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
  91 // CHECK-NEXT: fmul z0.d, z0.d, z0.d[2]
  92 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  93
  94
  95 // ------------------------------------------------------------------------- //
  96 // Tied operands must match
  97
  98 fmul    z0.h, p7/m, z1.h, z31.h
  99 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
 100 // CHECK-NEXT: fmul    z0.h, p7/m, z1.h, z31.h
 101 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 102
 103
 104 // ------------------------------------------------------------------------- //
 105 // Invalid element widths.
 106
 107 fmul    z0.b, p7/m, z0.b, z31.b
 108 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 109 // CHECK-NEXT: fmul    z0.b, p7/m, z0.b, z31.b
 110 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 111
 112 fmul    z0.h, p7/m, z0.h, z31.s
 113 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 114 // CHECK-NEXT: fmul    z0.h, p7/m, z0.h, z31.s
 115 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 116
 117 fmul z0.b, z1.b, z2.b
 118 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 119 // CHECK-NEXT: fmul z0.b, z1.b, z2.b
 120 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 121
 122 fmul z0.h, z1.s, z2.s
 123 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 124 // CHECK-NEXT: fmul z0.h, z1.s, z2.s
 125 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 126
 127
 128 // ------------------------------------------------------------------------- //
 129 // Invalid predicate
 130
 131 fmul    z0.h, p8/m, z0.h, z31.h
 132 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
 133 // CHECK-NEXT: fmul    z0.h, p8/m, z0.h, z31.h
 134 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 135
 136
 137 // --------------------------------------------------------------------------//
 138 // Negative tests for instructions that are incompatible with movprfx
 139
 140 movprfx z0.d, p0/z, z7.d
 141 fmul z0.d, z1.d, z31.d
 142 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
 143 // CHECK-NEXT: fmul z0.d, z1.d, z31.d
 144 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 145
 146 movprfx z0, z7
 147 fmul z0.d, z1.d, z31.d
 148 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
 149 // CHECK-NEXT: fmul z0.d, z1.d, z31.d
 150 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 151
 152 movprfx z31.d, p0/z, z6.d
 153 fmul    z31.d, z31.d, z15.d[1]
 154 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
 155 // CHECK-NEXT: fmul    z31.d, z31.d, z15.d[1]
 156 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 157
 158 movprfx z31, z6
 159 fmul    z31.d, z31.d, z15.d[1]
 160 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
 161 // CHECK-NEXT: fmul    z31.d, z31.d, z15.d[1]
 162 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: