test/MC/AArch64/SVE/sminv-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
   2
   3
   4 // ------------------------------------------------------------------------- //
   5 // Invalid destination or source register.
   6
   7 sminv d0, p7, z31.b
   8 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
   9 // CHECK-NEXT: sminv d0, p7, z31.b
  10 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  11
  12 sminv d0, p7, z31.h
  13 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  14 // CHECK-NEXT: sminv d0, p7, z31.h
  15 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  16
  17 sminv d0, p7, z31.s
  18 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  19 // CHECK-NEXT: sminv d0, p7, z31.s
  20 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  21
  22 sminv v0.2d, p7, z31.d
  23 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  24 // CHECK-NEXT: sminv v0.2d, p7, z31.d
  25 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  26
  27
  28 // ------------------------------------------------------------------------- //
  29 // Invalid predicate
  30
  31 sminv h0, p8, z31.h
  32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  33 // CHECK-NEXT: sminv h0, p8, z31.h
  34 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  35
  36 sminv h0, p7.b, z31.h
  37 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  38 // CHECK-NEXT: sminv h0, p7.b, z31.h
  39 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  40
  41 sminv h0, p7.q, z31.h
  42 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  43 // CHECK-NEXT: sminv h0, p7.q, z31.h
  44 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  45
  46
  47 // --------------------------------------------------------------------------//
  48 // Negative tests for instructions that are incompatible with movprfx
  49
  50 movprfx z31.d, p7/z, z6.d
  51 sminv d0, p7, z31.d
  52 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
  53 // CHECK-NEXT: sminv d0, p7, z31.d
  54 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  55
  56 movprfx z31, z6
  57 sminv d0, p7, z31.d
  58 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
  59 // CHECK-NEXT: sminv d0, p7, z31.d
  60 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: