test/MC/AArch64/SVE/sqdecw-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
   2
   3 // ------------------------------------------------------------------------- //
   4 // Invalid result register
   5
   6 sqdecw w0
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
   8 // CHECK-NEXT: sqdecw w0
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 sqdecw wsp
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
  13 // CHECK-NEXT: sqdecw wsp
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 sqdecw sp
  17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
  18 // CHECK-NEXT: sqdecw sp
  19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  20
  21 sqdecw z0.d
  22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  23 // CHECK-NEXT: sqdecw z0.d
  24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  25
  26
  27 // ------------------------------------------------------------------------- //
  28 // Operands not matching up
  29
  30 sqdecw x0, w1
  31 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
  32 // CHECK-NEXT: sqdecw x0, w1
  33 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  34
  35 sqdecw x0, x1
  36 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
  37 // CHECK-NEXT: sqdecw x0, x1
  38 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  39
  40
  41 // ------------------------------------------------------------------------- //
  42 // Immediate not compatible with encode/decode function.
  43
  44 sqdecw x0, all, mul #-1
  45 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
  46 // CHECK-NEXT: sqdecw x0, all, mul #-1
  47 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  48
  49 sqdecw x0, all, mul #0
  50 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
  51 // CHECK-NEXT: sqdecw x0, all, mul #0
  52 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  53
  54 sqdecw x0, all, mul #17
  55 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
  56 // CHECK-NEXT: sqdecw x0, all, mul #17
  57 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  58
  59
  60 // ------------------------------------------------------------------------- //
  61 // Invalid predicate patterns
  62
  63 sqdecw x0, vl512
  64 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
  65 // CHECK-NEXT: sqdecw x0, vl512
  66 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  67
  68 sqdecw x0, vl9
  69 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
  70 // CHECK-NEXT: sqdecw x0, vl9
  71 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  72
  73 sqdecw x0, #-1
  74 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
  75 // CHECK-NEXT: sqdecw x0, #-1
  76 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  77
  78 sqdecw x0, #32
  79 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
  80 // CHECK-NEXT: sqdecw x0, #32
  81 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  82
  83
  84 // --------------------------------------------------------------------------//
  85 // Negative tests for instructions that are incompatible with movprfx
  86
  87 movprfx z0.s, p0/z, z7.s
  88 sqdecw  z0.s
  89 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
  90 // CHECK-NEXT: sqdecw  z0.s
  91 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  92
  93 movprfx z0.s, p0/z, z7.s
  94 sqdecw  z0.s, pow2, mul #16
  95 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
  96 // CHECK-NEXT: sqdecw  z0.s, pow2, mul #16
  97 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  98
  99 movprfx z0.s, p0/z, z7.s
 100 sqdecw  z0.s, pow2
 101 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
 102 // CHECK-NEXT: sqdecw  z0.s, pow2
 103 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: