test/MC/AArch64/SVE/tbl-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
   2
   3 tbl z0.h, z0.h, z0.b
   4 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
   5 // CHECK-NEXT: tbl z0.h, z0.h, z0.b
   6 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
   7
   8 tbl { z0.h }, z0.h, z0.h
   9 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
  10 // CHECK-NEXT: tbl { z0.h }, z0.h, z0.h
  11 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  12
  13
  14 // --------------------------------------------------------------------------//
  15 // Negative tests for instructions that are incompatible with movprfx
  16
  17 movprfx z31.d, p0/z, z6.d
  18 tbl  z31.d, { z31.d }, z31.d
  19 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
  20 // CHECK-NEXT: tbl  z31.d, { z31.d }, z31.d
  21 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  22
  23 movprfx z31, z6
  24 tbl  z31.d, { z31.d }, z31.d
  25 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
  26 // CHECK-NEXT: tbl  z31.d, { z31.d }, z31.d
  27 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: