[llvm-readobj] - Simplify stack-sizes.test test case.
[llvm-complete.git] / test / MC / ARM / invalid-crc32.s
bloba541002acb1797b33e14aa88d2167e54de8bad3f
1 @ RUN: not llvm-mc -triple=armv8 -show-encoding < %s 2>&1 | FileCheck %s
2 @ RUN: not llvm-mc -triple=thumbv8 -show-encoding < %s 2>&1 | FileCheck %s
4 crc32cbeq r0, r1, r2
5 crc32bne r0, r1, r2
6 crc32chcc r0, r1, r2
7 crc32hpl r0, r1, r2
8 crc32cwgt r0, r1, r2
9 crc32wle r0, r1, r2
11 @ CHECK: error: instruction 'crc32cb' is not predicable, but condition code specified
12 @ CHECK: error: instruction 'crc32b' is not predicable, but condition code specified
13 @ CHECK: error: instruction 'crc32ch' is not predicable, but condition code specified
14 @ CHECK: error: instruction 'crc32h' is not predicable, but condition code specified
15 @ CHECK: error: instruction 'crc32cw' is not predicable, but condition code specified
16 @ CHECK: error: instruction 'crc32w' is not predicable, but condition code specified