test/MC/ARM/invalid-neon-v8.s

   1 @ RUN: not llvm-mc -triple armv8 -mattr=-fp-armv8d16sp -show-encoding < %s 2>&1 | FileCheck %s
   2
   3 vmaxnm.f32 s4, d5, q1
   4 @ CHECK: error: invalid instruction
   5 vmaxnm.f64.f64 s4, d5, q1
   6 @ CHECK: error: invalid instruction
   7 vmaxnmge.f64.f64 s4, d5, q1
   8 @ CHECK: error: instruction 'vmaxnm' is not predicable, but condition code specified
   9
  10 vcvta.s32.f32 s1, s2
  11 @ CHECK: error: instruction requires: FPARMv8
  12 vcvtp.u32.f32 s1, d2
  13 @ CHECK: error: operand must be a register in range [d0, d31]
  14 vcvtp.f32.u32 d1, q2
  15 @ CHECK: error: invalid instruction
  16 vcvtplo.f32.u32 s1, s2
  17 @ CHECK: error: instruction 'vcvtp' is not predicable, but condition code specified
  18
  19 vrinta.f64.f64 s3, d12
  20 @ CHECK: error: invalid instruction
  21 vrintn.f32 d3, q12
  22 @ CHECK: error: invalid instruction, any one of the following would fix this:
  23 @ CHECK: note: operand must be a register in range [d0, d31]
  24 @ CHECK: note: operand must be a register in range [q0, q15]
  25 vrintz.f32 d3, q12
  26 @ CHECK: error: invalid instruction, any one of the following would fix this:
  27 @ CHECK: note: operand must be a register in range [d0, d31]
  28 @ CHECK: note: operand must be a register in range [q0, q15]
  29 vrintmge.f32.f32 d3, d4
  30 @ CHECK: error: instruction 'vrintm' is not predicable, but condition code specified
  31
  32 aesd.8  q0, s1
  33 @ CHECK: error: operand must be a register in range [q0, q15]
  34 aese.8  s0, q1
  35 @ CHECK: error: operand must be a register in range [q0, q15]
  36 aesimc.8  s0, q1
  37 @ CHECK: error: operand must be a register in range [q0, q15]
  38 aesmc.8  q0, d1
  39 @ CHECK: error: operand must be a register in range [q0, q15]
  40 aesdge.8 q0, q1
  41 @ CHECK: error: instruction 'aesd' is not predicable, but condition code specified
  42
  43 sha1h.32  d0, q1
  44 @ CHECK: error: operand must be a register in range [q0, q15]
  45 sha1su1.32  q0, s1
  46 @ CHECK: error: operand must be a register in range [q0, q15]
  47 sha256su0.32  s0, q1
  48 @ CHECK: error: operand must be a register in range [q0, q15]
  49 sha1heq.32  q0, q1
  50 @ CHECK: error: instruction 'sha1h' is not predicable, but condition code specified
  51
  52 sha1c.32  s0, d1, q2
  53 @ CHECK: error: invalid instruction
  54 sha1m.32  q0, s1, q2
  55 @ CHECK: error: operand must be a register in range [q0, q15]
  56 sha1p.32  s0, q1, q2
  57 @ CHECK: error: operand must be a register in range [q0, q15]
  58 sha1su0.32  d0, q1, q2
  59 @ CHECK: error: operand must be a register in range [q0, q15]
  60 sha256h.32  q0, s1, q2
  61 @ CHECK: error: operand must be a register in range [q0, q15]
  62 sha256h2.32  q0, q1, s2
  63 @ CHECK: error: operand must be a register in range [q0, q15]
  64 sha256su1.32  s0, d1, q2
  65 @ CHECK: error: invalid instruction
  66 sha256su1lt.32  q0, d1, q2
  67 @ CHECK: error: instruction 'sha256su1' is not predicable, but condition code specified
  68
  69 vmull.p64 q0, s1, s3
  70 @ CHECK: error: invalid instruction
  71 vmull.p64 s1, d2, d3
  72 @ CHECK: error: operand must be a register in range [q0, q15]
  73 vmullge.p64 q0, d16, d17
  74 @ CHECK: error: instruction 'vmull' is not predicable, but condition code specified
  75
  76 // These instructions are predicable in VFP but not in NEON
  77 vrintzeq.f32 d0, d1
  78 vrintxgt.f32 d0, d1
  79 @ CHECK: error: invalid operand for instruction
  80 @ CHECK: error: invalid operand for instruction