[llvm-readobj] - Simplify stack-sizes.test test case.
[llvm-complete.git] / test / MC / ARM / mve-scalar-shift.s
blob4d060ec3a7cebd02a1900d797ebf154c417c1378
1 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s 2>%t \
2 # RUN: | FileCheck --check-prefix=CHECK %s
3 # RUN: FileCheck --check-prefix=ERROR < %t %s
4 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding < %s 2>%t \
5 # RUN: | FileCheck --check-prefix=CHECK %s
6 # RUN: FileCheck --check-prefix=ERROR < %t %s
7 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -show-encoding < %s 2>%t \
8 # RUN: | FileCheck --check-prefix=CHECK-NOMVE %s
9 # RUN: FileCheck --check-prefix=ERROR-NOMVE < %t %s
11 # CHECK: asrl r0, r1, #23 @ encoding: [0x50,0xea,0xef,0x51]
12 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
13 asrl r0, r1, #23
15 # CHECK: asrl lr, r1, #27 @ encoding: [0x5e,0xea,0xef,0x61]
16 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
17 asrl lr, r1, #27
19 # CHECK: it eq @ encoding: [0x08,0xbf]
20 # CHECK-NEXT: asrleq lr, r1, #27 @ encoding: [0x5e,0xea,0xef,0x61]
21 it eq
22 asrleq lr, r1, #27
24 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid instruction
25 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
26 asrl r3, r2, #33
28 # ERROR: [[@LINE+3]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
29 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [r0, r12] or r14
30 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
31 asrl r0, r1, #33
33 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be an odd-numbered register in range [r1,r11]
34 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
35 asrl r0, r0, #32
37 # CHECK: asrl r0, r1, r4 @ encoding: [0x50,0xea,0x2d,0x41]
38 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
39 asrl r0, r1, r4
41 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be an odd-numbered register in range [r1,r11]
42 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
43 asrl r0, r0, r4
45 # The assembler will reject the above shifts when MVE is not supported,
46 # so the previous valid instruction will be IT EQ, so we need to add
47 # a NOPEQ:
48 nopeq
50 # CHECK: cinc lr, r2, lo @ encoding: [0x52,0xea,0x22,0x9e]
51 # CHECK-NOMVE: cinc lr, r2, lo @ encoding: [0x52,0xea,0x22,0x9e]
52 csinc lr, r2, r2, hs
54 # CHECK: cinc lr, r7, pl @ encoding: [0x57,0xea,0x47,0x9e]
55 # CHECK-NOMVE: cinc lr, r7, pl @ encoding: [0x57,0xea,0x47,0x9e]
56 cinc lr, r7, pl
58 # CHECK: cinv lr, r12, hs @ encoding: [0x5c,0xea,0x3c,0xae]
59 # CHECK-NOMVE: cinv lr, r12, hs @ encoding: [0x5c,0xea,0x3c,0xae]
60 cinv lr, r12, hs
62 # CHECK: cneg lr, r10, hs @ encoding: [0x5a,0xea,0x3a,0xbe]
63 # CHECK-NOMVE: cneg lr, r10, hs @ encoding: [0x5a,0xea,0x3a,0xbe]
64 csneg lr, r10, r10, lo
66 # CHECK: csel r9, r9, r11, vc @ encoding: [0x59,0xea,0x7b,0x89]
67 # CHECK-NOMVE: csel r9, r9, r11, vc @ encoding: [0x59,0xea,0x7b,0x89]
68 csel r9, r9, r11, vc
70 # CHECK: cset lr, eq @ encoding: [0x5f,0xea,0x1f,0x9e]
71 # CHECK-NOMVE: cset lr, eq @ encoding: [0x5f,0xea,0x1f,0x9e]
72 cset lr, eq
74 # CHECK: csetm lr, hs @ encoding: [0x5f,0xea,0x3f,0xae]
75 # CHECK-NOMVE: csetm lr, hs @ encoding: [0x5f,0xea,0x3f,0xae]
76 csetm lr, hs
78 # CHECK: csinc lr, r10, r7, le @ encoding: [0x5a,0xea,0xd7,0x9e]
79 # CHECK-NOMVE: csinc lr, r10, r7, le @ encoding: [0x5a,0xea,0xd7,0x9e]
80 csinc lr, r10, r7, le
82 # CHECK: csinv lr, r5, zr, hs @ encoding: [0x55,0xea,0x2f,0xae]
83 # CHECK-NOMVE: csinv lr, r5, zr, hs @ encoding: [0x55,0xea,0x2f,0xae]
84 csinv lr, r5, zr, hs
86 # CHECK: cinv lr, r2, pl @ encoding: [0x52,0xea,0x42,0xae]
87 # CHECK-NOMVE: cinv lr, r2, pl @ encoding: [0x52,0xea,0x42,0xae]
88 csinv lr, r2, r2, mi
90 # CHECK: csneg lr, r1, r11, vc @ encoding: [0x51,0xea,0x7b,0xbe]
91 # CHECK-NOMVE: csneg lr, r1, r11, vc @ encoding: [0x51,0xea,0x7b,0xbe]
92 csneg lr, r1, r11, vc
94 # CHECK: lsll lr, r1, #11 @ encoding: [0x5e,0xea,0xcf,0x21]
95 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
96 lsll lr, r1, #11
98 # CHECK: lsll lr, r1, r4 @ encoding: [0x5e,0xea,0x0d,0x41]
99 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
100 lsll lr, r1, r4
102 # CHECK: lsrl lr, r1, #12 @ encoding: [0x5e,0xea,0x1f,0x31]
103 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
104 lsrl lr, r1, #12
106 # CHECK: sqrshr lr, r12 @ encoding: [0x5e,0xea,0x2d,0xcf]
107 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
108 sqrshr lr, r12
110 # CHECK: sqrshr r11, r12 @ encoding: [0x5b,0xea,0x2d,0xcf]
111 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
112 sqrshr r11, r12
114 # CHECK: sqrshrl lr, r3, #64, r8 @ encoding: [0x5f,0xea,0x2d,0x83]
115 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
116 sqrshrl lr, r3, #64, r8
118 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: saturate operand must be 48 or 64
119 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
120 sqrshrl lr, r3, #32, r8
122 # CHECK: sqshl lr, #17 @ encoding: [0x5e,0xea,0x7f,0x4f]
123 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
124 sqshl lr, #17
126 # CHECK: sqshll lr, r11, #28 @ encoding: [0x5f,0xea,0x3f,0x7b]
127 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
128 sqshll lr, r11, #28
130 # CHECK: srshr lr, #11 @ encoding: [0x5e,0xea,0xef,0x2f]
131 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
132 srshr lr, #11
134 # CHECK: srshrl lr, r11, #23 @ encoding: [0x5f,0xea,0xef,0x5b]
135 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
136 srshrl lr, r11, #23
138 # CHECK: uqrshl lr, r1 @ encoding: [0x5e,0xea,0x0d,0x1f]
139 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
140 uqrshl lr, r1
142 # CHECK: uqrshll lr, r1, #48, r4 @ encoding: [0x5f,0xea,0x8d,0x41]
143 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
144 uqrshll lr, r1, #48, r4
146 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: saturate operand must be 48 or 64
147 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
148 uqrshll lr, r1, #0, r4
150 # CHECK: uqshl r0, #1 @ encoding: [0x50,0xea,0x4f,0x0f]
151 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
152 uqshl r0, #1
154 # CHECK: uqshll lr, r7, #7 @ encoding: [0x5f,0xea,0xcf,0x17]
155 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
156 uqshll lr, r7, #7
158 # CHECK: urshr r0, #10 @ encoding: [0x50,0xea,0x9f,0x2f]
159 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
160 urshr r0, #10
162 # CHECK: urshrl r0, r9, #29 @ encoding: [0x51,0xea,0x5f,0x79]
163 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
164 urshrl r0, r9, #29