lib/Target/TargetInstrInfo.cpp

   1 //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file was developed by the LLVM research group and is distributed under
   6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "llvm/Target/TargetInstrInfo.h"
  15 #include "llvm/CodeGen/MachineInstr.h"
  16 #include "llvm/Constant.h"
  17 #include "llvm/DerivedTypes.h"
  18 using namespace llvm;
  19
  20 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
  21 /// dest operand. Returns -1 if there isn't one.
  22 int TargetInstrDescriptor::findTiedToSrcOperand(unsigned OpNum) const {
  23   for (unsigned i = 0, e = numOperands; i != e; ++i) {
  24     if (i == OpNum)
  25       continue;
  26     if (getOperandConstraint(i, TOI::TIED_TO) == (int)OpNum)
  27       return i;
  28   }
  29   return -1;
  30 }
  31
  32
  33 TargetInstrInfo::TargetInstrInfo(const TargetInstrDescriptor* Desc,
  34                                  unsigned numOpcodes)
  35   : desc(Desc), NumOpcodes(numOpcodes) {
  36 }
  37
  38 TargetInstrInfo::~TargetInstrInfo() {
  39 }
  40
  41 // commuteInstruction - The default implementation of this method just exchanges
  42 // operand 1 and 2.
  43 MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI) const {
  44   assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
  45          "This only knows how to commute register operands so far");
  46   unsigned Reg1 = MI->getOperand(1).getReg();
  47   unsigned Reg2 = MI->getOperand(2).getReg();
  48   bool Reg1IsKill = MI->getOperand(1).isKill();
  49   bool Reg2IsKill = MI->getOperand(2).isKill();
  50   MI->getOperand(2).setReg(Reg1);
  51   MI->getOperand(1).setReg(Reg2);
  52   if (Reg1IsKill)
  53     MI->getOperand(2).setIsKill();
  54   else
  55     MI->getOperand(2).unsetIsKill();
  56   if (Reg2IsKill)
  57     MI->getOperand(1).setIsKill();
  58   else
  59     MI->getOperand(1).unsetIsKill();
  60   return MI;
  61 }
  62
  63 bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
  64                                 const std::vector<MachineOperand> &Pred) const {
  65   bool MadeChange = false;
  66   const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
  67   if (TID->Flags & M_PREDICABLE) {
  68     for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
  69       if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
  70         MachineOperand &MO = MI->getOperand(i);
  71         if (MO.isRegister()) {
  72           MO.setReg(Pred[j].getReg());
  73           MadeChange = true;
  74         } else if (MO.isImmediate()) {
  75           MO.setImm(Pred[j].getImmedValue());
  76           MadeChange = true;
  77         } else if (MO.isMachineBasicBlock()) {
  78           MO.setMachineBasicBlock(Pred[j].getMachineBasicBlock());
  79           MadeChange = true;
  80         }
  81         ++j;
  82       }
  83     }
  84   }
  85   return MadeChange;
  86 }
  87
  88 bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
  89   const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
  90   if (TID->Flags & M_TERMINATOR_FLAG) {
  91     // Conditional branch is a special case.
  92     if ((TID->Flags & M_BRANCH_FLAG) != 0 && (TID->Flags & M_BARRIER_FLAG) == 0)
  93       return true;
  94     if ((TID->Flags & M_PREDICABLE) == 0)
  95       return true;
  96     return !isPredicated(MI);
  97   }
  98   return false;
  99 }