lib/Target/X86/X86CodeEmitter.cpp

   1 //===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file was developed by the LLVM research group and is distributed under
   6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the pass that transforms the X86 machine instructions into
  11 // relocatable machine code.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #define DEBUG_TYPE "x86-emitter"
  16 #include "X86InstrInfo.h"
  17 #include "X86Subtarget.h"
  18 #include "X86TargetMachine.h"
  19 #include "X86Relocations.h"
  20 #include "X86.h"
  21 #include "llvm/PassManager.h"
  22 #include "llvm/CodeGen/MachineCodeEmitter.h"
  23 #include "llvm/CodeGen/MachineFunctionPass.h"
  24 #include "llvm/CodeGen/MachineInstr.h"
  25 #include "llvm/CodeGen/Passes.h"
  26 #include "llvm/Function.h"
  27 #include "llvm/ADT/Statistic.h"
  28 #include "llvm/Support/Compiler.h"
  29 #include "llvm/Target/TargetOptions.h"
  30 using namespace llvm;
  31
  32 STATISTIC(NumEmitted, "Number of machine instructions emitted");
  33
  34 namespace {
  35   class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
  36     const X86InstrInfo  *II;
  37     const TargetData    *TD;
  38     TargetMachine       &TM;
  39     MachineCodeEmitter  &MCE;
  40     bool Is64BitMode;
  41   public:
  42     static char ID;
  43     explicit Emitter(TargetMachine &tm, MachineCodeEmitter &mce)
  44       : MachineFunctionPass((intptr_t)&ID), II(0), TD(0), TM(tm),
  45       MCE(mce), Is64BitMode(false) {}
  46     Emitter(TargetMachine &tm, MachineCodeEmitter &mce,
  47             const X86InstrInfo &ii, const TargetData &td, bool is64)
  48       : MachineFunctionPass((intptr_t)&ID), II(&ii), TD(&td), TM(tm),
  49       MCE(mce), Is64BitMode(is64) {}
  50
  51     bool runOnMachineFunction(MachineFunction &MF);
  52
  53     virtual const char *getPassName() const {
  54       return "X86 Machine Code Emitter";
  55     }
  56
  57     void emitInstruction(const MachineInstr &MI);
  58
  59   private:
  60     void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
  61     void emitPCRelativeValue(intptr_t Address);
  62     void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);
  63     void emitGlobalAddressForPtr(GlobalValue *GV, unsigned Reloc,
  64                                  int Disp = 0, unsigned PCAdj = 0);
  65     void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
  66     void emitConstPoolAddress(unsigned CPI, unsigned Reloc, int Disp = 0,
  67                               unsigned PCAdj = 0);
  68     void emitJumpTableAddress(unsigned JTI, unsigned Reloc, unsigned PCAdj = 0);
  69
  70     void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
  71                                unsigned PCAdj = 0);
  72
  73     void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
  74     void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
  75     void emitConstant(uint64_t Val, unsigned Size);
  76
  77     void emitMemModRMByte(const MachineInstr &MI,
  78                           unsigned Op, unsigned RegOpcodeField,
  79                           unsigned PCAdj = 0);
  80
  81     unsigned getX86RegNum(unsigned RegNo);
  82     bool isX86_64ExtendedReg(const MachineOperand &MO);
  83     unsigned determineREX(const MachineInstr &MI);
  84   };
  85   char Emitter::ID = 0;
  86 }
  87
  88 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
  89 /// to the specified MCE object.
  90 FunctionPass *llvm::createX86CodeEmitterPass(X86TargetMachine &TM,
  91                                              MachineCodeEmitter &MCE) {
  92   return new Emitter(TM, MCE);
  93 }
  94
  95 bool Emitter::runOnMachineFunction(MachineFunction &MF) {
  96   assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
  97           MF.getTarget().getRelocationModel() != Reloc::Static) &&
  98          "JIT relocation model must be set to static or default!");
  99   II = ((X86TargetMachine&)MF.getTarget()).getInstrInfo();
 100   TD = ((X86TargetMachine&)MF.getTarget()).getTargetData();
 101   Is64BitMode =
 102     ((X86TargetMachine&)MF.getTarget()).getSubtarget<X86Subtarget>().is64Bit();
 103
 104   do {
 105     MCE.startFunction(MF);
 106     for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
 107          MBB != E; ++MBB) {
 108       MCE.StartMachineBasicBlock(MBB);
 109       for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
 110            I != E; ++I)
 111         emitInstruction(*I);
 112     }
 113   } while (MCE.finishFunction(MF));
 114
 115   return false;
 116 }
 117
 118 /// emitPCRelativeValue - Emit a PC relative address.
 119 ///
 120 void Emitter::emitPCRelativeValue(intptr_t Address) {
 121   MCE.emitWordLE(Address-MCE.getCurrentPCValue()-4);
 122 }
 123
 124 /// emitPCRelativeBlockAddress - This method keeps track of the information
 125 /// necessary to resolve the address of this block later and emits a dummy
 126 /// value.
 127 ///
 128 void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
 129   // Remember where this reference was and where it is to so we can
 130   // deal with it later.
 131   MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
 132                                              X86::reloc_pcrel_word, MBB));
 133   MCE.emitWordLE(0);
 134 }
 135
 136 /// emitGlobalAddressForCall - Emit the specified address to the code stream
 137 /// assuming this is part of a function call, which is PC relative.
 138 ///
 139 void Emitter::emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub) {
 140   MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
 141                                       X86::reloc_pcrel_word, GV, 0,
 142                                       DoesntNeedStub));
 143   MCE.emitWordLE(0);
 144 }
 145
 146 /// emitGlobalAddress - Emit the specified address to the code stream assuming
 147 /// this is part of a "take the address of a global" instruction.
 148 ///
 149 void Emitter::emitGlobalAddressForPtr(GlobalValue *GV, unsigned Reloc,
 150                                       int Disp /* = 0 */,
 151                                       unsigned PCAdj /* = 0 */) {
 152   MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
 153                                              GV, PCAdj));
 154   if (Reloc == X86::reloc_absolute_dword)
 155     MCE.emitWordLE(0);
 156   MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
 157 }
 158
 159 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
 160 /// be emitted to the current location in the function, and allow it to be PC
 161 /// relative.
 162 void Emitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
 163   MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
 164                                                  Reloc, ES));
 165   if (Reloc == X86::reloc_absolute_dword)
 166     MCE.emitWordLE(0);
 167   MCE.emitWordLE(0);
 168 }
 169
 170 /// emitConstPoolAddress - Arrange for the address of an constant pool
 171 /// to be emitted to the current location in the function, and allow it to be PC
 172 /// relative.
 173 void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
 174                                    int Disp /* = 0 */,
 175                                    unsigned PCAdj /* = 0 */) {
 176   MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
 177                                                     Reloc, CPI, PCAdj));
 178   if (Reloc == X86::reloc_absolute_dword)
 179     MCE.emitWordLE(0);
 180   MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
 181 }
 182
 183 /// emitJumpTableAddress - Arrange for the address of a jump table to
 184 /// be emitted to the current location in the function, and allow it to be PC
 185 /// relative.
 186 void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
 187                                    unsigned PCAdj /* = 0 */) {
 188   MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
 189                                                     Reloc, JTI, PCAdj));
 190   if (Reloc == X86::reloc_absolute_dword)
 191     MCE.emitWordLE(0);
 192   MCE.emitWordLE(0); // The relocated value will be added to the displacement
 193 }
 194
 195 unsigned Emitter::getX86RegNum(unsigned RegNo) {
 196   return ((X86RegisterInfo&)II->getRegisterInfo()).getX86RegNum(RegNo);
 197 }
 198
 199 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
 200                                       unsigned RM) {
 201   assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
 202   return RM | (RegOpcode << 3) | (Mod << 6);
 203 }
 204
 205 void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){
 206   MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
 207 }
 208
 209 void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
 210   // SIB byte is in the same format as the ModRMByte...
 211   MCE.emitByte(ModRMByte(SS, Index, Base));
 212 }
 213
 214 void Emitter::emitConstant(uint64_t Val, unsigned Size) {
 215   // Output the constant in little endian byte order...
 216   for (unsigned i = 0; i != Size; ++i) {
 217     MCE.emitByte(Val & 255);
 218     Val >>= 8;
 219   }
 220 }
 221
 222 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
 223 /// sign-extended field.
 224 static bool isDisp8(int Value) {
 225   return Value == (signed char)Value;
 226 }
 227
 228 void Emitter::emitDisplacementField(const MachineOperand *RelocOp,
 229                                     int DispVal, unsigned PCAdj) {
 230   // If this is a simple integer displacement that doesn't require a relocation,
 231   // emit it now.
 232   if (!RelocOp) {
 233     emitConstant(DispVal, 4);
 234     return;
 235   }
 236
 237   // Otherwise, this is something that requires a relocation.  Emit it as such
 238   // now.
 239   if (RelocOp->isGlobalAddress()) {
 240     // In 64-bit static small code model, we could potentially emit absolute.
 241     // But it's probably not beneficial.
 242     //  89 05 00 00 00 00       mov    %eax,0(%rip)  # PC-relative
 243     //  89 04 25 00 00 00 00    mov    %eax,0x0      # Absolute
 244     unsigned rt= Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_absolute_word;
 245     emitGlobalAddressForPtr(RelocOp->getGlobal(), rt,
 246                             RelocOp->getOffset(), PCAdj);
 247   } else if (RelocOp->isConstantPoolIndex()) {
 248     // Must be in 64-bit mode.
 249     emitConstPoolAddress(RelocOp->getConstantPoolIndex(), X86::reloc_pcrel_word,
 250                          RelocOp->getOffset(), PCAdj);
 251   } else if (RelocOp->isJumpTableIndex()) {
 252     // Must be in 64-bit mode.
 253     emitJumpTableAddress(RelocOp->getJumpTableIndex(), X86::reloc_pcrel_word,
 254                          PCAdj);
 255   } else {
 256     assert(0 && "Unknown value to relocate!");
 257   }
 258 }
 259
 260 void Emitter::emitMemModRMByte(const MachineInstr &MI,
 261                                unsigned Op, unsigned RegOpcodeField,
 262                                unsigned PCAdj) {
 263   const MachineOperand &Op3 = MI.getOperand(Op+3);
 264   int DispVal = 0;
 265   const MachineOperand *DispForReloc = 0;
 266
 267   // Figure out what sort of displacement we have to handle here.
 268   if (Op3.isGlobalAddress()) {
 269     DispForReloc = &Op3;
 270   } else if (Op3.isConstantPoolIndex()) {
 271     if (Is64BitMode) {
 272       DispForReloc = &Op3;
 273     } else {
 274       DispVal += MCE.getConstantPoolEntryAddress(Op3.getConstantPoolIndex());
 275       DispVal += Op3.getOffset();
 276     }
 277   } else if (Op3.isJumpTableIndex()) {
 278     if (Is64BitMode) {
 279       DispForReloc = &Op3;
 280     } else {
 281       DispVal += MCE.getJumpTableEntryAddress(Op3.getJumpTableIndex());
 282     }
 283   } else {
 284     DispVal = Op3.getImm();
 285   }
 286
 287   const MachineOperand &Base     = MI.getOperand(Op);
 288   const MachineOperand &Scale    = MI.getOperand(Op+1);
 289   const MachineOperand &IndexReg = MI.getOperand(Op+2);
 290
 291   unsigned BaseReg = Base.getReg();
 292
 293   // Is a SIB byte needed?
 294   if (IndexReg.getReg() == 0 &&
 295       (BaseReg == 0 || getX86RegNum(BaseReg) != N86::ESP)) {
 296     if (BaseReg == 0) {  // Just a displacement?
 297       // Emit special case [disp32] encoding
 298       MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
 299
 300       emitDisplacementField(DispForReloc, DispVal, PCAdj);
 301     } else {
 302       unsigned BaseRegNo = getX86RegNum(BaseReg);
 303       if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
 304         // Emit simple indirect register encoding... [EAX] f.e.
 305         MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
 306       } else if (!DispForReloc && isDisp8(DispVal)) {
 307         // Emit the disp8 encoding... [REG+disp8]
 308         MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
 309         emitConstant(DispVal, 1);
 310       } else {
 311         // Emit the most general non-SIB encoding: [REG+disp32]
 312         MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
 313         emitDisplacementField(DispForReloc, DispVal, PCAdj);
 314       }
 315     }
 316
 317   } else {  // We need a SIB byte, so start by outputting the ModR/M byte first
 318     assert(IndexReg.getReg() != X86::ESP &&
 319            IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
 320
 321     bool ForceDisp32 = false;
 322     bool ForceDisp8  = false;
 323     if (BaseReg == 0) {
 324       // If there is no base register, we emit the special case SIB byte with
 325       // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
 326       MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
 327       ForceDisp32 = true;
 328     } else if (DispForReloc) {
 329       // Emit the normal disp32 encoding.
 330       MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
 331       ForceDisp32 = true;
 332     } else if (DispVal == 0 && getX86RegNum(BaseReg) != N86::EBP) {
 333       // Emit no displacement ModR/M byte
 334       MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
 335     } else if (isDisp8(DispVal)) {
 336       // Emit the disp8 encoding...
 337       MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
 338       ForceDisp8 = true;           // Make sure to force 8 bit disp if Base=EBP
 339     } else {
 340       // Emit the normal disp32 encoding...
 341       MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
 342     }
 343
 344     // Calculate what the SS field value should be...
 345     static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
 346     unsigned SS = SSTable[Scale.getImm()];
 347
 348     if (BaseReg == 0) {
 349       // Handle the SIB byte for the case where there is no base.  The
 350       // displacement has already been output.
 351       assert(IndexReg.getReg() && "Index register must be specified!");
 352       emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5);
 353     } else {
 354       unsigned BaseRegNo = getX86RegNum(BaseReg);
 355       unsigned IndexRegNo;
 356       if (IndexReg.getReg())
 357         IndexRegNo = getX86RegNum(IndexReg.getReg());
 358       else
 359         IndexRegNo = 4;   // For example [ESP+1*<noreg>+4]
 360       emitSIBByte(SS, IndexRegNo, BaseRegNo);
 361     }
 362
 363     // Do we need to output a displacement?
 364     if (ForceDisp8) {
 365       emitConstant(DispVal, 1);
 366     } else if (DispVal != 0 || ForceDisp32) {
 367       emitDisplacementField(DispForReloc, DispVal, PCAdj);
 368     }
 369   }
 370 }
 371
 372 static unsigned sizeOfImm(const TargetInstrDescriptor *Desc) {
 373   switch (Desc->TSFlags & X86II::ImmMask) {
 374   case X86II::Imm8:   return 1;
 375   case X86II::Imm16:  return 2;
 376   case X86II::Imm32:  return 4;
 377   case X86II::Imm64:  return 8;
 378   default: assert(0 && "Immediate size not set!");
 379     return 0;
 380   }
 381 }
 382
 383 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
 384 /// e.g. r8, xmm8, etc.
 385 bool Emitter::isX86_64ExtendedReg(const MachineOperand &MO) {
 386   if (!MO.isRegister()) return false;
 387   switch (MO.getReg()) {
 388   default: break;
 389   case X86::R8:    case X86::R9:    case X86::R10:   case X86::R11:
 390   case X86::R12:   case X86::R13:   case X86::R14:   case X86::R15:
 391   case X86::R8D:   case X86::R9D:   case X86::R10D:  case X86::R11D:
 392   case X86::R12D:  case X86::R13D:  case X86::R14D:  case X86::R15D:
 393   case X86::R8W:   case X86::R9W:   case X86::R10W:  case X86::R11W:
 394   case X86::R12W:  case X86::R13W:  case X86::R14W:  case X86::R15W:
 395   case X86::R8B:   case X86::R9B:   case X86::R10B:  case X86::R11B:
 396   case X86::R12B:  case X86::R13B:  case X86::R14B:  case X86::R15B:
 397   case X86::XMM8:  case X86::XMM9:  case X86::XMM10: case X86::XMM11:
 398   case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
 399     return true;
 400   }
 401   return false;
 402 }
 403
 404 inline static bool isX86_64NonExtLowByteReg(unsigned reg) {
 405   return (reg == X86::SPL || reg == X86::BPL ||
 406           reg == X86::SIL || reg == X86::DIL);
 407 }
 408
 409 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
 410 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
 411 /// size, and 3) use of X86-64 extended registers.
 412 unsigned Emitter::determineREX(const MachineInstr &MI) {
 413   unsigned REX = 0;
 414   const TargetInstrDescriptor *Desc = MI.getInstrDescriptor();
 415
 416   // Pseudo instructions do not need REX prefix byte.
 417   if ((Desc->TSFlags & X86II::FormMask) == X86II::Pseudo)
 418     return 0;
 419   if (Desc->TSFlags & X86II::REX_W)
 420     REX |= 1 << 3;
 421
 422   unsigned NumOps = Desc->numOperands;
 423   if (NumOps) {
 424     bool isTwoAddr = NumOps > 1 &&
 425       Desc->getOperandConstraint(1, TOI::TIED_TO) != -1;
 426
 427     // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
 428     unsigned i = isTwoAddr ? 1 : 0;
 429     for (unsigned e = NumOps; i != e; ++i) {
 430       const MachineOperand& MO = MI.getOperand(i);
 431       if (MO.isRegister()) {
 432         unsigned Reg = MO.getReg();
 433         if (isX86_64NonExtLowByteReg(Reg))
 434           REX |= 0x40;
 435       }
 436     }
 437
 438     switch (Desc->TSFlags & X86II::FormMask) {
 439     case X86II::MRMInitReg:
 440       if (isX86_64ExtendedReg(MI.getOperand(0)))
 441         REX |= (1 << 0) | (1 << 2);
 442       break;
 443     case X86II::MRMSrcReg: {
 444       if (isX86_64ExtendedReg(MI.getOperand(0)))
 445         REX |= 1 << 2;
 446       i = isTwoAddr ? 2 : 1;
 447       for (unsigned e = NumOps; i != e; ++i) {
 448         const MachineOperand& MO = MI.getOperand(i);
 449         if (isX86_64ExtendedReg(MO))
 450           REX |= 1 << 0;
 451       }
 452       break;
 453     }
 454     case X86II::MRMSrcMem: {
 455       if (isX86_64ExtendedReg(MI.getOperand(0)))
 456         REX |= 1 << 2;
 457       unsigned Bit = 0;
 458       i = isTwoAddr ? 2 : 1;
 459       for (; i != NumOps; ++i) {
 460         const MachineOperand& MO = MI.getOperand(i);
 461         if (MO.isRegister()) {
 462           if (isX86_64ExtendedReg(MO))
 463             REX |= 1 << Bit;
 464           Bit++;
 465         }
 466       }
 467       break;
 468     }
 469     case X86II::MRM0m: case X86II::MRM1m:
 470     case X86II::MRM2m: case X86II::MRM3m:
 471     case X86II::MRM4m: case X86II::MRM5m:
 472     case X86II::MRM6m: case X86II::MRM7m:
 473     case X86II::MRMDestMem: {
 474       unsigned e = isTwoAddr ? 5 : 4;
 475       i = isTwoAddr ? 1 : 0;
 476       if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
 477         REX |= 1 << 2;
 478       unsigned Bit = 0;
 479       for (; i != e; ++i) {
 480         const MachineOperand& MO = MI.getOperand(i);
 481         if (MO.isRegister()) {
 482           if (isX86_64ExtendedReg(MO))
 483             REX |= 1 << Bit;
 484           Bit++;
 485         }
 486       }
 487       break;
 488     }
 489     default: {
 490       if (isX86_64ExtendedReg(MI.getOperand(0)))
 491         REX |= 1 << 0;
 492       i = isTwoAddr ? 2 : 1;
 493       for (unsigned e = NumOps; i != e; ++i) {
 494         const MachineOperand& MO = MI.getOperand(i);
 495         if (isX86_64ExtendedReg(MO))
 496           REX |= 1 << 2;
 497       }
 498       break;
 499     }
 500     }
 501   }
 502   return REX;
 503 }
 504
 505 void Emitter::emitInstruction(const MachineInstr &MI) {
 506   NumEmitted++;  // Keep track of the # of mi's emitted
 507
 508   const TargetInstrDescriptor *Desc = MI.getInstrDescriptor();
 509   unsigned Opcode = Desc->Opcode;
 510
 511   // Emit the repeat opcode prefix as needed.
 512   if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
 513
 514   // Emit the operand size opcode prefix as needed.
 515   if (Desc->TSFlags & X86II::OpSize) MCE.emitByte(0x66);
 516
 517   // Emit the address size opcode prefix as needed.
 518   if (Desc->TSFlags & X86II::AdSize) MCE.emitByte(0x67);
 519
 520   bool Need0FPrefix = false;
 521   switch (Desc->TSFlags & X86II::Op0Mask) {
 522   case X86II::TB:
 523     Need0FPrefix = true;   // Two-byte opcode prefix
 524     break;
 525   case X86II::T8:
 526     MCE.emitByte(0x0F);
 527     MCE.emitByte(0x38);
 528     break;
 529   case X86II::TA:
 530     MCE.emitByte(0x0F);
 531     MCE.emitByte(0x3A);
 532     break;
 533   case X86II::REP: break; // already handled.
 534   case X86II::XS:   // F3 0F
 535     MCE.emitByte(0xF3);
 536     Need0FPrefix = true;
 537     break;
 538   case X86II::XD:   // F2 0F
 539     MCE.emitByte(0xF2);
 540     Need0FPrefix = true;
 541     break;
 542   case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
 543   case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
 544     MCE.emitByte(0xD8+
 545                  (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
 546                                    >> X86II::Op0Shift));
 547     break; // Two-byte opcode prefix
 548   default: assert(0 && "Invalid prefix!");
 549   case 0: break;  // No prefix!
 550   }
 551
 552   if (Is64BitMode) {
 553     // REX prefix
 554     unsigned REX = determineREX(MI);
 555     if (REX)
 556       MCE.emitByte(0x40 | REX);
 557   }
 558
 559   // 0x0F escape code must be emitted just before the opcode.
 560   if (Need0FPrefix)
 561     MCE.emitByte(0x0F);
 562
 563   // If this is a two-address instruction, skip one of the register operands.
 564   unsigned NumOps = Desc->numOperands;
 565   unsigned CurOp = 0;
 566   if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
 567     CurOp++;
 568
 569   unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc);
 570   switch (Desc->TSFlags & X86II::FormMask) {
 571   default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
 572   case X86II::Pseudo:
 573 #ifndef NDEBUG
 574     switch (Opcode) {
 575     default:
 576       assert(0 && "psuedo instructions should be removed before code emission");
 577     case TargetInstrInfo::INLINEASM:
 578       assert(0 && "JIT does not support inline asm!\n");
 579     case TargetInstrInfo::LABEL:
 580       assert(0 && "JIT does not support meta labels!\n");
 581     case X86::IMPLICIT_USE:
 582     case X86::IMPLICIT_DEF:
 583     case X86::IMPLICIT_DEF_GR8:
 584     case X86::IMPLICIT_DEF_GR16:
 585     case X86::IMPLICIT_DEF_GR32:
 586     case X86::IMPLICIT_DEF_GR64:
 587     case X86::IMPLICIT_DEF_FR32:
 588     case X86::IMPLICIT_DEF_FR64:
 589     case X86::IMPLICIT_DEF_VR64:
 590     case X86::IMPLICIT_DEF_VR128:
 591     case X86::FP_REG_KILL:
 592       break;
 593     }
 594 #endif
 595     CurOp = NumOps;
 596     break;
 597
 598   case X86II::RawFrm:
 599     MCE.emitByte(BaseOpcode);
 600     if (CurOp != NumOps) {
 601       const MachineOperand &MO = MI.getOperand(CurOp++);
 602       if (MO.isMachineBasicBlock()) {
 603         emitPCRelativeBlockAddress(MO.getMachineBasicBlock());
 604       } else if (MO.isGlobalAddress()) {
 605         bool NeedStub = Is64BitMode ||
 606                         Opcode == X86::TAILJMPd ||
 607                         Opcode == X86::TAILJMPr || Opcode == X86::TAILJMPm;
 608         emitGlobalAddressForCall(MO.getGlobal(), !NeedStub);
 609       } else if (MO.isExternalSymbol()) {
 610         emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
 611       } else if (MO.isImmediate()) {
 612         emitConstant(MO.getImm(), sizeOfImm(Desc));
 613       } else {
 614         assert(0 && "Unknown RawFrm operand!");
 615       }
 616     }
 617     break;
 618
 619   case X86II::AddRegFrm:
 620     MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
 621
 622     if (CurOp != NumOps) {
 623       const MachineOperand &MO1 = MI.getOperand(CurOp++);
 624       unsigned Size = sizeOfImm(Desc);
 625       if (MO1.isImmediate())
 626         emitConstant(MO1.getImm(), Size);
 627       else {
 628         unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_absolute_word;
 629         if (Opcode == X86::MOV64ri)
 630           rt = X86::reloc_absolute_dword;  // FIXME: add X86II flag?
 631         if (MO1.isGlobalAddress())
 632           emitGlobalAddressForPtr(MO1.getGlobal(), rt, MO1.getOffset());
 633         else if (MO1.isExternalSymbol())
 634           emitExternalSymbolAddress(MO1.getSymbolName(), rt);
 635         else if (MO1.isConstantPoolIndex())
 636           emitConstPoolAddress(MO1.getConstantPoolIndex(), rt);
 637         else if (MO1.isJumpTableIndex())
 638           emitJumpTableAddress(MO1.getJumpTableIndex(), rt);
 639       }
 640     }
 641     break;
 642
 643   case X86II::MRMDestReg: {
 644     MCE.emitByte(BaseOpcode);
 645     emitRegModRMByte(MI.getOperand(CurOp).getReg(),
 646                      getX86RegNum(MI.getOperand(CurOp+1).getReg()));
 647     CurOp += 2;
 648     if (CurOp != NumOps)
 649       emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
 650     break;
 651   }
 652   case X86II::MRMDestMem: {
 653     MCE.emitByte(BaseOpcode);
 654     emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(CurOp+4).getReg()));
 655     CurOp += 5;
 656     if (CurOp != NumOps)
 657       emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
 658     break;
 659   }
 660
 661   case X86II::MRMSrcReg:
 662     MCE.emitByte(BaseOpcode);
 663     emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
 664                      getX86RegNum(MI.getOperand(CurOp).getReg()));
 665     CurOp += 2;
 666     if (CurOp != NumOps)
 667       emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
 668     break;
 669
 670   case X86II::MRMSrcMem: {
 671     unsigned PCAdj = (CurOp+5 != NumOps) ? sizeOfImm(Desc) : 0;
 672
 673     MCE.emitByte(BaseOpcode);
 674     emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
 675                      PCAdj);
 676     CurOp += 5;
 677     if (CurOp != NumOps)
 678       emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
 679     break;
 680   }
 681
 682   case X86II::MRM0r: case X86II::MRM1r:
 683   case X86II::MRM2r: case X86II::MRM3r:
 684   case X86II::MRM4r: case X86II::MRM5r:
 685   case X86II::MRM6r: case X86II::MRM7r:
 686     MCE.emitByte(BaseOpcode);
 687     emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
 688                      (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
 689
 690     if (CurOp != NumOps) {
 691       const MachineOperand &MO1 = MI.getOperand(CurOp++);
 692       unsigned Size = sizeOfImm(Desc);
 693       if (MO1.isImmediate())
 694         emitConstant(MO1.getImm(), Size);
 695       else {
 696         unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
 697           : X86::reloc_absolute_word;
 698         if (Opcode == X86::MOV64ri32)
 699           rt = X86::reloc_absolute_word;  // FIXME: add X86II flag?
 700         if (MO1.isGlobalAddress())
 701           emitGlobalAddressForPtr(MO1.getGlobal(), rt, MO1.getOffset());
 702         else if (MO1.isExternalSymbol())
 703           emitExternalSymbolAddress(MO1.getSymbolName(), rt);
 704         else if (MO1.isConstantPoolIndex())
 705           emitConstPoolAddress(MO1.getConstantPoolIndex(), rt);
 706         else if (MO1.isJumpTableIndex())
 707           emitJumpTableAddress(MO1.getJumpTableIndex(), rt);
 708       }
 709     }
 710     break;
 711
 712   case X86II::MRM0m: case X86II::MRM1m:
 713   case X86II::MRM2m: case X86II::MRM3m:
 714   case X86II::MRM4m: case X86II::MRM5m:
 715   case X86II::MRM6m: case X86II::MRM7m: {
 716     unsigned PCAdj = (CurOp+4 != NumOps) ?
 717       (MI.getOperand(CurOp+4).isImmediate() ? sizeOfImm(Desc) : 4) : 0;
 718
 719     MCE.emitByte(BaseOpcode);
 720     emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
 721                      PCAdj);
 722     CurOp += 4;
 723
 724     if (CurOp != NumOps) {
 725       const MachineOperand &MO = MI.getOperand(CurOp++);
 726       unsigned Size = sizeOfImm(Desc);
 727       if (MO.isImmediate())
 728         emitConstant(MO.getImm(), Size);
 729       else {
 730         unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
 731           : X86::reloc_absolute_word;
 732         if (Opcode == X86::MOV64mi32)
 733           rt = X86::reloc_absolute_word;  // FIXME: add X86II flag?
 734         if (MO.isGlobalAddress())
 735           emitGlobalAddressForPtr(MO.getGlobal(), rt, MO.getOffset());
 736         else if (MO.isExternalSymbol())
 737           emitExternalSymbolAddress(MO.getSymbolName(), rt);
 738         else if (MO.isConstantPoolIndex())
 739           emitConstPoolAddress(MO.getConstantPoolIndex(), rt);
 740         else if (MO.isJumpTableIndex())
 741           emitJumpTableAddress(MO.getJumpTableIndex(), rt);
 742       }
 743     }
 744     break;
 745   }
 746
 747   case X86II::MRMInitReg:
 748     MCE.emitByte(BaseOpcode);
 749     // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
 750     emitRegModRMByte(MI.getOperand(CurOp).getReg(),
 751                      getX86RegNum(MI.getOperand(CurOp).getReg()));
 752     ++CurOp;
 753     break;
 754   }
 755
 756   assert((Desc->Flags & M_VARIABLE_OPS) != 0 ||
 757          CurOp == NumOps && "Unknown encoding!");
 758 }