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Inliner pass header file was moved.
[llvm-complete.git] / lib / Target / ARM / ARMISelLowering.cpp
blob0f82ce5f457064d5e6c25f4009c11c4d7f71b4e2
1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file was developed by Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "ARM.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Instruction.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/SSARegMap.h"
32 #include "llvm/Target/TargetOptions.h"
33 #include "llvm/ADT/VectorExtras.h"
34 #include "llvm/Support/MathExtras.h"
35 using namespace llvm;
36
37 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
38 : TargetLowering(TM), ARMPCLabelIndex(0) {
39 Subtarget = &TM.getSubtarget<ARMSubtarget>();
40
41 if (Subtarget->isTargetDarwin()) {
42 // Don't have these.
43 setLibcallName(RTLIB::UINTTOFP_I64_F32, NULL);
44 setLibcallName(RTLIB::UINTTOFP_I64_F64, NULL);
45
46 // Uses VFP for Thumb libfuncs if available.
47 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
48 // Single-precision floating-point arithmetic.
49 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
50 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
51 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
52 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
53
54 // Double-precision floating-point arithmetic.
55 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
56 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
57 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
58 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
59
60 // Single-precision comparisons.
61 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
62 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
63 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
64 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
65 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
66 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
67 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
68 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
69
70 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
71 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
72 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
73 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
74 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
75 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
76 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
77 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
78
79 // Double-precision comparisons.
80 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
81 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
82 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
83 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
84 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
85 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
86 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
87 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
88
89 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
90 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
91 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
92 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
93 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
94 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
95 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
96 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
97
98 // Floating-point to integer conversions.
99 // i64 conversions are done via library routines even when generating VFP
100 // instructions, so use the same ones.
101 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
102 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
103 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
104 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
105
106 // Conversions between floating types.
107 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
108 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
109
110 // Integer to floating-point conversions.
111 // i64 conversions are done via library routines even when generating VFP
112 // instructions, so use the same ones.
113 // FIXME: There appears to be some naming inconsistency in ARM libgcc: e.g.
114 // __floatunsidf vs. __floatunssidfvfp.
115 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
116 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
117 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
118 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
119 }
120 }
121
122 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
123 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
124 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
125 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
126 }
127 computeRegisterProperties();
128
129 // ARM does not have f32 extending load.
130 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
131
132 // ARM supports all 4 flavors of integer indexed load / store.
133 for (unsigned im = (unsigned)ISD::PRE_INC;
134 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
135 setIndexedLoadAction(im, MVT::i1, Legal);
136 setIndexedLoadAction(im, MVT::i8, Legal);
137 setIndexedLoadAction(im, MVT::i16, Legal);
138 setIndexedLoadAction(im, MVT::i32, Legal);
139 setIndexedStoreAction(im, MVT::i1, Legal);
140 setIndexedStoreAction(im, MVT::i8, Legal);
141 setIndexedStoreAction(im, MVT::i16, Legal);
142 setIndexedStoreAction(im, MVT::i32, Legal);
143 }
144
145 // i64 operation support.
146 if (Subtarget->isThumb()) {
147 setOperationAction(ISD::MUL, MVT::i64, Expand);
148 setOperationAction(ISD::MULHU, MVT::i32, Expand);
149 setOperationAction(ISD::MULHS, MVT::i32, Expand);
150 } else {
151 setOperationAction(ISD::MUL, MVT::i64, Custom);
152 setOperationAction(ISD::MULHU, MVT::i32, Custom);
153 if (!Subtarget->hasV6Ops())
154 setOperationAction(ISD::MULHS, MVT::i32, Custom);
155 }
156 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
157 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
158 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
159 setOperationAction(ISD::SRL, MVT::i64, Custom);
160 setOperationAction(ISD::SRA, MVT::i64, Custom);
161
162 // ARM does not have ROTL.
163 setOperationAction(ISD::ROTL, MVT::i32, Expand);
164 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
165 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
166 if (!Subtarget->hasV5TOps() || Subtarget->isThumb())
167 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
168
169 // Only ARMv6 has BSWAP.
170 if (!Subtarget->hasV6Ops())
171 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
172
173 // These are expanded into libcalls.
174 setOperationAction(ISD::SDIV, MVT::i32, Expand);
175 setOperationAction(ISD::UDIV, MVT::i32, Expand);
176 setOperationAction(ISD::SREM, MVT::i32, Expand);
177 setOperationAction(ISD::UREM, MVT::i32, Expand);
178
179 // Support label based line numbers.
180 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
181 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
182
183 setOperationAction(ISD::RET, MVT::Other, Custom);
184 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
185 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
186 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
187 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
188
189 // Expand mem operations genericly.
190 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
191 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
192 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
193
194 // Use the default implementation.
195 setOperationAction(ISD::VASTART , MVT::Other, Expand);
196 setOperationAction(ISD::VAARG , MVT::Other, Expand);
197 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
198 setOperationAction(ISD::VAEND , MVT::Other, Expand);
199 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
200 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
201 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
202
203 if (!Subtarget->hasV6Ops()) {
204 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
205 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
206 }
207 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
208
209 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb())
210 // Turn f64->i64 into FMRRD iff target supports vfp2.
211 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
212
213 setOperationAction(ISD::SETCC , MVT::i32, Expand);
214 setOperationAction(ISD::SETCC , MVT::f32, Expand);
215 setOperationAction(ISD::SETCC , MVT::f64, Expand);
216 setOperationAction(ISD::SELECT , MVT::i32, Expand);
217 setOperationAction(ISD::SELECT , MVT::f32, Expand);
218 setOperationAction(ISD::SELECT , MVT::f64, Expand);
219 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
220 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
221 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
222
223 setOperationAction(ISD::BRCOND , MVT::Other, Expand);
224 setOperationAction(ISD::BR_CC , MVT::i32, Custom);
225 setOperationAction(ISD::BR_CC , MVT::f32, Custom);
226 setOperationAction(ISD::BR_CC , MVT::f64, Custom);
227 setOperationAction(ISD::BR_JT , MVT::Other, Custom);
228
229 setOperationAction(ISD::VASTART, MVT::Other, Custom);
230 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
231 setOperationAction(ISD::VAEND, MVT::Other, Expand);
232 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
233 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
234
235 // FP Constants can't be immediates.
236 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
237 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
238
239 // We don't support sin/cos/fmod/copysign
240 setOperationAction(ISD::FSIN , MVT::f64, Expand);
241 setOperationAction(ISD::FSIN , MVT::f32, Expand);
242 setOperationAction(ISD::FCOS , MVT::f32, Expand);
243 setOperationAction(ISD::FCOS , MVT::f64, Expand);
244 setOperationAction(ISD::FREM , MVT::f64, Expand);
245 setOperationAction(ISD::FREM , MVT::f32, Expand);
246 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
247 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
248
249 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
250 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
251 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
252 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
253 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
254
255 setStackPointerRegisterToSaveRestore(ARM::SP);
256 setSchedulingPreference(SchedulingForRegPressure);
257 setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
258 setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 3);
259
260 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
261 }
262
263
264 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
265 switch (Opcode) {
266 default: return 0;
267 case ARMISD::Wrapper: return "ARMISD::Wrapper";
268 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
269 case ARMISD::CALL: return "ARMISD::CALL";
270 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
271 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
272 case ARMISD::tCALL: return "ARMISD::tCALL";
273 case ARMISD::BRCOND: return "ARMISD::BRCOND";
274 case ARMISD::BR_JT: return "ARMISD::BR_JT";
275 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
276 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
277 case ARMISD::CMP: return "ARMISD::CMP";
278 case ARMISD::CMPNZ: return "ARMISD::CMPNZ";
279 case ARMISD::CMPFP: return "ARMISD::CMPFP";
280 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
281 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
282 case ARMISD::CMOV: return "ARMISD::CMOV";
283 case ARMISD::CNEG: return "ARMISD::CNEG";
284
285 case ARMISD::FTOSI: return "ARMISD::FTOSI";
286 case ARMISD::FTOUI: return "ARMISD::FTOUI";
287 case ARMISD::SITOF: return "ARMISD::SITOF";
288 case ARMISD::UITOF: return "ARMISD::UITOF";
289 case ARMISD::MULHILOU: return "ARMISD::MULHILOU";
290 case ARMISD::MULHILOS: return "ARMISD::MULHILOS";
291
292 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
293 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
294 case ARMISD::RRX: return "ARMISD::RRX";
295
296 case ARMISD::FMRRD: return "ARMISD::FMRRD";
297 case ARMISD::FMDRR: return "ARMISD::FMDRR";
298
299 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
300 }
301 }
302
303 //===----------------------------------------------------------------------===//
304 // Lowering Code
305 //===----------------------------------------------------------------------===//
306
307
308 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
309 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
310 switch (CC) {
311 default: assert(0 && "Unknown condition code!");
312 case ISD::SETNE: return ARMCC::NE;
313 case ISD::SETEQ: return ARMCC::EQ;
314 case ISD::SETGT: return ARMCC::GT;
315 case ISD::SETGE: return ARMCC::GE;
316 case ISD::SETLT: return ARMCC::LT;
317 case ISD::SETLE: return ARMCC::LE;
318 case ISD::SETUGT: return ARMCC::HI;
319 case ISD::SETUGE: return ARMCC::HS;
320 case ISD::SETULT: return ARMCC::LO;
321 case ISD::SETULE: return ARMCC::LS;
322 }
323 }
324
325 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
326 /// returns true if the operands should be inverted to form the proper
327 /// comparison.
328 static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
329 ARMCC::CondCodes &CondCode2) {
330 bool Invert = false;
331 CondCode2 = ARMCC::AL;
332 switch (CC) {
333 default: assert(0 && "Unknown FP condition!");
334 case ISD::SETEQ:
335 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
336 case ISD::SETGT:
337 case ISD::SETOGT: CondCode = ARMCC::GT; break;
338 case ISD::SETGE:
339 case ISD::SETOGE: CondCode = ARMCC::GE; break;
340 case ISD::SETOLT: CondCode = ARMCC::MI; break;
341 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
342 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
343 case ISD::SETO: CondCode = ARMCC::VC; break;
344 case ISD::SETUO: CondCode = ARMCC::VS; break;
345 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
346 case ISD::SETUGT: CondCode = ARMCC::HI; break;
347 case ISD::SETUGE: CondCode = ARMCC::PL; break;
348 case ISD::SETLT:
349 case ISD::SETULT: CondCode = ARMCC::LT; break;
350 case ISD::SETLE:
351 case ISD::SETULE: CondCode = ARMCC::LE; break;
352 case ISD::SETNE:
353 case ISD::SETUNE: CondCode = ARMCC::NE; break;
354 }
355 return Invert;
356 }
357
358 static void
359 HowToPassArgument(MVT::ValueType ObjectVT, unsigned NumGPRs,
360 unsigned StackOffset, unsigned &NeededGPRs,
361 unsigned &NeededStackSize, unsigned &GPRPad,
362 unsigned &StackPad, unsigned Flags) {
363 NeededStackSize = 0;
364 NeededGPRs = 0;
365 StackPad = 0;
366 GPRPad = 0;
367 unsigned align = (Flags >> ISD::ParamFlags::OrigAlignmentOffs);
368 GPRPad = NumGPRs % ((align + 3)/4);
369 StackPad = StackOffset % align;
370 unsigned firstGPR = NumGPRs + GPRPad;
371 switch (ObjectVT) {
372 default: assert(0 && "Unhandled argument type!");
373 case MVT::i32:
374 case MVT::f32:
375 if (firstGPR < 4)
376 NeededGPRs = 1;
377 else
378 NeededStackSize = 4;
379 break;
380 case MVT::i64:
381 case MVT::f64:
382 if (firstGPR < 3)
383 NeededGPRs = 2;
384 else if (firstGPR == 3) {
385 NeededGPRs = 1;
386 NeededStackSize = 4;
387 } else
388 NeededStackSize = 8;
389 }
390 }
391
392 /// LowerCALL - Lowering a ISD::CALL node into a callseq_start <-
393 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
394 /// nodes.
395 SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
396 MVT::ValueType RetVT= Op.Val->getValueType(0);
397 SDOperand Chain = Op.getOperand(0);
398 unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
399 assert((CallConv == CallingConv::C ||
400 CallConv == CallingConv::Fast) && "unknown calling convention");
401 SDOperand Callee = Op.getOperand(4);
402 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
403 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
404 unsigned NumGPRs = 0; // GPRs used for parameter passing.
405
406 // Count how many bytes are to be pushed on the stack.
407 unsigned NumBytes = 0;
408
409 // Add up all the space actually used.
410 for (unsigned i = 0; i < NumOps; ++i) {
411 unsigned ObjSize;
412 unsigned ObjGPRs;
413 unsigned StackPad;
414 unsigned GPRPad;
415 MVT::ValueType ObjectVT = Op.getOperand(5+2*i).getValueType();
416 unsigned Flags = Op.getConstantOperandVal(5+2*i+1);
417 HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs, ObjSize,
418 GPRPad, StackPad, Flags);
419 NumBytes += ObjSize + StackPad;
420 NumGPRs += ObjGPRs + GPRPad;
421 }
422
423 // Adjust the stack pointer for the new arguments...
424 // These operations are automatically eliminated by the prolog/epilog pass
425 Chain = DAG.getCALLSEQ_START(Chain,
426 DAG.getConstant(NumBytes, MVT::i32));
427
428 SDOperand StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
429
430 static const unsigned GPRArgRegs[] = {
431 ARM::R0, ARM::R1, ARM::R2, ARM::R3
432 };
433
434 NumGPRs = 0;
435 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
436 std::vector<SDOperand> MemOpChains;
437 for (unsigned i = 0; i != NumOps; ++i) {
438 SDOperand Arg = Op.getOperand(5+2*i);
439 unsigned Flags = Op.getConstantOperandVal(5+2*i+1);
440 MVT::ValueType ArgVT = Arg.getValueType();
441
442 unsigned ObjSize;
443 unsigned ObjGPRs;
444 unsigned GPRPad;
445 unsigned StackPad;
446 HowToPassArgument(ArgVT, NumGPRs, ArgOffset, ObjGPRs,
447 ObjSize, GPRPad, StackPad, Flags);
448 NumGPRs += GPRPad;
449 ArgOffset += StackPad;
450 if (ObjGPRs > 0) {
451 switch (ArgVT) {
452 default: assert(0 && "Unexpected ValueType for argument!");
453 case MVT::i32:
454 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Arg));
455 break;
456 case MVT::f32:
457 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs],
458 DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg)));
459 break;
460 case MVT::i64: {
461 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
462 DAG.getConstant(0, getPointerTy()));
463 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
464 DAG.getConstant(1, getPointerTy()));
465 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo));
466 if (ObjGPRs == 2)
467 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi));
468 else {
469 SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
470 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
471 MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0));
472 }
473 break;
474 }
475 case MVT::f64: {
476 SDOperand Cvt = DAG.getNode(ARMISD::FMRRD,
477 DAG.getVTList(MVT::i32, MVT::i32),
478 &Arg, 1);
479 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt));
480 if (ObjGPRs == 2)
481 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1],
482 Cvt.getValue(1)));
483 else {
484 SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
485 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
486 MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff,
487 NULL, 0));
488 }
489 break;
490 }
491 }
492 } else {
493 assert(ObjSize != 0);
494 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
495 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
496 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
497 }
498
499 NumGPRs += ObjGPRs;
500 ArgOffset += ObjSize;
501 }
502
503 if (!MemOpChains.empty())
504 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
505 &MemOpChains[0], MemOpChains.size());
506
507 // Build a sequence of copy-to-reg nodes chained together with token chain
508 // and flag operands which copy the outgoing args into the appropriate regs.
509 SDOperand InFlag;
510 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
511 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
512 InFlag);
513 InFlag = Chain.getValue(1);
514 }
515
516 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
517 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
518 // node so that legalize doesn't hack it.
519 bool isDirect = false;
520 bool isARMFunc = false;
521 bool isLocalARMFunc = false;
522 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
523 GlobalValue *GV = G->getGlobal();
524 isDirect = true;
525 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() ||
526 GV->hasLinkOnceLinkage());
527 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
528 getTargetMachine().getRelocationModel() != Reloc::Static;
529 isARMFunc = !Subtarget->isThumb() || isStub;
530 // ARM call to a local ARM function is predicable.
531 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
532 // tBX takes a register source operand.
533 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
534 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
535 ARMCP::CPStub, 4);
536 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
537 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
538 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
539 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
540 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
541 } else
542 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
543 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
544 isDirect = true;
545 bool isStub = Subtarget->isTargetDarwin() &&
546 getTargetMachine().getRelocationModel() != Reloc::Static;
547 isARMFunc = !Subtarget->isThumb() || isStub;
548 // tBX takes a register source operand.
549 const char *Sym = S->getSymbol();
550 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
551 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
552 ARMCP::CPStub, 4);
553 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
554 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
555 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
556 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
557 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
558 } else
559 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
560 }
561
562 // FIXME: handle tail calls differently.
563 unsigned CallOpc;
564 if (Subtarget->isThumb()) {
565 if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc))
566 CallOpc = ARMISD::CALL_NOLINK;
567 else
568 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
569 } else {
570 CallOpc = (isDirect || Subtarget->hasV5TOps())
571 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
572 : ARMISD::CALL_NOLINK;
573 }
574 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
575 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
576 Chain = DAG.getCopyToReg(Chain, ARM::LR,
577 DAG.getNode(ISD::UNDEF, MVT::i32), InFlag);
578 InFlag = Chain.getValue(1);
579 }
580
581 std::vector<MVT::ValueType> NodeTys;
582 NodeTys.push_back(MVT::Other); // Returns a chain
583 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
584
585 std::vector<SDOperand> Ops;
586 Ops.push_back(Chain);
587 Ops.push_back(Callee);
588
589 // Add argument registers to the end of the list so that they are known live
590 // into the call.
591 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
592 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
593 RegsToPass[i].second.getValueType()));
594
595 if (InFlag.Val)
596 Ops.push_back(InFlag);
597 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
598 InFlag = Chain.getValue(1);
599
600 SDOperand CSOps[] = { Chain, DAG.getConstant(NumBytes, MVT::i32), InFlag };
601 Chain = DAG.getNode(ISD::CALLSEQ_END,
602 DAG.getNodeValueTypes(MVT::Other, MVT::Flag),
603 ((RetVT != MVT::Other) ? 2 : 1), CSOps, 3);
604 if (RetVT != MVT::Other)
605 InFlag = Chain.getValue(1);
606
607 std::vector<SDOperand> ResultVals;
608 NodeTys.clear();
609
610 // If the call has results, copy the values out of the ret val registers.
611 switch (RetVT) {
612 default: assert(0 && "Unexpected ret value!");
613 case MVT::Other:
614 break;
615 case MVT::i32:
616 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
617 ResultVals.push_back(Chain.getValue(0));
618 if (Op.Val->getValueType(1) == MVT::i32) {
619 // Returns a i64 value.
620 Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32,
621 Chain.getValue(2)).getValue(1);
622 ResultVals.push_back(Chain.getValue(0));
623 NodeTys.push_back(MVT::i32);
624 }
625 NodeTys.push_back(MVT::i32);
626 break;
627 case MVT::f32:
628 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
629 ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f32,
630 Chain.getValue(0)));
631 NodeTys.push_back(MVT::f32);
632 break;
633 case MVT::f64: {
634 SDOperand Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag);
635 SDOperand Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2));
636 ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi));
637 NodeTys.push_back(MVT::f64);
638 break;
639 }
640 }
641
642 NodeTys.push_back(MVT::Other);
643
644 if (ResultVals.empty())
645 return Chain;
646
647 ResultVals.push_back(Chain);
648 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, &ResultVals[0],
649 ResultVals.size());
650 return Res.getValue(Op.ResNo);
651 }
652
653 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
654 SDOperand Copy;
655 SDOperand Chain = Op.getOperand(0);
656 switch(Op.getNumOperands()) {
657 default:
658 assert(0 && "Do not know how to return this many arguments!");
659 abort();
660 case 1: {
661 SDOperand LR = DAG.getRegister(ARM::LR, MVT::i32);
662 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain);
663 }
664 case 3:
665 Op = Op.getOperand(1);
666 if (Op.getValueType() == MVT::f32) {
667 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
668 } else if (Op.getValueType() == MVT::f64) {
669 // Recursively legalize f64 -> i64.
670 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Op);
671 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op,
672 DAG.getConstant(0, MVT::i32));
673 }
674 Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand());
675 if (DAG.getMachineFunction().liveout_empty())
676 DAG.getMachineFunction().addLiveOut(ARM::R0);
677 break;
678 case 5:
679 Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand());
680 Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
681 // If we haven't noted the R0+R1 are live out, do so now.
682 if (DAG.getMachineFunction().liveout_empty()) {
683 DAG.getMachineFunction().addLiveOut(ARM::R0);
684 DAG.getMachineFunction().addLiveOut(ARM::R1);
685 }
686 break;
687 }
688
689 //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag
690 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
691 }
692
693 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
694 // their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is
695 // one of the above mentioned nodes. It has to be wrapped because otherwise
696 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
697 // be used to form addressing mode. These wrapped nodes will be selected
698 // into MOVi.
699 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
700 MVT::ValueType PtrVT = Op.getValueType();
701 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
702 SDOperand Res;
703 if (CP->isMachineConstantPoolEntry())
704 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
705 CP->getAlignment());
706 else
707 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
708 CP->getAlignment());
709 return DAG.getNode(ARMISD::Wrapper, MVT::i32, Res);
710 }
711
712 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
713 SDOperand
714 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
715 SelectionDAG &DAG) {
716 MVT::ValueType PtrVT = getPointerTy();
717 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
718 ARMConstantPoolValue *CPV =
719 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
720 PCAdj, "tlsgd", true);
721 SDOperand Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2);
722 Argument = DAG.getNode(ARMISD::Wrapper, MVT::i32, Argument);
723 Argument = DAG.getLoad(PtrVT, DAG.getEntryNode(), Argument, NULL, 0);
724 SDOperand Chain = Argument.getValue(1);
725
726 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
727 Argument = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Argument, PICLabel);
728
729 // call __tls_get_addr.
730 ArgListTy Args;
731 ArgListEntry Entry;
732 Entry.Node = Argument;
733 Entry.Ty = (const Type *) Type::Int32Ty;
734 Args.push_back(Entry);
735 std::pair<SDOperand, SDOperand> CallResult =
736 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false,
737 CallingConv::C, false,
738 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG);
739 return CallResult.first;
740 }
741
742 // Lower ISD::GlobalTLSAddress using the "initial exec" or
743 // "local exec" model.
744 SDOperand
745 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
746 SelectionDAG &DAG) {
747 GlobalValue *GV = GA->getGlobal();
748 SDOperand Offset;
749 SDOperand Chain = DAG.getEntryNode();
750 MVT::ValueType PtrVT = getPointerTy();
751 // Get the Thread Pointer
752 SDOperand ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
753
754 if (GV->isDeclaration()){
755 // initial exec model
756 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
757 ARMConstantPoolValue *CPV =
758 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
759 PCAdj, "gottpoff", true);
760 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2);
761 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset);
762 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
763 Chain = Offset.getValue(1);
764
765 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
766 Offset = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Offset, PICLabel);
767
768 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
769 } else {
770 // local exec model
771 ARMConstantPoolValue *CPV =
772 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
773 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2);
774 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset);
775 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
776 }
777
778 // The address of the thread local variable is the add of the thread
779 // pointer with the offset of the variable.
780 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
781 }
782
783 SDOperand
784 ARMTargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
785 // TODO: implement the "local dynamic" model
786 assert(Subtarget->isTargetELF() &&
787 "TLS not implemented for non-ELF targets");
788 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
789 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
790 // otherwise use the "Local Exec" TLS Model
791 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
792 return LowerToTLSGeneralDynamicModel(GA, DAG);
793 else
794 return LowerToTLSExecModels(GA, DAG);
795 }
796
797 SDOperand ARMTargetLowering::LowerGlobalAddressELF(SDOperand Op,
798 SelectionDAG &DAG) {
799 MVT::ValueType PtrVT = getPointerTy();
800 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
801 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
802 if (RelocM == Reloc::PIC_) {
803 bool UseGOTOFF = GV->hasInternalLinkage() || GV->hasHiddenVisibility();
804 ARMConstantPoolValue *CPV =
805 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
806 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
807 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
808 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
809 SDOperand Chain = Result.getValue(1);
810 SDOperand GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT);
811 Result = DAG.getNode(ISD::ADD, PtrVT, Result, GOT);
812 if (!UseGOTOFF)
813 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0);
814 return Result;
815 } else {
816 SDOperand CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
817 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
818 return DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
819 }
820 }
821
822 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
823 /// even in non-static mode.
824 static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) {
825 return RelocM != Reloc::Static &&
826 (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
827 (GV->isDeclaration() && !GV->hasNotBeenReadFromBytecode()));
828 }
829
830 SDOperand ARMTargetLowering::LowerGlobalAddressDarwin(SDOperand Op,
831 SelectionDAG &DAG) {
832 MVT::ValueType PtrVT = getPointerTy();
833 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
834 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
835 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
836 SDOperand CPAddr;
837 if (RelocM == Reloc::Static)
838 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
839 else {
840 unsigned PCAdj = (RelocM != Reloc::PIC_)
841 ? 0 : (Subtarget->isThumb() ? 4 : 8);
842 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr
843 : ARMCP::CPValue;
844 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
845 Kind, PCAdj);
846 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
847 }
848 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
849
850 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
851 SDOperand Chain = Result.getValue(1);
852
853 if (RelocM == Reloc::PIC_) {
854 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
855 Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
856 }
857 if (IsIndirect)
858 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0);
859
860 return Result;
861 }
862
863 SDOperand ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDOperand Op,
864 SelectionDAG &DAG){
865 assert(Subtarget->isTargetELF() &&
866 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
867 MVT::ValueType PtrVT = getPointerTy();
868 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
869 ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_",
870 ARMPCLabelIndex,
871 ARMCP::CPValue, PCAdj);
872 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
873 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
874 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
875 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
876 return DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
877 }
878
879 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
880 unsigned VarArgsFrameIndex) {
881 // vastart just stores the address of the VarArgsFrameIndex slot into the
882 // memory location argument.
883 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
884 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
885 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
886 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(),
887 SV->getOffset());
888 }
889
890 static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
891 unsigned *vRegs, unsigned ArgNo,
892 unsigned &NumGPRs, unsigned &ArgOffset) {
893 MachineFunction &MF = DAG.getMachineFunction();
894 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
895 SDOperand Root = Op.getOperand(0);
896 std::vector<SDOperand> ArgValues;
897 SSARegMap *RegMap = MF.getSSARegMap();
898
899 static const unsigned GPRArgRegs[] = {
900 ARM::R0, ARM::R1, ARM::R2, ARM::R3
901 };
902
903 unsigned ObjSize;
904 unsigned ObjGPRs;
905 unsigned GPRPad;
906 unsigned StackPad;
907 unsigned Flags = Op.getConstantOperandVal(ArgNo + 3);
908 HowToPassArgument(ObjectVT, NumGPRs, ArgOffset, ObjGPRs,
909 ObjSize, GPRPad, StackPad, Flags);
910 NumGPRs += GPRPad;
911 ArgOffset += StackPad;
912
913 SDOperand ArgValue;
914 if (ObjGPRs == 1) {
915 unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
916 MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
917 vRegs[NumGPRs] = VReg;
918 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
919 if (ObjectVT == MVT::f32)
920 ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue);
921 } else if (ObjGPRs == 2) {
922 unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
923 MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
924 vRegs[NumGPRs] = VReg;
925 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
926
927 VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
928 MF.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
929 vRegs[NumGPRs+1] = VReg;
930 SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32);
931
932 if (ObjectVT == MVT::i64)
933 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2);
934 else
935 ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
936 }
937 NumGPRs += ObjGPRs;
938
939 if (ObjSize) {
940 // If the argument is actually used, emit a load from the right stack
941 // slot.
942 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
943 MachineFrameInfo *MFI = MF.getFrameInfo();
944 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
945 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
946 if (ObjGPRs == 0)
947 ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
948 else {
949 SDOperand ArgValue2 =
950 DAG.getLoad(MVT::i32, Root, FIN, NULL, 0);
951 if (ObjectVT == MVT::i64)
952 ArgValue= DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2);
953 else
954 ArgValue= DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
955 }
956 } else {
957 // Don't emit a dead load.
958 ArgValue = DAG.getNode(ISD::UNDEF, ObjectVT);
959 }
960
961 ArgOffset += ObjSize; // Move on to the next argument.
962 }
963
964 return ArgValue;
965 }
966
967 SDOperand
968 ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
969 std::vector<SDOperand> ArgValues;
970 SDOperand Root = Op.getOperand(0);
971 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
972 unsigned NumGPRs = 0; // GPRs used for parameter passing.
973 unsigned VRegs[4];
974
975 unsigned NumArgs = Op.Val->getNumValues()-1;
976 for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo)
977 ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, VRegs, ArgNo,
978 NumGPRs, ArgOffset));
979
980 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
981 if (isVarArg) {
982 static const unsigned GPRArgRegs[] = {
983 ARM::R0, ARM::R1, ARM::R2, ARM::R3
984 };
985
986 MachineFunction &MF = DAG.getMachineFunction();
987 SSARegMap *RegMap = MF.getSSARegMap();
988 MachineFrameInfo *MFI = MF.getFrameInfo();
989 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
990 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
991 unsigned VARegSize = (4 - NumGPRs) * 4;
992 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
993 if (VARegSaveSize) {
994 // If this function is vararg, store any remaining integer argument regs
995 // to their spots on the stack so that they may be loaded by deferencing
996 // the result of va_next.
997 AFI->setVarArgsRegSaveSize(VARegSaveSize);
998 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
999 VARegSaveSize - VARegSize);
1000 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
1001
1002 SmallVector<SDOperand, 4> MemOps;
1003 for (; NumGPRs < 4; ++NumGPRs) {
1004 unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
1005 MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
1006 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1007 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1008 MemOps.push_back(Store);
1009 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1010 DAG.getConstant(4, getPointerTy()));
1011 }
1012 if (!MemOps.empty())
1013 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1014 &MemOps[0], MemOps.size());
1015 } else
1016 // This will point to the next argument passed via stack.
1017 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1018 }
1019
1020 ArgValues.push_back(Root);
1021
1022 // Return the new list of results.
1023 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
1024 Op.Val->value_end());
1025 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
1026 }
1027
1028 /// isFloatingPointZero - Return true if this is +0.0.
1029 static bool isFloatingPointZero(SDOperand Op) {
1030 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1031 return CFP->isExactlyValue(0.0);
1032 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
1033 // Maybe this has already been legalized into the constant pool?
1034 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1035 SDOperand WrapperOp = Op.getOperand(1).getOperand(0);
1036 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1037 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1038 return CFP->isExactlyValue(0.0);
1039 }
1040 }
1041 return false;
1042 }
1043
1044 static bool isLegalCmpImmediate(unsigned C, bool isThumb) {
1045 return ( isThumb && (C & ~255U) == 0) ||
1046 (!isThumb && ARM_AM::getSOImmVal(C) != -1);
1047 }
1048
1049 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1050 /// the given operands.
1051 static SDOperand getARMCmp(SDOperand LHS, SDOperand RHS, ISD::CondCode CC,
1052 SDOperand &ARMCC, SelectionDAG &DAG, bool isThumb) {
1053 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.Val)) {
1054 unsigned C = RHSC->getValue();
1055 if (!isLegalCmpImmediate(C, isThumb)) {
1056 // Constant does not fit, try adjusting it by one?
1057 switch (CC) {
1058 default: break;
1059 case ISD::SETLT:
1060 case ISD::SETGE:
1061 if (isLegalCmpImmediate(C-1, isThumb)) {
1062 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1063 RHS = DAG.getConstant(C-1, MVT::i32);
1064 }
1065 break;
1066 case ISD::SETULT:
1067 case ISD::SETUGE:
1068 if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) {
1069 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1070 RHS = DAG.getConstant(C-1, MVT::i32);
1071 }
1072 break;
1073 case ISD::SETLE:
1074 case ISD::SETGT:
1075 if (isLegalCmpImmediate(C+1, isThumb)) {
1076 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1077 RHS = DAG.getConstant(C+1, MVT::i32);
1078 }
1079 break;
1080 case ISD::SETULE:
1081 case ISD::SETUGT:
1082 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) {
1083 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1084 RHS = DAG.getConstant(C+1, MVT::i32);
1085 }
1086 break;
1087 }
1088 }
1089 }
1090
1091 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1092 ARMISD::NodeType CompareType;
1093 switch (CondCode) {
1094 default:
1095 CompareType = ARMISD::CMP;
1096 break;
1097 case ARMCC::EQ:
1098 case ARMCC::NE:
1099 case ARMCC::MI:
1100 case ARMCC::PL:
1101 // Uses only N and Z Flags
1102 CompareType = ARMISD::CMPNZ;
1103 break;
1104 }
1105 ARMCC = DAG.getConstant(CondCode, MVT::i32);
1106 return DAG.getNode(CompareType, MVT::Flag, LHS, RHS);
1107 }
1108
1109 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1110 static SDOperand getVFPCmp(SDOperand LHS, SDOperand RHS, SelectionDAG &DAG) {
1111 SDOperand Cmp;
1112 if (!isFloatingPointZero(RHS))
1113 Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS);
1114 else
1115 Cmp = DAG.getNode(ARMISD::CMPFPw0, MVT::Flag, LHS);
1116 return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp);
1117 }
1118
1119 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG,
1120 const ARMSubtarget *ST) {
1121 MVT::ValueType VT = Op.getValueType();
1122 SDOperand LHS = Op.getOperand(0);
1123 SDOperand RHS = Op.getOperand(1);
1124 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1125 SDOperand TrueVal = Op.getOperand(2);
1126 SDOperand FalseVal = Op.getOperand(3);
1127
1128 if (LHS.getValueType() == MVT::i32) {
1129 SDOperand ARMCC;
1130 SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
1131 return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, Cmp);
1132 }
1133
1134 ARMCC::CondCodes CondCode, CondCode2;
1135 if (FPCCToARMCC(CC, CondCode, CondCode2))
1136 std::swap(TrueVal, FalseVal);
1137
1138 SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
1139 SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
1140 SDOperand Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal,
1141 ARMCC, Cmp);
1142 if (CondCode2 != ARMCC::AL) {
1143 SDOperand ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1144 // FIXME: Needs another CMP because flag can have but one use.
1145 SDOperand Cmp2 = getVFPCmp(LHS, RHS, DAG);
1146 Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, Cmp2);
1147 }
1148 return Result;
1149 }
1150
1151 static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG,
1152 const ARMSubtarget *ST) {
1153 SDOperand Chain = Op.getOperand(0);
1154 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1155 SDOperand LHS = Op.getOperand(2);
1156 SDOperand RHS = Op.getOperand(3);
1157 SDOperand Dest = Op.getOperand(4);
1158
1159 if (LHS.getValueType() == MVT::i32) {
1160 SDOperand ARMCC;
1161 SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
1162 return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, Cmp);
1163 }
1164
1165 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1166 ARMCC::CondCodes CondCode, CondCode2;
1167 if (FPCCToARMCC(CC, CondCode, CondCode2))
1168 // Swap the LHS/RHS of the comparison if needed.
1169 std::swap(LHS, RHS);
1170
1171 SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
1172 SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
1173 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1174 SDOperand Ops[] = { Chain, Dest, ARMCC, Cmp };
1175 SDOperand Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 4);
1176 if (CondCode2 != ARMCC::AL) {
1177 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1178 SDOperand Ops[] = { Res, Dest, ARMCC, Res.getValue(1) };
1179 Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 4);
1180 }
1181 return Res;
1182 }
1183
1184 SDOperand ARMTargetLowering::LowerBR_JT(SDOperand Op, SelectionDAG &DAG) {
1185 SDOperand Chain = Op.getOperand(0);
1186 SDOperand Table = Op.getOperand(1);
1187 SDOperand Index = Op.getOperand(2);
1188
1189 MVT::ValueType PTy = getPointerTy();
1190 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1191 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1192 SDOperand UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
1193 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1194 Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId);
1195 Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy));
1196 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1197 bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1198 Addr = DAG.getLoad(isPIC ? MVT::i32 : PTy, Chain, Addr, NULL, 0);
1199 Chain = Addr.getValue(1);
1200 if (isPIC)
1201 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table);
1202 return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId);
1203 }
1204
1205 static SDOperand LowerFP_TO_INT(SDOperand Op, SelectionDAG &DAG) {
1206 unsigned Opc =
1207 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1208 Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0));
1209 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
1210 }
1211
1212 static SDOperand LowerINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
1213 MVT::ValueType VT = Op.getValueType();
1214 unsigned Opc =
1215 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1216
1217 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
1218 return DAG.getNode(Opc, VT, Op);
1219 }
1220
1221 static SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
1222 // Implement fcopysign with a fabs and a conditional fneg.
1223 SDOperand Tmp0 = Op.getOperand(0);
1224 SDOperand Tmp1 = Op.getOperand(1);
1225 MVT::ValueType VT = Op.getValueType();
1226 MVT::ValueType SrcVT = Tmp1.getValueType();
1227 SDOperand AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0);
1228 SDOperand Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG);
1229 SDOperand ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1230 return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, Cmp);
1231 }
1232
1233 static SDOperand LowerBIT_CONVERT(SDOperand Op, SelectionDAG &DAG) {
1234 // Turn f64->i64 into FMRRD.
1235 assert(Op.getValueType() == MVT::i64 &&
1236 Op.getOperand(0).getValueType() == MVT::f64);
1237
1238 Op = Op.getOperand(0);
1239 SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32),
1240 &Op, 1);
1241
1242 // Merge the pieces into a single i64 value.
1243 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1));
1244 }
1245
1246 static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
1247 // FIXME: All this code is target-independent. Create a new target-indep
1248 // MULHILO node and move this code to the legalizer.
1249 //
1250 assert(Op.getValueType() == MVT::i64 && "Only handles i64 expand right now!");
1251
1252 SDOperand LL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1253 DAG.getConstant(0, MVT::i32));
1254 SDOperand RL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(1),
1255 DAG.getConstant(0, MVT::i32));
1256
1257 const TargetLowering &TL = DAG.getTargetLoweringInfo();
1258 unsigned LHSSB = TL.ComputeNumSignBits(Op.getOperand(0));
1259 unsigned RHSSB = TL.ComputeNumSignBits(Op.getOperand(1));
1260
1261 SDOperand Lo, Hi;
1262 // Figure out how to lower this multiply.
1263 if (LHSSB >= 33 && RHSSB >= 33) {
1264 // If the input values are both sign extended, we can emit a mulhs+mul.
1265 Lo = DAG.getNode(ISD::MUL, MVT::i32, LL, RL);
1266 Hi = DAG.getNode(ISD::MULHS, MVT::i32, LL, RL);
1267 } else if (LHSSB == 32 && RHSSB == 32 &&
1268 TL.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) &&
1269 TL.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) {
1270 // If the inputs are zero extended, use mulhu.
1271 Lo = DAG.getNode(ISD::MUL, MVT::i32, LL, RL);
1272 Hi = DAG.getNode(ISD::MULHU, MVT::i32, LL, RL);
1273 } else {
1274 SDOperand LH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1275 DAG.getConstant(1, MVT::i32));
1276 SDOperand RH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(1),
1277 DAG.getConstant(1, MVT::i32));
1278
1279 // Lo,Hi = umul LHS, RHS.
1280 SDOperand Ops[] = { LL, RL };
1281 SDOperand UMul64 = DAG.getNode(ARMISD::MULHILOU,
1282 DAG.getVTList(MVT::i32, MVT::i32), Ops, 2);
1283 Lo = UMul64;
1284 Hi = UMul64.getValue(1);
1285 RH = DAG.getNode(ISD::MUL, MVT::i32, LL, RH);
1286 LH = DAG.getNode(ISD::MUL, MVT::i32, LH, RL);
1287 Hi = DAG.getNode(ISD::ADD, MVT::i32, Hi, RH);
1288 Hi = DAG.getNode(ISD::ADD, MVT::i32, Hi, LH);
1289 }
1290
1291 // Merge the pieces into a single i64 value.
1292 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
1293 }
1294
1295 static SDOperand LowerMULHU(SDOperand Op, SelectionDAG &DAG) {
1296 SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1) };
1297 return DAG.getNode(ARMISD::MULHILOU,
1298 DAG.getVTList(MVT::i32, MVT::i32), Ops, 2).getValue(1);
1299 }
1300
1301 static SDOperand LowerMULHS(SDOperand Op, SelectionDAG &DAG) {
1302 SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1) };
1303 return DAG.getNode(ARMISD::MULHILOS,
1304 DAG.getVTList(MVT::i32, MVT::i32), Ops, 2).getValue(1);
1305 }
1306
1307 static SDOperand LowerSRx(SDOperand Op, SelectionDAG &DAG,
1308 const ARMSubtarget *ST) {
1309 assert(Op.getValueType() == MVT::i64 &&
1310 (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) &&
1311 "Unknown shift to lower!");
1312
1313 // We only lower SRA, SRL of 1 here, all others use generic lowering.
1314 if (!isa<ConstantSDNode>(Op.getOperand(1)) ||
1315 cast<ConstantSDNode>(Op.getOperand(1))->getValue() != 1)
1316 return SDOperand();
1317
1318 // If we are in thumb mode, we don't have RRX.
1319 if (ST->isThumb()) return SDOperand();
1320
1321 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
1322 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1323 DAG.getConstant(0, MVT::i32));
1324 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1325 DAG.getConstant(1, MVT::i32));
1326
1327 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
1328 // captures the result into a carry flag.
1329 unsigned Opc = Op.getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
1330 Hi = DAG.getNode(Opc, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
1331
1332 // The low part is an ARMISD::RRX operand, which shifts the carry in.
1333 Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1));
1334
1335 // Merge the pieces into a single i64 value.
1336 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
1337 }
1338
1339 SDOperand ARMTargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) {
1340 SDOperand Chain = Op.getOperand(0);
1341 SDOperand Dest = Op.getOperand(1);
1342 SDOperand Src = Op.getOperand(2);
1343 SDOperand Count = Op.getOperand(3);
1344 unsigned Align =
1345 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
1346 if (Align == 0) Align = 1;
1347
1348 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Count);
1349 // Just call memcpy if:
1350 // not 4-byte aligned
1351 // size is unknown
1352 // size is >= the threshold.
1353 if ((Align & 3) != 0 ||
1354 !I ||
1355 I->getValue() >= 64 ||
1356 (I->getValue() & 3) != 0) {
1357 MVT::ValueType IntPtr = getPointerTy();
1358 TargetLowering::ArgListTy Args;
1359 TargetLowering::ArgListEntry Entry;
1360 Entry.Ty = getTargetData()->getIntPtrType();
1361 Entry.Node = Op.getOperand(1); Args.push_back(Entry);
1362 Entry.Node = Op.getOperand(2); Args.push_back(Entry);
1363 Entry.Node = Op.getOperand(3); Args.push_back(Entry);
1364 std::pair<SDOperand,SDOperand> CallResult =
1365 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
1366 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG);
1367 return CallResult.second;
1368 }
1369
1370 // Otherwise do repeated 4-byte loads and stores. To be improved.
1371 assert((I->getValue() & 3) == 0);
1372 assert((Align & 3) == 0);
1373 unsigned NumMemOps = I->getValue() >> 2;
1374 unsigned EmittedNumMemOps = 0;
1375 unsigned SrcOff = 0, DstOff = 0;
1376 MVT::ValueType VT = MVT::i32;
1377 unsigned VTSize = 4;
1378 const unsigned MAX_LOADS_IN_LDM = 6;
1379 SDOperand LoadChains[MAX_LOADS_IN_LDM];
1380 SDOperand Loads[MAX_LOADS_IN_LDM];
1381
1382 // Emit up to 4 loads, then a TokenFactor barrier, then the same
1383 // number of stores. The loads and stores will get combined into
1384 // ldm/stm later on.
1385 while(EmittedNumMemOps < NumMemOps) {
1386 unsigned i;
1387 for (i=0; i<MAX_LOADS_IN_LDM && EmittedNumMemOps+i < NumMemOps; i++) {
1388 Loads[i] = DAG.getLoad(VT, Chain,
1389 DAG.getNode(ISD::ADD, VT, Src,
1390 DAG.getConstant(SrcOff, VT)),
1391 NULL, 0);
1392 LoadChains[i] = Loads[i].getValue(1);
1393 SrcOff += VTSize;
1394 }
1395
1396 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &LoadChains[0], i);
1397
1398 for (i=0; i<MAX_LOADS_IN_LDM && EmittedNumMemOps+i < NumMemOps; i++) {
1399 Chain = DAG.getStore(Chain, Loads[i],
1400 DAG.getNode(ISD::ADD, VT, Dest,
1401 DAG.getConstant(DstOff, VT)),
1402 NULL, 0);
1403 DstOff += VTSize;
1404 }
1405 EmittedNumMemOps += i;
1406 }
1407
1408 return Chain;
1409 }
1410
1411 SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
1412 switch (Op.getOpcode()) {
1413 default: assert(0 && "Don't know how to custom lower this!"); abort();
1414 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1415 case ISD::GlobalAddress:
1416 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
1417 LowerGlobalAddressELF(Op, DAG);
1418 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
1419 case ISD::CALL: return LowerCALL(Op, DAG);
1420 case ISD::RET: return LowerRET(Op, DAG);
1421 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget);
1422 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget);
1423 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
1424 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
1425 case ISD::SINT_TO_FP:
1426 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
1427 case ISD::FP_TO_SINT:
1428 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
1429 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
1430 case ISD::BIT_CONVERT: return LowerBIT_CONVERT(Op, DAG);
1431 case ISD::MUL: return LowerMUL(Op, DAG);
1432 case ISD::MULHU: return LowerMULHU(Op, DAG);
1433 case ISD::MULHS: return LowerMULHS(Op, DAG);
1434 case ISD::SRL:
1435 case ISD::SRA: return LowerSRx(Op, DAG, Subtarget);
1436 case ISD::FORMAL_ARGUMENTS:
1437 return LowerFORMAL_ARGUMENTS(Op, DAG);
1438 case ISD::RETURNADDR: break;
1439 case ISD::FRAMEADDR: break;
1440 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
1441 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
1442 }
1443 return SDOperand();
1444 }
1445
1446 //===----------------------------------------------------------------------===//
1447 // ARM Scheduler Hooks
1448 //===----------------------------------------------------------------------===//
1449
1450 MachineBasicBlock *
1451 ARMTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
1452 MachineBasicBlock *BB) {
1453 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1454 switch (MI->getOpcode()) {
1455 default: assert(false && "Unexpected instr type to insert");
1456 case ARM::tMOVCCr: {
1457 // To "insert" a SELECT_CC instruction, we actually have to insert the
1458 // diamond control-flow pattern. The incoming instruction knows the
1459 // destination vreg to set, the condition code register to branch on, the
1460 // true/false values to select between, and a branch opcode to use.
1461 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1462 ilist<MachineBasicBlock>::iterator It = BB;
1463 ++It;
1464
1465 // thisMBB:
1466 // ...
1467 // TrueVal = ...
1468 // cmpTY ccX, r1, r2
1469 // bCC copy1MBB
1470 // fallthrough --> copy0MBB
1471 MachineBasicBlock *thisMBB = BB;
1472 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1473 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
1474 BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB)
1475 .addImm(MI->getOperand(3).getImm());
1476 MachineFunction *F = BB->getParent();
1477 F->getBasicBlockList().insert(It, copy0MBB);
1478 F->getBasicBlockList().insert(It, sinkMBB);
1479 // Update machine-CFG edges by first adding all successors of the current
1480 // block to the new block which will contain the Phi node for the select.
1481 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
1482 e = BB->succ_end(); i != e; ++i)
1483 sinkMBB->addSuccessor(*i);
1484 // Next, remove all successors of the current block, and add the true
1485 // and fallthrough blocks as its successors.
1486 while(!BB->succ_empty())
1487 BB->removeSuccessor(BB->succ_begin());
1488 BB->addSuccessor(copy0MBB);
1489 BB->addSuccessor(sinkMBB);
1490
1491 // copy0MBB:
1492 // %FalseValue = ...
1493 // # fallthrough to sinkMBB
1494 BB = copy0MBB;
1495
1496 // Update machine-CFG edges
1497 BB->addSuccessor(sinkMBB);
1498
1499 // sinkMBB:
1500 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1501 // ...
1502 BB = sinkMBB;
1503 BuildMI(BB, TII->get(ARM::PHI), MI->getOperand(0).getReg())
1504 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
1505 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1506
1507 delete MI; // The pseudo instruction is gone now.
1508 return BB;
1509 }
1510 }
1511 }
1512
1513 //===----------------------------------------------------------------------===//
1514 // ARM Optimization Hooks
1515 //===----------------------------------------------------------------------===//
1516
1517 /// isLegalAddressImmediate - Return true if the integer value can be used
1518 /// as the offset of the target addressing mode for load / store of the
1519 /// given type.
1520 static bool isLegalAddressImmediate(int64_t V, MVT::ValueType VT,
1521 const ARMSubtarget *Subtarget) {
1522 if (V == 0)
1523 return true;
1524
1525 if (Subtarget->isThumb()) {
1526 if (V < 0)
1527 return false;
1528
1529 unsigned Scale = 1;
1530 switch (VT) {
1531 default: return false;
1532 case MVT::i1:
1533 case MVT::i8:
1534 // Scale == 1;
1535 break;
1536 case MVT::i16:
1537 // Scale == 2;
1538 Scale = 2;
1539 break;
1540 case MVT::i32:
1541 // Scale == 4;
1542 Scale = 4;
1543 break;
1544 }
1545
1546 if ((V & (Scale - 1)) != 0)
1547 return false;
1548 V /= Scale;
1549 return V == V & ((1LL << 5) - 1);
1550 }
1551
1552 if (V < 0)
1553 V = - V;
1554 switch (VT) {
1555 default: return false;
1556 case MVT::i1:
1557 case MVT::i8:
1558 case MVT::i32:
1559 // +- imm12
1560 return V == V & ((1LL << 12) - 1);
1561 case MVT::i16:
1562 // +- imm8
1563 return V == V & ((1LL << 8) - 1);
1564 case MVT::f32:
1565 case MVT::f64:
1566 if (!Subtarget->hasVFP2())
1567 return false;
1568 if ((V & 3) != 0)
1569 return false;
1570 V >>= 2;
1571 return V == V & ((1LL << 8) - 1);
1572 }
1573 }
1574
1575 /// isLegalAddressingMode - Return true if the addressing mode represented
1576 /// by AM is legal for this target, for a load/store of the specified type.
1577 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1578 const Type *Ty) const {
1579 if (!isLegalAddressImmediate(AM.BaseOffs, getValueType(Ty), Subtarget))
1580 return false;
1581
1582 // Can never fold addr of global into load/store.
1583 if (AM.BaseGV)
1584 return false;
1585
1586 switch (AM.Scale) {
1587 case 0: // no scale reg, must be "r+i" or "r", or "i".
1588 break;
1589 case 1:
1590 if (Subtarget->isThumb())
1591 return false;
1592 // FALL THROUGH.
1593 default:
1594 // ARM doesn't support any R+R*scale+imm addr modes.
1595 if (AM.BaseOffs)
1596 return false;
1597
1598 int Scale = AM.Scale;
1599 switch (getValueType(Ty)) {
1600 default: return false;
1601 case MVT::i1:
1602 case MVT::i8:
1603 case MVT::i32:
1604 case MVT::i64:
1605 // This assumes i64 is legalized to a pair of i32. If not (i.e.
1606 // ldrd / strd are used, then its address mode is same as i16.
1607 // r + r
1608 if (Scale < 0) Scale = -Scale;
1609 if (Scale == 1)
1610 return true;
1611 // r + r << imm
1612 return isPowerOf2_32(Scale & ~1);
1613 case MVT::i16:
1614 // r + r
1615 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
1616 return true;
1617 return false;
1618
1619 case MVT::isVoid:
1620 // Note, we allow "void" uses (basically, uses that aren't loads or
1621 // stores), because arm allows folding a scale into many arithmetic
1622 // operations. This should be made more precise and revisited later.
1623
1624 // Allow r << imm, but the imm has to be a multiple of two.
1625 if (AM.Scale & 1) return false;
1626 return isPowerOf2_32(AM.Scale);
1627 }
1628 break;
1629 }
1630 return true;
1631 }
1632
1633
1634 static bool getIndexedAddressParts(SDNode *Ptr, MVT::ValueType VT,
1635 bool isSEXTLoad, SDOperand &Base,
1636 SDOperand &Offset, bool &isInc,
1637 SelectionDAG &DAG) {
1638 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
1639 return false;
1640
1641 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
1642 // AddressingMode 3
1643 Base = Ptr->getOperand(0);
1644 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1645 int RHSC = (int)RHS->getValue();
1646 if (RHSC < 0 && RHSC > -256) {
1647 isInc = false;
1648 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1649 return true;
1650 }
1651 }
1652 isInc = (Ptr->getOpcode() == ISD::ADD);
1653 Offset = Ptr->getOperand(1);
1654 return true;
1655 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
1656 // AddressingMode 2
1657 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1658 int RHSC = (int)RHS->getValue();
1659 if (RHSC < 0 && RHSC > -0x1000) {
1660 isInc = false;
1661 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1662 Base = Ptr->getOperand(0);
1663 return true;
1664 }
1665 }
1666
1667 if (Ptr->getOpcode() == ISD::ADD) {
1668 isInc = true;
1669 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
1670 if (ShOpcVal != ARM_AM::no_shift) {
1671 Base = Ptr->getOperand(1);
1672 Offset = Ptr->getOperand(0);
1673 } else {
1674 Base = Ptr->getOperand(0);
1675 Offset = Ptr->getOperand(1);
1676 }
1677 return true;
1678 }
1679
1680 isInc = (Ptr->getOpcode() == ISD::ADD);
1681 Base = Ptr->getOperand(0);
1682 Offset = Ptr->getOperand(1);
1683 return true;
1684 }
1685
1686 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
1687 return false;
1688 }
1689
1690 /// getPreIndexedAddressParts - returns true by value, base pointer and
1691 /// offset pointer and addressing mode by reference if the node's address
1692 /// can be legally represented as pre-indexed load / store address.
1693 bool
1694 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
1695 SDOperand &Offset,
1696 ISD::MemIndexedMode &AM,
1697 SelectionDAG &DAG) {
1698 if (Subtarget->isThumb())
1699 return false;
1700
1701 MVT::ValueType VT;
1702 SDOperand Ptr;
1703 bool isSEXTLoad = false;
1704 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1705 Ptr = LD->getBasePtr();
1706 VT = LD->getLoadedVT();
1707 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1708 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1709 Ptr = ST->getBasePtr();
1710 VT = ST->getStoredVT();
1711 } else
1712 return false;
1713
1714 bool isInc;
1715 bool isLegal = getIndexedAddressParts(Ptr.Val, VT, isSEXTLoad, Base, Offset,
1716 isInc, DAG);
1717 if (isLegal) {
1718 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
1719 return true;
1720 }
1721 return false;
1722 }
1723
1724 /// getPostIndexedAddressParts - returns true by value, base pointer and
1725 /// offset pointer and addressing mode by reference if this node can be
1726 /// combined with a load / store to form a post-indexed load / store.
1727 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1728 SDOperand &Base,
1729 SDOperand &Offset,
1730 ISD::MemIndexedMode &AM,
1731 SelectionDAG &DAG) {
1732 if (Subtarget->isThumb())
1733 return false;
1734
1735 MVT::ValueType VT;
1736 SDOperand Ptr;
1737 bool isSEXTLoad = false;
1738 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1739 VT = LD->getLoadedVT();
1740 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1741 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1742 VT = ST->getStoredVT();
1743 } else
1744 return false;
1745
1746 bool isInc;
1747 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
1748 isInc, DAG);
1749 if (isLegal) {
1750 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
1751 return true;
1752 }
1753 return false;
1754 }
1755
1756 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
1757 uint64_t Mask,
1758 uint64_t &KnownZero,
1759 uint64_t &KnownOne,
1760 unsigned Depth) const {
1761 KnownZero = 0;
1762 KnownOne = 0;
1763 switch (Op.getOpcode()) {
1764 default: break;
1765 case ARMISD::CMOV: {
1766 // Bits are known zero/one if known on the LHS and RHS.
1767 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
1768 if (KnownZero == 0 && KnownOne == 0) return;
1769
1770 uint64_t KnownZeroRHS, KnownOneRHS;
1771 ComputeMaskedBits(Op.getOperand(1), Mask,
1772 KnownZeroRHS, KnownOneRHS, Depth+1);
1773 KnownZero &= KnownZeroRHS;
1774 KnownOne &= KnownOneRHS;
1775 return;
1776 }
1777 }
1778 }
1779
1780 //===----------------------------------------------------------------------===//
1781 // ARM Inline Assembly Support
1782 //===----------------------------------------------------------------------===//
1783
1784 /// getConstraintType - Given a constraint letter, return the type of
1785 /// constraint it is for this target.
1786 ARMTargetLowering::ConstraintType
1787 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
1788 if (Constraint.size() == 1) {
1789 switch (Constraint[0]) {
1790 default: break;
1791 case 'l': return C_RegisterClass;
1792 case 'w': return C_RegisterClass;
1793 }
1794 }
1795 return TargetLowering::getConstraintType(Constraint);
1796 }
1797
1798 std::pair<unsigned, const TargetRegisterClass*>
1799 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
1800 MVT::ValueType VT) const {
1801 if (Constraint.size() == 1) {
1802 // GCC RS6000 Constraint Letters
1803 switch (Constraint[0]) {
1804 case 'l':
1805 // FIXME: in thumb mode, 'l' is only low-regs.
1806 // FALL THROUGH.
1807 case 'r':
1808 return std::make_pair(0U, ARM::GPRRegisterClass);
1809 case 'w':
1810 if (VT == MVT::f32)
1811 return std::make_pair(0U, ARM::SPRRegisterClass);
1812 if (VT == MVT::f64)
1813 return std::make_pair(0U, ARM::DPRRegisterClass);
1814 break;
1815 }
1816 }
1817 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1818 }
1819
1820 std::vector<unsigned> ARMTargetLowering::
1821 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1822 MVT::ValueType VT) const {
1823 if (Constraint.size() != 1)
1824 return std::vector<unsigned>();
1825
1826 switch (Constraint[0]) { // GCC ARM Constraint Letters
1827 default: break;
1828 case 'l':
1829 case 'r':
1830 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1831 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1832 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1833 ARM::R12, ARM::LR, 0);
1834 case 'w':
1835 if (VT == MVT::f32)
1836 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1837 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1838 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1839 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
1840 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
1841 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
1842 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
1843 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
1844 if (VT == MVT::f64)
1845 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1846 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1847 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
1848 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
1849 break;
1850 }
1851
1852 return std::vector<unsigned>();
1853 }
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