tools/llvm-exegesis/lib/MCInstrDescView.h

   1 //===-- MCInstrDescView.h ---------------------------------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 ///
  10 /// \file
  11 /// Provide views around LLVM structures to represents an instruction instance,
  12 /// as well as its implicit and explicit arguments in a uniform way.
  13 /// Arguments that are explicit and independant (non tied) also have a Variable
  14 /// associated to them so the instruction can be fully defined by reading its
  15 /// Variables.
  16 ///
  17 //===----------------------------------------------------------------------===//
  18
  19 #ifndef LLVM_TOOLS_LLVM_EXEGESIS_MCINSTRDESCVIEW_H
  20 #define LLVM_TOOLS_LLVM_EXEGESIS_MCINSTRDESCVIEW_H
  21
  22 #include <random>
  23
  24 #include "RegisterAliasing.h"
  25 #include "llvm/ADT/ArrayRef.h"
  26 #include "llvm/ADT/Optional.h"
  27 #include "llvm/MC/MCInst.h"
  28 #include "llvm/MC/MCInstrDesc.h"
  29 #include "llvm/MC/MCInstrInfo.h"
  30
  31 namespace exegesis {
  32
  33 // A variable represents the value associated to an Operand or a set of Operands
  34 // if they are tied together.
  35 struct Variable {
  36   // Returns the index of this Variable inside Instruction's Variable.
  37   unsigned getIndex() const;
  38
  39   // Returns the index of the Operand linked to this Variable.
  40   unsigned getPrimaryOperandIndex() const;
  41
  42   // Returns whether this Variable has more than one Operand linked to it.
  43   bool hasTiedOperands() const;
  44
  45   // The indices of the operands tied to this Variable.
  46   llvm::SmallVector<unsigned, 2> TiedOperands;
  47   llvm::MCOperand AssignedValue;
  48   // The index of this Variable in Instruction.Variables and its associated
  49   // Value in InstructionBuilder.VariableValues.
  50   int Index = -1;
  51 };
  52
  53 // MCOperandInfo can only represents Explicit operands. This object gives a
  54 // uniform view of Implicit and Explicit Operands.
  55 // - Index: can be used to refer to MCInstrDesc::operands for Explicit operands.
  56 // - Tracker: is set for Register Operands and is used to keep track of possible
  57 // registers and the registers reachable from them (aliasing registers).
  58 // - Info: a shortcut for MCInstrDesc::operands()[Index].
  59 // - TiedToIndex: the index of the Operand holding the value or -1.
  60 // - ImplicitReg: a pointer to the register value when Operand is Implicit,
  61 // nullptr otherwise.
  62 // - VariableIndex: the index of the Variable holding the value for this Operand
  63 // or -1 if this operand is implicit.
  64 struct Operand {
  65   bool getIndex() const;
  66   bool isExplicit() const;
  67   bool isImplicit() const;
  68   bool isImplicitReg() const;
  69   bool isDef() const;
  70   bool isUse() const;
  71   bool isReg() const;
  72   bool isTied() const;
  73   bool isVariable() const;
  74   bool isMemory() const;
  75   bool isImmediate() const;
  76   int getTiedToIndex() const;
  77   int getVariableIndex() const;
  78   unsigned getImplicitReg() const;
  79   const RegisterAliasingTracker &getRegisterAliasing() const;
  80   const llvm::MCOperandInfo &getExplicitOperandInfo() const;
  81
  82   // Please use the accessors above and not the following fields.
  83   unsigned Index = 0;
  84   bool IsDef = false;
  85   const RegisterAliasingTracker *Tracker = nullptr; // Set for Register Op.
  86   const llvm::MCOperandInfo *Info = nullptr;        // Set for Explicit Op.
  87   int TiedToIndex = -1;                             // Set for Reg&Explicit Op.
  88   const llvm::MCPhysReg *ImplicitReg = nullptr;     // Set for Implicit Op.
  89   int VariableIndex = -1;                           // Set for Explicit Op.
  90 };
  91
  92 // A view over an MCInstrDesc offering a convenient interface to compute
  93 // Register aliasing.
  94 struct Instruction {
  95   Instruction(const llvm::MCInstrDesc &MCInstrDesc,
  96               const RegisterAliasingTrackerCache &ATC);
  97
  98   // Returns the Operand linked to this Variable.
  99   // In case the Variable is tied, the primary (i.e. Def) Operand is returned.
 100   const Operand &getPrimaryOperand(const Variable &Var) const;
 101
 102   // Returns whether this instruction has Memory Operands.
 103   // Repeating this instruction executes sequentially with an instruction that
 104   // reads or write the same memory region.
 105   bool hasMemoryOperands() const;
 106
 107   // Whether this instruction is self aliasing through its implicit registers.
 108   // Repeating this instruction is guaranteed to executes sequentially.
 109   bool hasAliasingImplicitRegisters() const;
 110
 111   // Whether this instruction is self aliasing through its tied registers.
 112   // Repeating this instruction is guaranteed to executes sequentially.
 113   bool hasTiedRegisters() const;
 114
 115   // Whether this instruction is self aliasing through some registers.
 116   // Repeating this instruction may execute sequentially by picking aliasing
 117   // Use and Def registers. It may also execute in parallel by picking non
 118   // aliasing Use and Def registers.
 119   bool hasAliasingRegisters() const;
 120
 121   const llvm::MCInstrDesc *Description; // Never nullptr.
 122   llvm::SmallVector<Operand, 8> Operands;
 123   llvm::SmallVector<Variable, 4> Variables;
 124   llvm::BitVector ImplDefRegs; // The set of aliased implicit def registers.
 125   llvm::BitVector ImplUseRegs; // The set of aliased implicit use registers.
 126   llvm::BitVector AllDefRegs;  // The set of all aliased def registers.
 127   llvm::BitVector AllUseRegs;  // The set of all aliased use registers.
 128 };
 129
 130 // Represents the assignment of a Register to an Operand.
 131 struct RegisterOperandAssignment {
 132   RegisterOperandAssignment(const Operand *Operand, llvm::MCPhysReg Reg)
 133       : Op(Operand), Reg(Reg) {}
 134
 135   const Operand *Op; // Pointer to an Explicit Register Operand.
 136   llvm::MCPhysReg Reg;
 137
 138   bool operator==(const RegisterOperandAssignment &other) const;
 139 };
 140
 141 // Represents a set of Operands that would alias through the use of some
 142 // Registers.
 143 // There are two reasons why operands would alias:
 144 // - The registers assigned to each of the operands are the same or alias each
 145 //   other (e.g. AX/AL)
 146 // - The operands are tied.
 147 struct AliasingRegisterOperands {
 148   llvm::SmallVector<RegisterOperandAssignment, 1> Defs; // Unlikely size() > 1.
 149   llvm::SmallVector<RegisterOperandAssignment, 2> Uses;
 150
 151   // True is Defs and Use contain an Implicit Operand.
 152   bool hasImplicitAliasing() const;
 153
 154   bool operator==(const AliasingRegisterOperands &other) const;
 155 };
 156
 157 // Returns all possible configurations leading Def registers of DefInstruction
 158 // to alias with Use registers of UseInstruction.
 159 struct AliasingConfigurations {
 160   AliasingConfigurations(const Instruction &DefInstruction,
 161                          const Instruction &UseInstruction);
 162
 163   bool empty() const; // True if no aliasing configuration is found.
 164   bool hasImplicitAliasing() const;
 165   void setExplicitAliasing() const;
 166
 167   const Instruction &DefInstruction;
 168   const Instruction &UseInstruction;
 169   llvm::SmallVector<AliasingRegisterOperands, 32> Configurations;
 170 };
 171
 172 // Writes MCInst to OS.
 173 // This is not assembly but the internal LLVM's name for instructions and
 174 // registers.
 175 void DumpMCInst(const llvm::MCRegisterInfo &MCRegisterInfo,
 176                 const llvm::MCInstrInfo &MCInstrInfo,
 177                 const llvm::MCInst &MCInst, llvm::raw_ostream &OS);
 178
 179 } // namespace exegesis
 180
 181 #endif // LLVM_TOOLS_LLVM_EXEGESIS_MCINSTRDESCVIEW_H