lib/CodeGen/LiveIntervalAnalysis.cpp

   1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file was developed by the LLVM research group and is distributed under
   6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the LiveInterval analysis pass which is used
  11 // by the Linear Scan Register allocator. This pass linearizes the
  12 // basic blocks of the function in DFS order and uses the
  13 // LiveVariables pass to conservatively compute live intervals for
  14 // each virtual and physical register.
  15 //
  16 //===----------------------------------------------------------------------===//
  17
  18 #define DEBUG_TYPE "liveintervals"
  19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
  20 #include "VirtRegMap.h"
  21 #include "llvm/Value.h"
  22 #include "llvm/Analysis/LoopInfo.h"
  23 #include "llvm/CodeGen/LiveVariables.h"
  24 #include "llvm/CodeGen/MachineFrameInfo.h"
  25 #include "llvm/CodeGen/MachineInstr.h"
  26 #include "llvm/CodeGen/Passes.h"
  27 #include "llvm/CodeGen/SSARegMap.h"
  28 #include "llvm/Target/MRegisterInfo.h"
  29 #include "llvm/Target/TargetInstrInfo.h"
  30 #include "llvm/Target/TargetMachine.h"
  31 #include "llvm/Support/CommandLine.h"
  32 #include "llvm/Support/Debug.h"
  33 #include "llvm/ADT/Statistic.h"
  34 #include "llvm/ADT/STLExtras.h"
  35 #include <algorithm>
  36 #include <cmath>
  37 #include <iostream>
  38 using namespace llvm;
  39
  40 namespace {
  41   RegisterAnalysis<LiveIntervals> X("liveintervals", "Live Interval Analysis");
  42
  43   static Statistic<> numIntervals
  44   ("liveintervals", "Number of original intervals");
  45
  46   static Statistic<> numIntervalsAfter
  47   ("liveintervals", "Number of intervals after coalescing");
  48
  49   static Statistic<> numJoins
  50   ("liveintervals", "Number of interval joins performed");
  51
  52   static Statistic<> numPeep
  53   ("liveintervals", "Number of identity moves eliminated after coalescing");
  54
  55   static Statistic<> numFolded
  56   ("liveintervals", "Number of loads/stores folded into instructions");
  57
  58   static cl::opt<bool>
  59   EnableJoining("join-liveintervals",
  60                 cl::desc("Join compatible live intervals"),
  61                 cl::init(true));
  62 }
  63
  64 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const
  65 {
  66   AU.addRequired<LiveVariables>();
  67   AU.addPreservedID(PHIEliminationID);
  68   AU.addRequiredID(PHIEliminationID);
  69   AU.addRequiredID(TwoAddressInstructionPassID);
  70   AU.addRequired<LoopInfo>();
  71   MachineFunctionPass::getAnalysisUsage(AU);
  72 }
  73
  74 void LiveIntervals::releaseMemory()
  75 {
  76   mi2iMap_.clear();
  77   i2miMap_.clear();
  78   r2iMap_.clear();
  79   r2rMap_.clear();
  80 }
  81
  82
  83 static bool isZeroLengthInterval(LiveInterval *li) {
  84   for (LiveInterval::Ranges::const_iterator
  85          i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
  86     if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
  87       return false;
  88   return true;
  89 }
  90
  91
  92 /// runOnMachineFunction - Register allocate the whole function
  93 ///
  94 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
  95   mf_ = &fn;
  96   tm_ = &fn.getTarget();
  97   mri_ = tm_->getRegisterInfo();
  98   tii_ = tm_->getInstrInfo();
  99   lv_ = &getAnalysis<LiveVariables>();
 100   allocatableRegs_ = mri_->getAllocatableSet(fn);
 101   r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg());
 102
 103   // If this function has any live ins, insert a dummy instruction at the
 104   // beginning of the function that we will pretend "defines" the values.  This
 105   // is to make the interval analysis simpler by providing a number.
 106   if (fn.livein_begin() != fn.livein_end()) {
 107     unsigned FirstLiveIn = fn.livein_begin()->first;
 108
 109     // Find a reg class that contains this live in.
 110     const TargetRegisterClass *RC = 0;
 111     for (MRegisterInfo::regclass_iterator RCI = mri_->regclass_begin(),
 112            E = mri_->regclass_end(); RCI != E; ++RCI)
 113       if ((*RCI)->contains(FirstLiveIn)) {
 114         RC = *RCI;
 115         break;
 116       }
 117
 118     MachineInstr *OldFirstMI = fn.begin()->begin();
 119     mri_->copyRegToReg(*fn.begin(), fn.begin()->begin(),
 120                        FirstLiveIn, FirstLiveIn, RC);
 121     assert(OldFirstMI != fn.begin()->begin() &&
 122            "copyRetToReg didn't insert anything!");
 123   }
 124
 125   // number MachineInstrs
 126   unsigned miIndex = 0;
 127   for (MachineFunction::iterator mbb = mf_->begin(), mbbEnd = mf_->end();
 128        mbb != mbbEnd; ++mbb)
 129     for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
 130          mi != miEnd; ++mi) {
 131       bool inserted = mi2iMap_.insert(std::make_pair(mi, miIndex)).second;
 132       assert(inserted && "multiple MachineInstr -> index mappings");
 133       i2miMap_.push_back(mi);
 134       miIndex += InstrSlots::NUM;
 135     }
 136
 137   // Note intervals due to live-in values.
 138   if (fn.livein_begin() != fn.livein_end()) {
 139     MachineBasicBlock *Entry = fn.begin();
 140     for (MachineFunction::livein_iterator I = fn.livein_begin(),
 141            E = fn.livein_end(); I != E; ++I) {
 142       handlePhysicalRegisterDef(Entry, Entry->begin(),
 143                                 getOrCreateInterval(I->first), 0, 0, true);
 144       for (const unsigned* AS = mri_->getAliasSet(I->first); *AS; ++AS)
 145         handlePhysicalRegisterDef(Entry, Entry->begin(),
 146                                   getOrCreateInterval(*AS), 0, 0, true);
 147     }
 148   }
 149
 150   computeIntervals();
 151
 152   numIntervals += getNumIntervals();
 153
 154   DEBUG(std::cerr << "********** INTERVALS **********\n";
 155         for (iterator I = begin(), E = end(); I != E; ++I) {
 156           I->second.print(std::cerr, mri_);
 157           std::cerr << "\n";
 158         });
 159
 160   // join intervals if requested
 161   if (EnableJoining) joinIntervals();
 162
 163   numIntervalsAfter += getNumIntervals();
 164
 165   // perform a final pass over the instructions and compute spill
 166   // weights, coalesce virtual registers and remove identity moves
 167   const LoopInfo& loopInfo = getAnalysis<LoopInfo>();
 168
 169   for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
 170        mbbi != mbbe; ++mbbi) {
 171     MachineBasicBlock* mbb = mbbi;
 172     unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock());
 173
 174     for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
 175          mii != mie; ) {
 176       // if the move will be an identity move delete it
 177       unsigned srcReg, dstReg, RegRep;
 178       if (tii_->isMoveInstr(*mii, srcReg, dstReg) &&
 179           (RegRep = rep(srcReg)) == rep(dstReg)) {
 180         // remove from def list
 181         LiveInterval &interval = getOrCreateInterval(RegRep);
 182         // remove index -> MachineInstr and
 183         // MachineInstr -> index mappings
 184         Mi2IndexMap::iterator mi2i = mi2iMap_.find(mii);
 185         if (mi2i != mi2iMap_.end()) {
 186           i2miMap_[mi2i->second/InstrSlots::NUM] = 0;
 187           mi2iMap_.erase(mi2i);
 188         }
 189         mii = mbbi->erase(mii);
 190         ++numPeep;
 191       }
 192       else {
 193         for (unsigned i = 0; i < mii->getNumOperands(); ++i) {
 194           const MachineOperand& mop = mii->getOperand(i);
 195           if (mop.isRegister() && mop.getReg() &&
 196               MRegisterInfo::isVirtualRegister(mop.getReg())) {
 197             // replace register with representative register
 198             unsigned reg = rep(mop.getReg());
 199             mii->getOperand(i).setReg(reg);
 200
 201             LiveInterval &RegInt = getInterval(reg);
 202             RegInt.weight +=
 203               (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth);
 204           }
 205         }
 206         ++mii;
 207       }
 208     }
 209   }
 210
 211   for (iterator I = begin(), E = end(); I != E; ++I) {
 212     LiveInterval &li = I->second;
 213     if (MRegisterInfo::isVirtualRegister(li.reg))
 214       // If the live interval legnth is essentially zero, i.e. in every live
 215       // range the use follows def immediately, it doesn't make sense to spill
 216       // it and hope it will be easier to allocate for this li.
 217       if (isZeroLengthInterval(&li))
 218         li.weight = float(HUGE_VAL);
 219   }
 220
 221   DEBUG(dump());
 222   return true;
 223 }
 224
 225 /// print - Implement the dump method.
 226 void LiveIntervals::print(std::ostream &O, const Module* ) const {
 227   O << "********** INTERVALS **********\n";
 228   for (const_iterator I = begin(), E = end(); I != E; ++I) {
 229     I->second.print(std::cerr, mri_);
 230     std::cerr << "\n";
 231   }
 232
 233   O << "********** MACHINEINSTRS **********\n";
 234   for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
 235        mbbi != mbbe; ++mbbi) {
 236     O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n";
 237     for (MachineBasicBlock::iterator mii = mbbi->begin(),
 238            mie = mbbi->end(); mii != mie; ++mii) {
 239       O << getInstructionIndex(mii) << '\t' << *mii;
 240     }
 241   }
 242 }
 243
 244 std::vector<LiveInterval*> LiveIntervals::
 245 addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) {
 246   // since this is called after the analysis is done we don't know if
 247   // LiveVariables is available
 248   lv_ = getAnalysisToUpdate<LiveVariables>();
 249
 250   std::vector<LiveInterval*> added;
 251
 252   assert(li.weight != HUGE_VAL &&
 253          "attempt to spill already spilled interval!");
 254
 255   DEBUG(std::cerr << "\t\t\t\tadding intervals for spills for interval: "
 256         << li << '\n');
 257
 258   const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg);
 259
 260   for (LiveInterval::Ranges::const_iterator
 261          i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) {
 262     unsigned index = getBaseIndex(i->start);
 263     unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM;
 264     for (; index != end; index += InstrSlots::NUM) {
 265       // skip deleted instructions
 266       while (index != end && !getInstructionFromIndex(index))
 267         index += InstrSlots::NUM;
 268       if (index == end) break;
 269
 270       MachineInstr *MI = getInstructionFromIndex(index);
 271
 272       // NewRegLiveIn - This instruction might have multiple uses of the spilled
 273       // register.  In this case, for the first use, keep track of the new vreg
 274       // that we reload it into.  If we see a second use, reuse this vreg
 275       // instead of creating live ranges for two reloads.
 276       unsigned NewRegLiveIn = 0;
 277
 278     for_operand:
 279       for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
 280         MachineOperand& mop = MI->getOperand(i);
 281         if (mop.isRegister() && mop.getReg() == li.reg) {
 282           if (NewRegLiveIn && mop.isUse()) {
 283             // We already emitted a reload of this value, reuse it for
 284             // subsequent operands.
 285             MI->getOperand(i).setReg(NewRegLiveIn);
 286             DEBUG(std::cerr << "\t\t\t\treused reload into reg" << NewRegLiveIn
 287                             << " for operand #" << i << '\n');
 288           } else if (MachineInstr* fmi = mri_->foldMemoryOperand(MI, i, slot)) {
 289             // Attempt to fold the memory reference into the instruction.  If we
 290             // can do this, we don't need to insert spill code.
 291             if (lv_)
 292               lv_->instructionChanged(MI, fmi);
 293             MachineBasicBlock &MBB = *MI->getParent();
 294             vrm.virtFolded(li.reg, MI, i, fmi);
 295             mi2iMap_.erase(MI);
 296             i2miMap_[index/InstrSlots::NUM] = fmi;
 297             mi2iMap_[fmi] = index;
 298             MI = MBB.insert(MBB.erase(MI), fmi);
 299             ++numFolded;
 300             // Folding the load/store can completely change the instruction in
 301             // unpredictable ways, rescan it from the beginning.
 302             goto for_operand;
 303           } else {
 304             // This is tricky. We need to add information in the interval about
 305             // the spill code so we have to use our extra load/store slots.
 306             //
 307             // If we have a use we are going to have a load so we start the
 308             // interval from the load slot onwards. Otherwise we start from the
 309             // def slot.
 310             unsigned start = (mop.isUse() ?
 311                               getLoadIndex(index) :
 312                               getDefIndex(index));
 313             // If we have a def we are going to have a store right after it so
 314             // we end the interval after the use of the next
 315             // instruction. Otherwise we end after the use of this instruction.
 316             unsigned end = 1 + (mop.isDef() ?
 317                                 getStoreIndex(index) :
 318                                 getUseIndex(index));
 319
 320             // create a new register for this spill
 321             NewRegLiveIn = mf_->getSSARegMap()->createVirtualRegister(rc);
 322             MI->getOperand(i).setReg(NewRegLiveIn);
 323             vrm.grow();
 324             vrm.assignVirt2StackSlot(NewRegLiveIn, slot);
 325             LiveInterval& nI = getOrCreateInterval(NewRegLiveIn);
 326             assert(nI.empty());
 327
 328             // the spill weight is now infinity as it
 329             // cannot be spilled again
 330             nI.weight = float(HUGE_VAL);
 331             LiveRange LR(start, end, nI.getNextValue());
 332             DEBUG(std::cerr << " +" << LR);
 333             nI.addRange(LR);
 334             added.push_back(&nI);
 335
 336             // update live variables if it is available
 337             if (lv_)
 338               lv_->addVirtualRegisterKilled(NewRegLiveIn, MI);
 339
 340             // If this is a live in, reuse it for subsequent live-ins.  If it's
 341             // a def, we can't do this.
 342             if (!mop.isUse()) NewRegLiveIn = 0;
 343
 344             DEBUG(std::cerr << "\t\t\t\tadded new interval: " << nI << '\n');
 345           }
 346         }
 347       }
 348     }
 349   }
 350
 351   return added;
 352 }
 353
 354 void LiveIntervals::printRegName(unsigned reg) const
 355 {
 356   if (MRegisterInfo::isPhysicalRegister(reg))
 357     std::cerr << mri_->getName(reg);
 358   else
 359     std::cerr << "%reg" << reg;
 360 }
 361
 362 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock* mbb,
 363                                              MachineBasicBlock::iterator mi,
 364                                              LiveInterval& interval)
 365 {
 366   DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
 367   LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
 368
 369   // Virtual registers may be defined multiple times (due to phi
 370   // elimination and 2-addr elimination).  Much of what we do only has to be
 371   // done once for the vreg.  We use an empty interval to detect the first
 372   // time we see a vreg.
 373   if (interval.empty()) {
 374     // Get the Idx of the defining instructions.
 375     unsigned defIndex = getDefIndex(getInstructionIndex(mi));
 376
 377     unsigned ValNum = interval.getNextValue();
 378     assert(ValNum == 0 && "First value in interval is not 0?");
 379     ValNum = 0;  // Clue in the optimizer.
 380
 381     // Loop over all of the blocks that the vreg is defined in.  There are
 382     // two cases we have to handle here.  The most common case is a vreg
 383     // whose lifetime is contained within a basic block.  In this case there
 384     // will be a single kill, in MBB, which comes after the definition.
 385     if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
 386       // FIXME: what about dead vars?
 387       unsigned killIdx;
 388       if (vi.Kills[0] != mi)
 389         killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1;
 390       else
 391         killIdx = defIndex+1;
 392
 393       // If the kill happens after the definition, we have an intra-block
 394       // live range.
 395       if (killIdx > defIndex) {
 396         assert(vi.AliveBlocks.empty() &&
 397                "Shouldn't be alive across any blocks!");
 398         LiveRange LR(defIndex, killIdx, ValNum);
 399         interval.addRange(LR);
 400         DEBUG(std::cerr << " +" << LR << "\n");
 401         return;
 402       }
 403     }
 404
 405     // The other case we handle is when a virtual register lives to the end
 406     // of the defining block, potentially live across some blocks, then is
 407     // live into some number of blocks, but gets killed.  Start by adding a
 408     // range that goes from this definition to the end of the defining block.
 409     LiveRange NewLR(defIndex,
 410                     getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
 411                     ValNum);
 412     DEBUG(std::cerr << " +" << NewLR);
 413     interval.addRange(NewLR);
 414
 415     // Iterate over all of the blocks that the variable is completely
 416     // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
 417     // live interval.
 418     for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) {
 419       if (vi.AliveBlocks[i]) {
 420         MachineBasicBlock* mbb = mf_->getBlockNumbered(i);
 421         if (!mbb->empty()) {
 422           LiveRange LR(getInstructionIndex(&mbb->front()),
 423                        getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
 424                        ValNum);
 425           interval.addRange(LR);
 426           DEBUG(std::cerr << " +" << LR);
 427         }
 428       }
 429     }
 430
 431     // Finally, this virtual register is live from the start of any killing
 432     // block to the 'use' slot of the killing instruction.
 433     for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
 434       MachineInstr *Kill = vi.Kills[i];
 435       LiveRange LR(getInstructionIndex(Kill->getParent()->begin()),
 436                    getUseIndex(getInstructionIndex(Kill))+1,
 437                    ValNum);
 438       interval.addRange(LR);
 439       DEBUG(std::cerr << " +" << LR);
 440     }
 441
 442   } else {
 443     // If this is the second time we see a virtual register definition, it
 444     // must be due to phi elimination or two addr elimination.  If this is
 445     // the result of two address elimination, then the vreg is the first
 446     // operand, and is a def-and-use.
 447     if (mi->getOperand(0).isRegister() &&
 448         mi->getOperand(0).getReg() == interval.reg &&
 449         mi->getOperand(0).isDef() && mi->getOperand(0).isUse()) {
 450       // If this is a two-address definition, then we have already processed
 451       // the live range.  The only problem is that we didn't realize there
 452       // are actually two values in the live interval.  Because of this we
 453       // need to take the LiveRegion that defines this register and split it
 454       // into two values.
 455       unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst));
 456       unsigned RedefIndex = getDefIndex(getInstructionIndex(mi));
 457
 458       // Delete the initial value, which should be short and continuous,
 459       // becuase the 2-addr copy must be in the same MBB as the redef.
 460       interval.removeRange(DefIndex, RedefIndex);
 461
 462       LiveRange LR(DefIndex, RedefIndex, interval.getNextValue());
 463       DEBUG(std::cerr << " replace range with " << LR);
 464       interval.addRange(LR);
 465
 466       // If this redefinition is dead, we need to add a dummy unit live
 467       // range covering the def slot.
 468       if (lv_->RegisterDefIsDead(mi, interval.reg))
 469         interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0));
 470
 471       DEBUG(std::cerr << "RESULT: " << interval);
 472
 473     } else {
 474       // Otherwise, this must be because of phi elimination.  If this is the
 475       // first redefinition of the vreg that we have seen, go back and change
 476       // the live range in the PHI block to be a different value number.
 477       if (interval.containsOneValue()) {
 478         assert(vi.Kills.size() == 1 &&
 479                "PHI elimination vreg should have one kill, the PHI itself!");
 480
 481         // Remove the old range that we now know has an incorrect number.
 482         MachineInstr *Killer = vi.Kills[0];
 483         unsigned Start = getInstructionIndex(Killer->getParent()->begin());
 484         unsigned End = getUseIndex(getInstructionIndex(Killer))+1;
 485         DEBUG(std::cerr << "Removing [" << Start << "," << End << "] from: "
 486               << interval << "\n");
 487         interval.removeRange(Start, End);
 488         DEBUG(std::cerr << "RESULT: " << interval);
 489
 490         // Replace the interval with one of a NEW value number.
 491         LiveRange LR(Start, End, interval.getNextValue());
 492         DEBUG(std::cerr << " replace range with " << LR);
 493         interval.addRange(LR);
 494         DEBUG(std::cerr << "RESULT: " << interval);
 495       }
 496
 497       // In the case of PHI elimination, each variable definition is only
 498       // live until the end of the block.  We've already taken care of the
 499       // rest of the live range.
 500       unsigned defIndex = getDefIndex(getInstructionIndex(mi));
 501       LiveRange LR(defIndex,
 502                    getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
 503                    interval.getNextValue());
 504       interval.addRange(LR);
 505       DEBUG(std::cerr << " +" << LR);
 506     }
 507   }
 508
 509   DEBUG(std::cerr << '\n');
 510 }
 511
 512 void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
 513                                               MachineBasicBlock::iterator mi,
 514                                               LiveInterval& interval,
 515                                               unsigned SrcReg, unsigned DestReg,
 516                                               bool isLiveIn)
 517 {
 518   // A physical register cannot be live across basic block, so its
 519   // lifetime must end somewhere in its defining basic block.
 520   DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
 521   typedef LiveVariables::killed_iterator KillIter;
 522
 523   unsigned baseIndex = getInstructionIndex(mi);
 524   unsigned start = getDefIndex(baseIndex);
 525   unsigned end = start;
 526
 527   // If it is not used after definition, it is considered dead at
 528   // the instruction defining it. Hence its interval is:
 529   // [defSlot(def), defSlot(def)+1)
 530   if (lv_->RegisterDefIsDead(mi, interval.reg)) {
 531     DEBUG(std::cerr << " dead");
 532     end = getDefIndex(start) + 1;
 533     goto exit;
 534   }
 535
 536   // If it is not dead on definition, it must be killed by a
 537   // subsequent instruction. Hence its interval is:
 538   // [defSlot(def), useSlot(kill)+1)
 539   while (++mi != MBB->end()) {
 540     baseIndex += InstrSlots::NUM;
 541     if (lv_->KillsRegister(mi, interval.reg)) {
 542       DEBUG(std::cerr << " killed");
 543       end = getUseIndex(baseIndex) + 1;
 544       goto exit;
 545     }
 546   }
 547
 548   // The only case we should have a dead physreg here without a killing or
 549   // instruction where we know it's dead is if it is live-in to the function
 550   // and never used.
 551   assert(isLiveIn && "physreg was not killed in defining block!");
 552   end = getDefIndex(start) + 1;  // It's dead.
 553
 554 exit:
 555   assert(start < end && "did not find end of interval?");
 556
 557   // Finally, if this is defining a new range for the physical register, and if
 558   // that physreg is just a copy from a vreg, and if THAT vreg was a copy from
 559   // the physreg, then the new fragment has the same value as the one copied
 560   // into the vreg.
 561   if (interval.reg == DestReg && !interval.empty() &&
 562       MRegisterInfo::isVirtualRegister(SrcReg)) {
 563
 564     // Get the live interval for the vreg, see if it is defined by a copy.
 565     LiveInterval &SrcInterval = getOrCreateInterval(SrcReg);
 566
 567     if (SrcInterval.containsOneValue()) {
 568       assert(!SrcInterval.empty() && "Can't contain a value and be empty!");
 569
 570       // Get the first index of the first range.  Though the interval may have
 571       // multiple liveranges in it, we only check the first.
 572       unsigned StartIdx = SrcInterval.begin()->start;
 573       MachineInstr *SrcDefMI = getInstructionFromIndex(StartIdx);
 574
 575       // Check to see if the vreg was defined by a copy instruction, and that
 576       // the source was this physreg.
 577       unsigned VRegSrcSrc, VRegSrcDest;
 578       if (tii_->isMoveInstr(*SrcDefMI, VRegSrcSrc, VRegSrcDest) &&
 579           SrcReg == VRegSrcDest && VRegSrcSrc == DestReg) {
 580         // Okay, now we know that the vreg was defined by a copy from this
 581         // physreg.  Find the value number being copied and use it as the value
 582         // for this range.
 583         const LiveRange *DefRange = interval.getLiveRangeContaining(StartIdx-1);
 584         if (DefRange) {
 585           LiveRange LR(start, end, DefRange->ValId);
 586           interval.addRange(LR);
 587           DEBUG(std::cerr << " +" << LR << '\n');
 588           return;
 589         }
 590       }
 591     }
 592   }
 593
 594
 595   LiveRange LR(start, end, interval.getNextValue());
 596   interval.addRange(LR);
 597   DEBUG(std::cerr << " +" << LR << '\n');
 598 }
 599
 600 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
 601                                       MachineBasicBlock::iterator MI,
 602                                       unsigned reg) {
 603   if (MRegisterInfo::isVirtualRegister(reg))
 604     handleVirtualRegisterDef(MBB, MI, getOrCreateInterval(reg));
 605   else if (allocatableRegs_[reg]) {
 606     unsigned SrcReg = 0, DestReg = 0;
 607     if (!tii_->isMoveInstr(*MI, SrcReg, DestReg))
 608       SrcReg = DestReg = 0;
 609
 610     handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(reg),
 611                               SrcReg, DestReg);
 612     for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS)
 613       handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(*AS),
 614                                 SrcReg, DestReg);
 615   }
 616 }
 617
 618 /// computeIntervals - computes the live intervals for virtual
 619 /// registers. for some ordering of the machine instructions [1,N] a
 620 /// live interval is an interval [i, j) where 1 <= i <= j < N for
 621 /// which a variable is live
 622 void LiveIntervals::computeIntervals()
 623 {
 624   DEBUG(std::cerr << "********** COMPUTING LIVE INTERVALS **********\n");
 625   DEBUG(std::cerr << "********** Function: "
 626         << ((Value*)mf_->getFunction())->getName() << '\n');
 627   bool IgnoreFirstInstr = mf_->livein_begin() != mf_->livein_end();
 628
 629   for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
 630        I != E; ++I) {
 631     MachineBasicBlock* mbb = I;
 632     DEBUG(std::cerr << ((Value*)mbb->getBasicBlock())->getName() << ":\n");
 633
 634     MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
 635     if (IgnoreFirstInstr) { ++mi; IgnoreFirstInstr = false; }
 636     for (; mi != miEnd; ++mi) {
 637       const TargetInstrDescriptor& tid =
 638         tm_->getInstrInfo()->get(mi->getOpcode());
 639       DEBUG(std::cerr << getInstructionIndex(mi) << "\t" << *mi);
 640
 641       // handle implicit defs
 642       if (tid.ImplicitDefs) {
 643         for (const unsigned* id = tid.ImplicitDefs; *id; ++id)
 644           handleRegisterDef(mbb, mi, *id);
 645       }
 646
 647       // handle explicit defs
 648       for (int i = mi->getNumOperands() - 1; i >= 0; --i) {
 649         MachineOperand& mop = mi->getOperand(i);
 650         // handle register defs - build intervals
 651         if (mop.isRegister() && mop.getReg() && mop.isDef())
 652           handleRegisterDef(mbb, mi, mop.getReg());
 653       }
 654     }
 655   }
 656 }
 657
 658 /// IntA is defined as a copy from IntB and we know it only has one value
 659 /// number.  If all of the places that IntA and IntB overlap are defined by
 660 /// copies from IntA to IntB, we know that these two ranges can really be
 661 /// merged if we adjust the value numbers.  If it is safe, adjust the value
 662 /// numbers and return true, allowing coalescing to occur.
 663 bool LiveIntervals::
 664 AdjustIfAllOverlappingRangesAreCopiesFrom(LiveInterval &IntA,
 665                                           LiveInterval &IntB,
 666                                           unsigned CopyIdx) {
 667   std::vector<LiveRange*> Ranges;
 668   IntA.getOverlapingRanges(IntB, CopyIdx, Ranges);
 669
 670   assert(!Ranges.empty() && "Why didn't we do a simple join of this?");
 671
 672   unsigned IntBRep = rep(IntB.reg);
 673
 674   // Check to see if all of the overlaps (entries in Ranges) are defined by a
 675   // copy from IntA.  If not, exit.
 676   for (unsigned i = 0, e = Ranges.size(); i != e; ++i) {
 677     unsigned Idx = Ranges[i]->start;
 678     MachineInstr *MI = getInstructionFromIndex(Idx);
 679     unsigned SrcReg, DestReg;
 680     if (!tii_->isMoveInstr(*MI, SrcReg, DestReg)) return false;
 681
 682     // If this copy isn't actually defining this range, it must be a live
 683     // range spanning basic blocks or something.
 684     if (rep(DestReg) != rep(IntA.reg)) return false;
 685
 686     // Check to see if this is coming from IntB.  If not, bail out.
 687     if (rep(SrcReg) != IntBRep) return false;
 688   }
 689
 690   // Okay, we can change this one.  Get the IntB value number that IntA is
 691   // copied from.
 692   unsigned ActualValNo = IntA.getLiveRangeContaining(CopyIdx-1)->ValId;
 693
 694   // Change all of the value numbers to the same as what we IntA is copied from.
 695   for (unsigned i = 0, e = Ranges.size(); i != e; ++i)
 696     Ranges[i]->ValId = ActualValNo;
 697
 698   return true;
 699 }
 700
 701 void LiveIntervals::joinIntervalsInMachineBB(MachineBasicBlock *MBB) {
 702   DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n");
 703
 704   for (MachineBasicBlock::iterator mi = MBB->begin(), mie = MBB->end();
 705        mi != mie; ++mi) {
 706     DEBUG(std::cerr << getInstructionIndex(mi) << '\t' << *mi);
 707
 708     // we only join virtual registers with allocatable
 709     // physical registers since we do not have liveness information
 710     // on not allocatable physical registers
 711     unsigned SrcReg, DestReg;
 712     if (tii_->isMoveInstr(*mi, SrcReg, DestReg) &&
 713         (MRegisterInfo::isVirtualRegister(SrcReg) || allocatableRegs_[SrcReg])&&
 714         (MRegisterInfo::isVirtualRegister(DestReg)||allocatableRegs_[DestReg])){
 715
 716       // Get representative registers.
 717       SrcReg = rep(SrcReg);
 718       DestReg = rep(DestReg);
 719
 720       // If they are already joined we continue.
 721       if (SrcReg == DestReg)
 722         continue;
 723
 724       // If they are both physical registers, we cannot join them.
 725       if (MRegisterInfo::isPhysicalRegister(SrcReg) &&
 726           MRegisterInfo::isPhysicalRegister(DestReg))
 727         continue;
 728
 729       // If they are not of the same register class, we cannot join them.
 730       if (differingRegisterClasses(SrcReg, DestReg))
 731         continue;
 732
 733       LiveInterval &SrcInt = getInterval(SrcReg);
 734       LiveInterval &DestInt = getInterval(DestReg);
 735       assert(SrcInt.reg == SrcReg && DestInt.reg == DestReg &&
 736              "Register mapping is horribly broken!");
 737
 738       DEBUG(std::cerr << "\t\tInspecting " << SrcInt << " and " << DestInt
 739                       << ": ");
 740
 741       // If two intervals contain a single value and are joined by a copy, it
 742       // does not matter if the intervals overlap, they can always be joined.
 743       bool Joinable = SrcInt.containsOneValue() && DestInt.containsOneValue();
 744
 745       unsigned MIDefIdx = getDefIndex(getInstructionIndex(mi));
 746
 747       // If the intervals think that this is joinable, do so now.
 748       if (!Joinable && DestInt.joinable(SrcInt, MIDefIdx))
 749         Joinable = true;
 750
 751       // If DestInt is actually a copy from SrcInt (which we know) that is used
 752       // to define another value of SrcInt, we can change the other range of
 753       // SrcInt to be the value of the range that defines DestInt, allowing a
 754       // coalesce.
 755       if (!Joinable && DestInt.containsOneValue() &&
 756           AdjustIfAllOverlappingRangesAreCopiesFrom(SrcInt, DestInt, MIDefIdx))
 757         Joinable = true;
 758
 759       if (!Joinable || overlapsAliases(&SrcInt, &DestInt)) {
 760         DEBUG(std::cerr << "Interference!\n");
 761       } else {
 762         DestInt.join(SrcInt, MIDefIdx);
 763         DEBUG(std::cerr << "Joined.  Result = " << DestInt << "\n");
 764
 765         if (!MRegisterInfo::isPhysicalRegister(SrcReg)) {
 766           r2iMap_.erase(SrcReg);
 767           r2rMap_[SrcReg] = DestReg;
 768         } else {
 769           // Otherwise merge the data structures the other way so we don't lose
 770           // the physreg information.
 771           r2rMap_[DestReg] = SrcReg;
 772           DestInt.reg = SrcReg;
 773           SrcInt.swap(DestInt);
 774           r2iMap_.erase(DestReg);
 775         }
 776         ++numJoins;
 777       }
 778     }
 779   }
 780 }
 781
 782 namespace {
 783   // DepthMBBCompare - Comparison predicate that sort first based on the loop
 784   // depth of the basic block (the unsigned), and then on the MBB number.
 785   struct DepthMBBCompare {
 786     typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
 787     bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
 788       if (LHS.first > RHS.first) return true;   // Deeper loops first
 789       return LHS.first == RHS.first &&
 790         LHS.second->getNumber() < RHS.second->getNumber();
 791     }
 792   };
 793 }
 794
 795 void LiveIntervals::joinIntervals() {
 796   DEBUG(std::cerr << "********** JOINING INTERVALS ***********\n");
 797
 798   const LoopInfo &LI = getAnalysis<LoopInfo>();
 799   if (LI.begin() == LI.end()) {
 800     // If there are no loops in the function, join intervals in function order.
 801     for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
 802          I != E; ++I)
 803       joinIntervalsInMachineBB(I);
 804   } else {
 805     // Otherwise, join intervals in inner loops before other intervals.
 806     // Unfortunately we can't just iterate over loop hierarchy here because
 807     // there may be more MBB's than BB's.  Collect MBB's for sorting.
 808     std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
 809     for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
 810          I != E; ++I)
 811       MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I));
 812
 813     // Sort by loop depth.
 814     std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
 815
 816     // Finally, join intervals in loop nest order.
 817     for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
 818       joinIntervalsInMachineBB(MBBs[i].second);
 819   }
 820
 821   DEBUG(std::cerr << "*** Register mapping ***\n");
 822   DEBUG(for (int i = 0, e = r2rMap_.size(); i != e; ++i)
 823           if (r2rMap_[i])
 824              std::cerr << "  reg " << i << " -> reg " << r2rMap_[i] << "\n");
 825 }
 826
 827 /// Return true if the two specified registers belong to different register
 828 /// classes.  The registers may be either phys or virt regs.
 829 bool LiveIntervals::differingRegisterClasses(unsigned RegA,
 830                                              unsigned RegB) const {
 831
 832   // Get the register classes for the first reg.
 833   if (MRegisterInfo::isPhysicalRegister(RegA)) {
 834     assert(MRegisterInfo::isVirtualRegister(RegB) &&
 835            "Shouldn't consider two physregs!");
 836     return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA);
 837   }
 838
 839   // Compare against the regclass for the second reg.
 840   const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA);
 841   if (MRegisterInfo::isVirtualRegister(RegB))
 842     return RegClass != mf_->getSSARegMap()->getRegClass(RegB);
 843   else
 844     return !RegClass->contains(RegB);
 845 }
 846
 847 bool LiveIntervals::overlapsAliases(const LiveInterval *LHS,
 848                                     const LiveInterval *RHS) const {
 849   if (!MRegisterInfo::isPhysicalRegister(LHS->reg)) {
 850     if (!MRegisterInfo::isPhysicalRegister(RHS->reg))
 851       return false;   // vreg-vreg merge has no aliases!
 852     std::swap(LHS, RHS);
 853   }
 854
 855   assert(MRegisterInfo::isPhysicalRegister(LHS->reg) &&
 856          MRegisterInfo::isVirtualRegister(RHS->reg) &&
 857          "first interval must describe a physical register");
 858
 859   for (const unsigned *AS = mri_->getAliasSet(LHS->reg); *AS; ++AS)
 860     if (RHS->overlaps(getInterval(*AS)))
 861       return true;
 862
 863   return false;
 864 }
 865
 866 LiveInterval LiveIntervals::createInterval(unsigned reg) {
 867   float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
 868                        (float)HUGE_VAL :0.0F;
 869   return LiveInterval(reg, Weight);
 870 }