include/llvm/MCA/Stages/ExecuteStage.h

   1 //===---------------------- ExecuteStage.h ----------------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 /// \file
   9 ///
  10 /// This file defines the execution stage of a default instruction pipeline.
  11 ///
  12 /// The ExecuteStage is responsible for managing the hardware scheduler
  13 /// and issuing notifications that an instruction has been executed.
  14 ///
  15 //===----------------------------------------------------------------------===//
  16
  17 #ifndef LLVM_MCA_EXECUTE_STAGE_H
  18 #define LLVM_MCA_EXECUTE_STAGE_H
  19
  20 #include "llvm/ADT/ArrayRef.h"
  21 #include "llvm/MCA/HardwareUnits/Scheduler.h"
  22 #include "llvm/MCA/Instruction.h"
  23 #include "llvm/MCA/Stages/Stage.h"
  24
  25 namespace llvm {
  26 namespace mca {
  27
  28 class ExecuteStage final : public Stage {
  29   Scheduler &HWS;
  30
  31   Error issueInstruction(InstRef &IR);
  32
  33   // Called at the beginning of each cycle to issue already dispatched
  34   // instructions to the underlying pipelines.
  35   Error issueReadyInstructions();
  36
  37   // Used to notify instructions eliminated at register renaming stage.
  38   Error handleInstructionEliminated(InstRef &IR);
  39
  40   ExecuteStage(const ExecuteStage &Other) = delete;
  41   ExecuteStage &operator=(const ExecuteStage &Other) = delete;
  42
  43 public:
  44   ExecuteStage(Scheduler &S) : Stage(), HWS(S) {}
  45
  46   // This stage works under the assumption that the Pipeline will eventually
  47   // execute a retire stage. We don't need to check if pipelines and/or
  48   // schedulers have instructions to process, because those instructions are
  49   // also tracked by the retire control unit. That means,
  50   // RetireControlUnit::hasWorkToComplete() is responsible for checking if there
  51   // are still instructions in-flight in the out-of-order backend.
  52   bool hasWorkToComplete() const override { return false; }
  53   bool isAvailable(const InstRef &IR) const override;
  54
  55   // Notifies the scheduler that a new cycle just started.
  56   //
  57   // This method notifies the scheduler that a new cycle started.
  58   // This method is also responsible for notifying listeners about instructions
  59   // state changes, and processor resources freed by the scheduler.
  60   // Instructions that transitioned to the 'Executed' state are automatically
  61   // moved to the next stage (i.e. RetireStage).
  62   Error cycleStart() override;
  63   Error execute(InstRef &IR) override;
  64
  65   void notifyInstructionIssued(
  66       const InstRef &IR,
  67       MutableArrayRef<std::pair<ResourceRef, ResourceCycles>> Used) const;
  68   void notifyInstructionExecuted(const InstRef &IR) const;
  69   void notifyInstructionReady(const InstRef &IR) const;
  70   void notifyResourceAvailable(const ResourceRef &RR) const;
  71
  72   // Notify listeners that buffered resources have been consumed or freed.
  73   void notifyReservedOrReleasedBuffers(const InstRef &IR, bool Reserved) const;
  74 };
  75
  76 } // namespace mca
  77 } // namespace llvm
  78
  79 #endif // LLVM_MCA_EXECUTE_STAGE_H