lib/CodeGen/LiveRangeEdit.cpp

   1 //===-- LiveRangeEdit.cpp - Basic tools for editing a register live range -===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // The LiveRangeEdit class represents changes done to a virtual register when it
  10 // is spilled or split.
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "llvm/CodeGen/LiveRangeEdit.h"
  14 #include "llvm/ADT/Statistic.h"
  15 #include "llvm/CodeGen/CalcSpillWeights.h"
  16 #include "llvm/CodeGen/LiveIntervals.h"
  17 #include "llvm/CodeGen/MachineRegisterInfo.h"
  18 #include "llvm/CodeGen/TargetInstrInfo.h"
  19 #include "llvm/CodeGen/VirtRegMap.h"
  20 #include "llvm/Support/Debug.h"
  21 #include "llvm/Support/raw_ostream.h"
  22
  23 using namespace llvm;
  24
  25 #define DEBUG_TYPE "regalloc"
  26
  27 STATISTIC(NumDCEDeleted,     "Number of instructions deleted by DCE");
  28 STATISTIC(NumDCEFoldedLoads, "Number of single use loads folded after DCE");
  29 STATISTIC(NumFracRanges,     "Number of live ranges fractured by DCE");
  30
  31 void LiveRangeEdit::Delegate::anchor() { }
  32
  33 LiveInterval &LiveRangeEdit::createEmptyIntervalFrom(unsigned OldReg,
  34                                                      bool createSubRanges) {
  35   unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
  36   if (VRM)
  37     VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
  38
  39   LiveInterval &LI = LIS.createEmptyInterval(VReg);
  40   if (Parent && !Parent->isSpillable())
  41     LI.markNotSpillable();
  42   if (createSubRanges) {
  43     // Create empty subranges if the OldReg's interval has them. Do not create
  44     // the main range here---it will be constructed later after the subranges
  45     // have been finalized.
  46     LiveInterval &OldLI = LIS.getInterval(OldReg);
  47     VNInfo::Allocator &Alloc = LIS.getVNInfoAllocator();
  48     for (LiveInterval::SubRange &S : OldLI.subranges())
  49       LI.createSubRange(Alloc, S.LaneMask);
  50   }
  51   return LI;
  52 }
  53
  54 unsigned LiveRangeEdit::createFrom(unsigned OldReg) {
  55   unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
  56   if (VRM) {
  57     VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
  58   }
  59   // FIXME: Getting the interval here actually computes it.
  60   // In theory, this may not be what we want, but in practice
  61   // the createEmptyIntervalFrom API is used when this is not
  62   // the case. Generally speaking we just want to annotate the
  63   // LiveInterval when it gets created but we cannot do that at
  64   // the moment.
  65   if (Parent && !Parent->isSpillable())
  66     LIS.getInterval(VReg).markNotSpillable();
  67   return VReg;
  68 }
  69
  70 bool LiveRangeEdit::checkRematerializable(VNInfo *VNI,
  71                                           const MachineInstr *DefMI,
  72                                           AliasAnalysis *aa) {
  73   assert(DefMI && "Missing instruction");
  74   ScannedRemattable = true;
  75   if (!TII.isTriviallyReMaterializable(*DefMI, aa))
  76     return false;
  77   Remattable.insert(VNI);
  78   return true;
  79 }
  80
  81 void LiveRangeEdit::scanRemattable(AliasAnalysis *aa) {
  82   for (VNInfo *VNI : getParent().valnos) {
  83     if (VNI->isUnused())
  84       continue;
  85     unsigned Original = VRM->getOriginal(getReg());
  86     LiveInterval &OrigLI = LIS.getInterval(Original);
  87     VNInfo *OrigVNI = OrigLI.getVNInfoAt(VNI->def);
  88     if (!OrigVNI)
  89       continue;
  90     MachineInstr *DefMI = LIS.getInstructionFromIndex(OrigVNI->def);
  91     if (!DefMI)
  92       continue;
  93     checkRematerializable(OrigVNI, DefMI, aa);
  94   }
  95   ScannedRemattable = true;
  96 }
  97
  98 bool LiveRangeEdit::anyRematerializable(AliasAnalysis *aa) {
  99   if (!ScannedRemattable)
 100     scanRemattable(aa);
 101   return !Remattable.empty();
 102 }
 103
 104 /// allUsesAvailableAt - Return true if all registers used by OrigMI at
 105 /// OrigIdx are also available with the same value at UseIdx.
 106 bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI,
 107                                        SlotIndex OrigIdx,
 108                                        SlotIndex UseIdx) const {
 109   OrigIdx = OrigIdx.getRegSlot(true);
 110   UseIdx = UseIdx.getRegSlot(true);
 111   for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) {
 112     const MachineOperand &MO = OrigMI->getOperand(i);
 113     if (!MO.isReg() || !MO.getReg() || !MO.readsReg())
 114       continue;
 115
 116     // We can't remat physreg uses, unless it is a constant.
 117     if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
 118       if (MRI.isConstantPhysReg(MO.getReg()))
 119         continue;
 120       return false;
 121     }
 122
 123     LiveInterval &li = LIS.getInterval(MO.getReg());
 124     const VNInfo *OVNI = li.getVNInfoAt(OrigIdx);
 125     if (!OVNI)
 126       continue;
 127
 128     // Don't allow rematerialization immediately after the original def.
 129     // It would be incorrect if OrigMI redefines the register.
 130     // See PR14098.
 131     if (SlotIndex::isSameInstr(OrigIdx, UseIdx))
 132       return false;
 133
 134     if (OVNI != li.getVNInfoAt(UseIdx))
 135       return false;
 136   }
 137   return true;
 138 }
 139
 140 bool LiveRangeEdit::canRematerializeAt(Remat &RM, VNInfo *OrigVNI,
 141                                        SlotIndex UseIdx, bool cheapAsAMove) {
 142   assert(ScannedRemattable && "Call anyRematerializable first");
 143
 144   // Use scanRemattable info.
 145   if (!Remattable.count(OrigVNI))
 146     return false;
 147
 148   // No defining instruction provided.
 149   SlotIndex DefIdx;
 150   assert(RM.OrigMI && "No defining instruction for remattable value");
 151   DefIdx = LIS.getInstructionIndex(*RM.OrigMI);
 152
 153   // If only cheap remats were requested, bail out early.
 154   if (cheapAsAMove && !TII.isAsCheapAsAMove(*RM.OrigMI))
 155     return false;
 156
 157   // Verify that all used registers are available with the same values.
 158   if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
 159     return false;
 160
 161   return true;
 162 }
 163
 164 SlotIndex LiveRangeEdit::rematerializeAt(MachineBasicBlock &MBB,
 165                                          MachineBasicBlock::iterator MI,
 166                                          unsigned DestReg,
 167                                          const Remat &RM,
 168                                          const TargetRegisterInfo &tri,
 169                                          bool Late) {
 170   assert(RM.OrigMI && "Invalid remat");
 171   TII.reMaterialize(MBB, MI, DestReg, 0, *RM.OrigMI, tri);
 172   // DestReg of the cloned instruction cannot be Dead. Set isDead of DestReg
 173   // to false anyway in case the isDead flag of RM.OrigMI's dest register
 174   // is true.
 175   (*--MI).getOperand(0).setIsDead(false);
 176   Rematted.insert(RM.ParentVNI);
 177   return LIS.getSlotIndexes()->insertMachineInstrInMaps(*MI, Late).getRegSlot();
 178 }
 179
 180 void LiveRangeEdit::eraseVirtReg(unsigned Reg) {
 181   if (TheDelegate && TheDelegate->LRE_CanEraseVirtReg(Reg))
 182     LIS.removeInterval(Reg);
 183 }
 184
 185 bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
 186                                SmallVectorImpl<MachineInstr*> &Dead) {
 187   MachineInstr *DefMI = nullptr, *UseMI = nullptr;
 188
 189   // Check that there is a single def and a single use.
 190   for (MachineOperand &MO : MRI.reg_nodbg_operands(LI->reg)) {
 191     MachineInstr *MI = MO.getParent();
 192     if (MO.isDef()) {
 193       if (DefMI && DefMI != MI)
 194         return false;
 195       if (!MI->canFoldAsLoad())
 196         return false;
 197       DefMI = MI;
 198     } else if (!MO.isUndef()) {
 199       if (UseMI && UseMI != MI)
 200         return false;
 201       // FIXME: Targets don't know how to fold subreg uses.
 202       if (MO.getSubReg())
 203         return false;
 204       UseMI = MI;
 205     }
 206   }
 207   if (!DefMI || !UseMI)
 208     return false;
 209
 210   // Since we're moving the DefMI load, make sure we're not extending any live
 211   // ranges.
 212   if (!allUsesAvailableAt(DefMI, LIS.getInstructionIndex(*DefMI),
 213                           LIS.getInstructionIndex(*UseMI)))
 214     return false;
 215
 216   // We also need to make sure it is safe to move the load.
 217   // Assume there are stores between DefMI and UseMI.
 218   bool SawStore = true;
 219   if (!DefMI->isSafeToMove(nullptr, SawStore))
 220     return false;
 221
 222   LLVM_DEBUG(dbgs() << "Try to fold single def: " << *DefMI
 223                     << "       into single use: " << *UseMI);
 224
 225   SmallVector<unsigned, 8> Ops;
 226   if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second)
 227     return false;
 228
 229   MachineInstr *FoldMI = TII.foldMemoryOperand(*UseMI, Ops, *DefMI, &LIS);
 230   if (!FoldMI)
 231     return false;
 232   LLVM_DEBUG(dbgs() << "                folded: " << *FoldMI);
 233   LIS.ReplaceMachineInstrInMaps(*UseMI, *FoldMI);
 234   UseMI->eraseFromParent();
 235   DefMI->addRegisterDead(LI->reg, nullptr);
 236   Dead.push_back(DefMI);
 237   ++NumDCEFoldedLoads;
 238   return true;
 239 }
 240
 241 bool LiveRangeEdit::useIsKill(const LiveInterval &LI,
 242                               const MachineOperand &MO) const {
 243   const MachineInstr &MI = *MO.getParent();
 244   SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
 245   if (LI.Query(Idx).isKill())
 246     return true;
 247   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
 248   unsigned SubReg = MO.getSubReg();
 249   LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
 250   for (const LiveInterval::SubRange &S : LI.subranges()) {
 251     if ((S.LaneMask & LaneMask).any() && S.Query(Idx).isKill())
 252       return true;
 253   }
 254   return false;
 255 }
 256
 257 /// Find all live intervals that need to shrink, then remove the instruction.
 258 void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink,
 259                                      AliasAnalysis *AA) {
 260   assert(MI->allDefsAreDead() && "Def isn't really dead");
 261   SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
 262
 263   // Never delete a bundled instruction.
 264   if (MI->isBundled()) {
 265     return;
 266   }
 267   // Never delete inline asm.
 268   if (MI->isInlineAsm()) {
 269     LLVM_DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI);
 270     return;
 271   }
 272
 273   // Use the same criteria as DeadMachineInstructionElim.
 274   bool SawStore = false;
 275   if (!MI->isSafeToMove(nullptr, SawStore)) {
 276     LLVM_DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI);
 277     return;
 278   }
 279
 280   LLVM_DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI);
 281
 282   // Collect virtual registers to be erased after MI is gone.
 283   SmallVector<unsigned, 8> RegsToErase;
 284   bool ReadsPhysRegs = false;
 285   bool isOrigDef = false;
 286   unsigned Dest;
 287   // Only optimize rematerialize case when the instruction has one def, since
 288   // otherwise we could leave some dead defs in the code.  This case is
 289   // extremely rare.
 290   if (VRM && MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
 291       MI->getDesc().getNumDefs() == 1) {
 292     Dest = MI->getOperand(0).getReg();
 293     unsigned Original = VRM->getOriginal(Dest);
 294     LiveInterval &OrigLI = LIS.getInterval(Original);
 295     VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
 296     // The original live-range may have been shrunk to
 297     // an empty live-range. It happens when it is dead, but
 298     // we still keep it around to be able to rematerialize
 299     // other values that depend on it.
 300     if (OrigVNI)
 301       isOrigDef = SlotIndex::isSameInstr(OrigVNI->def, Idx);
 302   }
 303
 304   // Check for live intervals that may shrink
 305   for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
 306          MOE = MI->operands_end(); MOI != MOE; ++MOI) {
 307     if (!MOI->isReg())
 308       continue;
 309     unsigned Reg = MOI->getReg();
 310     if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
 311       // Check if MI reads any unreserved physregs.
 312       if (Reg && MOI->readsReg() && !MRI.isReserved(Reg))
 313         ReadsPhysRegs = true;
 314       else if (MOI->isDef())
 315         LIS.removePhysRegDefAt(Reg, Idx);
 316       continue;
 317     }
 318     LiveInterval &LI = LIS.getInterval(Reg);
 319
 320     // Shrink read registers, unless it is likely to be expensive and
 321     // unlikely to change anything. We typically don't want to shrink the
 322     // PIC base register that has lots of uses everywhere.
 323     // Always shrink COPY uses that probably come from live range splitting.
 324     if ((MI->readsVirtualRegister(Reg) && (MI->isCopy() || MOI->isDef())) ||
 325         (MOI->readsReg() && (MRI.hasOneNonDBGUse(Reg) || useIsKill(LI, *MOI))))
 326       ToShrink.insert(&LI);
 327
 328     // Remove defined value.
 329     if (MOI->isDef()) {
 330       if (TheDelegate && LI.getVNInfoAt(Idx) != nullptr)
 331         TheDelegate->LRE_WillShrinkVirtReg(LI.reg);
 332       LIS.removeVRegDefAt(LI, Idx);
 333       if (LI.empty())
 334         RegsToErase.push_back(Reg);
 335     }
 336   }
 337
 338   // Currently, we don't support DCE of physreg live ranges. If MI reads
 339   // any unreserved physregs, don't erase the instruction, but turn it into
 340   // a KILL instead. This way, the physreg live ranges don't end up
 341   // dangling.
 342   // FIXME: It would be better to have something like shrinkToUses() for
 343   // physregs. That could potentially enable more DCE and it would free up
 344   // the physreg. It would not happen often, though.
 345   if (ReadsPhysRegs) {
 346     MI->setDesc(TII.get(TargetOpcode::KILL));
 347     // Remove all operands that aren't physregs.
 348     for (unsigned i = MI->getNumOperands(); i; --i) {
 349       const MachineOperand &MO = MI->getOperand(i-1);
 350       if (MO.isReg() && TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
 351         continue;
 352       MI->RemoveOperand(i-1);
 353     }
 354     LLVM_DEBUG(dbgs() << "Converted physregs to:\t" << *MI);
 355   } else {
 356     // If the dest of MI is an original reg and MI is reMaterializable,
 357     // don't delete the inst. Replace the dest with a new reg, and keep
 358     // the inst for remat of other siblings. The inst is saved in
 359     // LiveRangeEdit::DeadRemats and will be deleted after all the
 360     // allocations of the func are done.
 361     if (isOrigDef && DeadRemats && TII.isTriviallyReMaterializable(*MI, AA)) {
 362       LiveInterval &NewLI = createEmptyIntervalFrom(Dest, false);
 363       VNInfo *VNI = NewLI.getNextValue(Idx, LIS.getVNInfoAllocator());
 364       NewLI.addSegment(LiveInterval::Segment(Idx, Idx.getDeadSlot(), VNI));
 365       pop_back();
 366       DeadRemats->insert(MI);
 367       const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
 368       MI->substituteRegister(Dest, NewLI.reg, 0, TRI);
 369       MI->getOperand(0).setIsDead(true);
 370     } else {
 371       if (TheDelegate)
 372         TheDelegate->LRE_WillEraseInstruction(MI);
 373       LIS.RemoveMachineInstrFromMaps(*MI);
 374       MI->eraseFromParent();
 375       ++NumDCEDeleted;
 376     }
 377   }
 378
 379   // Erase any virtregs that are now empty and unused. There may be <undef>
 380   // uses around. Keep the empty live range in that case.
 381   for (unsigned i = 0, e = RegsToErase.size(); i != e; ++i) {
 382     unsigned Reg = RegsToErase[i];
 383     if (LIS.hasInterval(Reg) && MRI.reg_nodbg_empty(Reg)) {
 384       ToShrink.remove(&LIS.getInterval(Reg));
 385       eraseVirtReg(Reg);
 386     }
 387   }
 388 }
 389
 390 void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr *> &Dead,
 391                                       ArrayRef<unsigned> RegsBeingSpilled,
 392                                       AliasAnalysis *AA) {
 393   ToShrinkSet ToShrink;
 394
 395   for (;;) {
 396     // Erase all dead defs.
 397     while (!Dead.empty())
 398       eliminateDeadDef(Dead.pop_back_val(), ToShrink, AA);
 399
 400     if (ToShrink.empty())
 401       break;
 402
 403     // Shrink just one live interval. Then delete new dead defs.
 404     LiveInterval *LI = ToShrink.back();
 405     ToShrink.pop_back();
 406     if (foldAsLoad(LI, Dead))
 407       continue;
 408     unsigned VReg = LI->reg;
 409     if (TheDelegate)
 410       TheDelegate->LRE_WillShrinkVirtReg(VReg);
 411     if (!LIS.shrinkToUses(LI, &Dead))
 412       continue;
 413
 414     // Don't create new intervals for a register being spilled.
 415     // The new intervals would have to be spilled anyway so its not worth it.
 416     // Also they currently aren't spilled so creating them and not spilling
 417     // them results in incorrect code.
 418     bool BeingSpilled = false;
 419     for (unsigned i = 0, e = RegsBeingSpilled.size(); i != e; ++i) {
 420       if (VReg == RegsBeingSpilled[i]) {
 421         BeingSpilled = true;
 422         break;
 423       }
 424     }
 425
 426     if (BeingSpilled) continue;
 427
 428     // LI may have been separated, create new intervals.
 429     LI->RenumberValues();
 430     SmallVector<LiveInterval*, 8> SplitLIs;
 431     LIS.splitSeparateComponents(*LI, SplitLIs);
 432     if (!SplitLIs.empty())
 433       ++NumFracRanges;
 434
 435     unsigned Original = VRM ? VRM->getOriginal(VReg) : 0;
 436     for (const LiveInterval *SplitLI : SplitLIs) {
 437       // If LI is an original interval that hasn't been split yet, make the new
 438       // intervals their own originals instead of referring to LI. The original
 439       // interval must contain all the split products, and LI doesn't.
 440       if (Original != VReg && Original != 0)
 441         VRM->setIsSplitFromReg(SplitLI->reg, Original);
 442       if (TheDelegate)
 443         TheDelegate->LRE_DidCloneVirtReg(SplitLI->reg, VReg);
 444     }
 445   }
 446 }
 447
 448 // Keep track of new virtual registers created via
 449 // MachineRegisterInfo::createVirtualRegister.
 450 void
 451 LiveRangeEdit::MRI_NoteNewVirtualRegister(unsigned VReg)
 452 {
 453   if (VRM)
 454     VRM->grow();
 455
 456   NewRegs.push_back(VReg);
 457 }
 458
 459 void
 460 LiveRangeEdit::calculateRegClassAndHint(MachineFunction &MF,
 461                                         const MachineLoopInfo &Loops,
 462                                         const MachineBlockFrequencyInfo &MBFI) {
 463   VirtRegAuxInfo VRAI(MF, LIS, VRM, Loops, MBFI);
 464   for (unsigned I = 0, Size = size(); I < Size; ++I) {
 465     LiveInterval &LI = LIS.getInterval(get(I));
 466     if (MRI.recomputeRegClass(LI.reg))
 467       LLVM_DEBUG({
 468         const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
 469         dbgs() << "Inflated " << printReg(LI.reg) << " to "
 470                << TRI->getRegClassName(MRI.getRegClass(LI.reg)) << '\n';
 471       });
 472     VRAI.calculateSpillWeightAndHint(LI);
 473   }
 474 }