lib/CodeGen/MIRParser/MIParser.h

   1 //===- MIParser.h - Machine Instructions Parser -----------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file declares the function that parses the machine instructions.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_CODEGEN_MIRPARSER_MIPARSER_H
  14 #define LLVM_LIB_CODEGEN_MIRPARSER_MIPARSER_H
  15
  16 #include "llvm/ADT/DenseMap.h"
  17 #include "llvm/ADT/StringMap.h"
  18 #include "llvm/Support/Allocator.h"
  19
  20 namespace llvm {
  21
  22 class MachineBasicBlock;
  23 class MachineFunction;
  24 class MDNode;
  25 class RegisterBank;
  26 struct SlotMapping;
  27 class SMDiagnostic;
  28 class SourceMgr;
  29 class StringRef;
  30 class TargetRegisterClass;
  31
  32 struct VRegInfo {
  33   enum uint8_t {
  34     UNKNOWN, NORMAL, GENERIC, REGBANK
  35   } Kind = UNKNOWN;
  36   bool Explicit = false; ///< VReg was explicitly specified in the .mir file.
  37   union {
  38     const TargetRegisterClass *RC;
  39     const RegisterBank *RegBank;
  40   } D;
  41   unsigned VReg;
  42   unsigned PreferredReg = 0;
  43 };
  44
  45 using Name2RegClassMap = StringMap<const TargetRegisterClass *>;
  46 using Name2RegBankMap = StringMap<const RegisterBank *>;
  47
  48 struct PerFunctionMIParsingState {
  49   BumpPtrAllocator Allocator;
  50   MachineFunction &MF;
  51   SourceMgr *SM;
  52   const SlotMapping &IRSlots;
  53   const Name2RegClassMap &Names2RegClasses;
  54   const Name2RegBankMap &Names2RegBanks;
  55
  56   DenseMap<unsigned, MachineBasicBlock *> MBBSlots;
  57   DenseMap<unsigned, VRegInfo*> VRegInfos;
  58   StringMap<VRegInfo*> VRegInfosNamed;
  59   DenseMap<unsigned, int> FixedStackObjectSlots;
  60   DenseMap<unsigned, int> StackObjectSlots;
  61   DenseMap<unsigned, unsigned> ConstantPoolSlots;
  62   DenseMap<unsigned, unsigned> JumpTableSlots;
  63
  64   PerFunctionMIParsingState(MachineFunction &MF, SourceMgr &SM,
  65                             const SlotMapping &IRSlots,
  66                             const Name2RegClassMap &Names2RegClasses,
  67                             const Name2RegBankMap &Names2RegBanks);
  68
  69   VRegInfo &getVRegInfo(unsigned Num);
  70   VRegInfo &getVRegInfoNamed(StringRef RegName);
  71 };
  72
  73 /// Parse the machine basic block definitions, and skip the machine
  74 /// instructions.
  75 ///
  76 /// This function runs the first parsing pass on the machine function's body.
  77 /// It parses only the machine basic block definitions and creates the machine
  78 /// basic blocks in the given machine function.
  79 ///
  80 /// The machine instructions aren't parsed during the first pass because all
  81 /// the machine basic blocks aren't defined yet - this makes it impossible to
  82 /// resolve the machine basic block references.
  83 ///
  84 /// Return true if an error occurred.
  85 bool parseMachineBasicBlockDefinitions(PerFunctionMIParsingState &PFS,
  86                                        StringRef Src, SMDiagnostic &Error);
  87
  88 /// Parse the machine instructions.
  89 ///
  90 /// This function runs the second parsing pass on the machine function's body.
  91 /// It skips the machine basic block definitions and parses only the machine
  92 /// instructions and basic block attributes like liveins and successors.
  93 ///
  94 /// The second parsing pass assumes that the first parsing pass already ran
  95 /// on the given source string.
  96 ///
  97 /// Return true if an error occurred.
  98 bool parseMachineInstructions(PerFunctionMIParsingState &PFS, StringRef Src,
  99                               SMDiagnostic &Error);
 100
 101 bool parseMBBReference(PerFunctionMIParsingState &PFS,
 102                        MachineBasicBlock *&MBB, StringRef Src,
 103                        SMDiagnostic &Error);
 104
 105 bool parseRegisterReference(PerFunctionMIParsingState &PFS,
 106                             unsigned &Reg, StringRef Src,
 107                             SMDiagnostic &Error);
 108
 109 bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, unsigned &Reg,
 110                                  StringRef Src, SMDiagnostic &Error);
 111
 112 bool parseVirtualRegisterReference(PerFunctionMIParsingState &PFS,
 113                                    VRegInfo *&Info, StringRef Src,
 114                                    SMDiagnostic &Error);
 115
 116 bool parseStackObjectReference(PerFunctionMIParsingState &PFS, int &FI,
 117                                StringRef Src, SMDiagnostic &Error);
 118
 119 bool parseMDNode(PerFunctionMIParsingState &PFS, MDNode *&Node, StringRef Src,
 120                  SMDiagnostic &Error);
 121
 122 } // end namespace llvm
 123
 124 #endif // LLVM_LIB_CODEGEN_MIRPARSER_MIPARSER_H