1 //===- MachineVerifier.cpp - Machine Code Verifier ------------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // Pass to verify generated machine code. The following is checked:
11 // Operand counts: All explicit operands must be present.
13 // Register classes: All physical and virtual register operands must be
14 // compatible with the register class required by the instruction descriptor.
16 // Register live intervals: Registers must be defined only once, and must be
17 // defined before use.
19 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
20 // command-line option -verify-machineinstrs, or by defining the environment
21 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
22 // the verifier errors.
23 //===----------------------------------------------------------------------===//
25 #include "LiveRangeCalc.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/ADT/DenseMap.h"
28 #include "llvm/ADT/DenseSet.h"
29 #include "llvm/ADT/DepthFirstIterator.h"
30 #include "llvm/ADT/STLExtras.h"
31 #include "llvm/ADT/SetOperations.h"
32 #include "llvm/ADT/SmallPtrSet.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/StringRef.h"
35 #include "llvm/ADT/Twine.h"
36 #include "llvm/Analysis/EHPersonalities.h"
37 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
38 #include "llvm/CodeGen/LiveInterval.h"
39 #include "llvm/CodeGen/LiveIntervals.h"
40 #include "llvm/CodeGen/LiveStacks.h"
41 #include "llvm/CodeGen/LiveVariables.h"
42 #include "llvm/CodeGen/MachineBasicBlock.h"
43 #include "llvm/CodeGen/MachineFrameInfo.h"
44 #include "llvm/CodeGen/MachineFunction.h"
45 #include "llvm/CodeGen/MachineFunctionPass.h"
46 #include "llvm/CodeGen/MachineInstr.h"
47 #include "llvm/CodeGen/MachineInstrBundle.h"
48 #include "llvm/CodeGen/MachineMemOperand.h"
49 #include "llvm/CodeGen/MachineOperand.h"
50 #include "llvm/CodeGen/MachineRegisterInfo.h"
51 #include "llvm/CodeGen/PseudoSourceValue.h"
52 #include "llvm/CodeGen/SlotIndexes.h"
53 #include "llvm/CodeGen/StackMaps.h"
54 #include "llvm/CodeGen/TargetInstrInfo.h"
55 #include "llvm/CodeGen/TargetOpcodes.h"
56 #include "llvm/CodeGen/TargetRegisterInfo.h"
57 #include "llvm/CodeGen/TargetSubtargetInfo.h"
58 #include "llvm/IR/BasicBlock.h"
59 #include "llvm/IR/Function.h"
60 #include "llvm/IR/InlineAsm.h"
61 #include "llvm/IR/Instructions.h"
62 #include "llvm/MC/LaneBitmask.h"
63 #include "llvm/MC/MCAsmInfo.h"
64 #include "llvm/MC/MCInstrDesc.h"
65 #include "llvm/MC/MCRegisterInfo.h"
66 #include "llvm/MC/MCTargetOptions.h"
67 #include "llvm/Pass.h"
68 #include "llvm/Support/Casting.h"
69 #include "llvm/Support/ErrorHandling.h"
70 #include "llvm/Support/LowLevelTypeImpl.h"
71 #include "llvm/Support/MathExtras.h"
72 #include "llvm/Support/raw_ostream.h"
73 #include "llvm/Target/TargetMachine.h"
86 struct MachineVerifier
{
87 MachineVerifier(Pass
*pass
, const char *b
) : PASS(pass
), Banner(b
) {}
89 unsigned verify(MachineFunction
&MF
);
93 const MachineFunction
*MF
;
94 const TargetMachine
*TM
;
95 const TargetInstrInfo
*TII
;
96 const TargetRegisterInfo
*TRI
;
97 const MachineRegisterInfo
*MRI
;
101 // Avoid querying the MachineFunctionProperties for each operand.
102 bool isFunctionRegBankSelected
;
103 bool isFunctionSelected
;
105 using RegVector
= SmallVector
<unsigned, 16>;
106 using RegMaskVector
= SmallVector
<const uint32_t *, 4>;
107 using RegSet
= DenseSet
<unsigned>;
108 using RegMap
= DenseMap
<unsigned, const MachineInstr
*>;
109 using BlockSet
= SmallPtrSet
<const MachineBasicBlock
*, 8>;
111 const MachineInstr
*FirstNonPHI
;
112 const MachineInstr
*FirstTerminator
;
113 BlockSet FunctionBlocks
;
115 BitVector regsReserved
;
117 RegVector regsDefined
, regsDead
, regsKilled
;
118 RegMaskVector regMasks
;
122 // Add Reg and any sub-registers to RV
123 void addRegWithSubRegs(RegVector
&RV
, unsigned Reg
) {
125 if (TargetRegisterInfo::isPhysicalRegister(Reg
))
126 for (MCSubRegIterator
SubRegs(Reg
, TRI
); SubRegs
.isValid(); ++SubRegs
)
127 RV
.push_back(*SubRegs
);
131 // Is this MBB reachable from the MF entry point?
132 bool reachable
= false;
134 // Vregs that must be live in because they are used without being
135 // defined. Map value is the user.
138 // Regs killed in MBB. They may be defined again, and will then be in both
139 // regsKilled and regsLiveOut.
142 // Regs defined in MBB and live out. Note that vregs passing through may
143 // be live out without being mentioned here.
146 // Vregs that pass through MBB untouched. This set is disjoint from
147 // regsKilled and regsLiveOut.
150 // Vregs that must pass through MBB because they are needed by a successor
151 // block. This set is disjoint from regsLiveOut.
152 RegSet vregsRequired
;
154 // Set versions of block's predecessor and successor lists.
155 BlockSet Preds
, Succs
;
159 // Add register to vregsPassed if it belongs there. Return true if
161 bool addPassed(unsigned Reg
) {
162 if (!TargetRegisterInfo::isVirtualRegister(Reg
))
164 if (regsKilled
.count(Reg
) || regsLiveOut
.count(Reg
))
166 return vregsPassed
.insert(Reg
).second
;
169 // Same for a full set.
170 bool addPassed(const RegSet
&RS
) {
171 bool changed
= false;
172 for (RegSet::const_iterator I
= RS
.begin(), E
= RS
.end(); I
!= E
; ++I
)
178 // Add register to vregsRequired if it belongs there. Return true if
180 bool addRequired(unsigned Reg
) {
181 if (!TargetRegisterInfo::isVirtualRegister(Reg
))
183 if (regsLiveOut
.count(Reg
))
185 return vregsRequired
.insert(Reg
).second
;
188 // Same for a full set.
189 bool addRequired(const RegSet
&RS
) {
190 bool changed
= false;
191 for (RegSet::const_iterator I
= RS
.begin(), E
= RS
.end(); I
!= E
; ++I
)
197 // Same for a full map.
198 bool addRequired(const RegMap
&RM
) {
199 bool changed
= false;
200 for (RegMap::const_iterator I
= RM
.begin(), E
= RM
.end(); I
!= E
; ++I
)
201 if (addRequired(I
->first
))
206 // Live-out registers are either in regsLiveOut or vregsPassed.
207 bool isLiveOut(unsigned Reg
) const {
208 return regsLiveOut
.count(Reg
) || vregsPassed
.count(Reg
);
212 // Extra register info per MBB.
213 DenseMap
<const MachineBasicBlock
*, BBInfo
> MBBInfoMap
;
215 bool isReserved(unsigned Reg
) {
216 return Reg
< regsReserved
.size() && regsReserved
.test(Reg
);
219 bool isAllocatable(unsigned Reg
) const {
220 return Reg
< TRI
->getNumRegs() && TRI
->isInAllocatableClass(Reg
) &&
221 !regsReserved
.test(Reg
);
224 // Analysis information if available
225 LiveVariables
*LiveVars
;
226 LiveIntervals
*LiveInts
;
227 LiveStacks
*LiveStks
;
228 SlotIndexes
*Indexes
;
230 void visitMachineFunctionBefore();
231 void visitMachineBasicBlockBefore(const MachineBasicBlock
*MBB
);
232 void visitMachineBundleBefore(const MachineInstr
*MI
);
234 bool verifyVectorElementMatch(LLT Ty0
, LLT Ty1
, const MachineInstr
*MI
);
235 void verifyPreISelGenericInstruction(const MachineInstr
*MI
);
236 void visitMachineInstrBefore(const MachineInstr
*MI
);
237 void visitMachineOperand(const MachineOperand
*MO
, unsigned MONum
);
238 void visitMachineInstrAfter(const MachineInstr
*MI
);
239 void visitMachineBundleAfter(const MachineInstr
*MI
);
240 void visitMachineBasicBlockAfter(const MachineBasicBlock
*MBB
);
241 void visitMachineFunctionAfter();
243 void report(const char *msg
, const MachineFunction
*MF
);
244 void report(const char *msg
, const MachineBasicBlock
*MBB
);
245 void report(const char *msg
, const MachineInstr
*MI
);
246 void report(const char *msg
, const MachineOperand
*MO
, unsigned MONum
,
247 LLT MOVRegType
= LLT
{});
249 void report_context(const LiveInterval
&LI
) const;
250 void report_context(const LiveRange
&LR
, unsigned VRegUnit
,
251 LaneBitmask LaneMask
) const;
252 void report_context(const LiveRange::Segment
&S
) const;
253 void report_context(const VNInfo
&VNI
) const;
254 void report_context(SlotIndex Pos
) const;
255 void report_context(MCPhysReg PhysReg
) const;
256 void report_context_liverange(const LiveRange
&LR
) const;
257 void report_context_lanemask(LaneBitmask LaneMask
) const;
258 void report_context_vreg(unsigned VReg
) const;
259 void report_context_vreg_regunit(unsigned VRegOrUnit
) const;
261 void verifyInlineAsm(const MachineInstr
*MI
);
263 void checkLiveness(const MachineOperand
*MO
, unsigned MONum
);
264 void checkLivenessAtUse(const MachineOperand
*MO
, unsigned MONum
,
265 SlotIndex UseIdx
, const LiveRange
&LR
, unsigned VRegOrUnit
,
266 LaneBitmask LaneMask
= LaneBitmask::getNone());
267 void checkLivenessAtDef(const MachineOperand
*MO
, unsigned MONum
,
268 SlotIndex DefIdx
, const LiveRange
&LR
, unsigned VRegOrUnit
,
269 bool SubRangeCheck
= false,
270 LaneBitmask LaneMask
= LaneBitmask::getNone());
272 void markReachable(const MachineBasicBlock
*MBB
);
273 void calcRegsPassed();
274 void checkPHIOps(const MachineBasicBlock
&MBB
);
276 void calcRegsRequired();
277 void verifyLiveVariables();
278 void verifyLiveIntervals();
279 void verifyLiveInterval(const LiveInterval
&);
280 void verifyLiveRangeValue(const LiveRange
&, const VNInfo
*, unsigned,
282 void verifyLiveRangeSegment(const LiveRange
&,
283 const LiveRange::const_iterator I
, unsigned,
285 void verifyLiveRange(const LiveRange
&, unsigned,
286 LaneBitmask LaneMask
= LaneBitmask::getNone());
288 void verifyStackFrame();
290 void verifySlotIndexes() const;
291 void verifyProperties(const MachineFunction
&MF
);
294 struct MachineVerifierPass
: public MachineFunctionPass
{
295 static char ID
; // Pass ID, replacement for typeid
297 const std::string Banner
;
299 MachineVerifierPass(std::string banner
= std::string())
300 : MachineFunctionPass(ID
), Banner(std::move(banner
)) {
301 initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
304 void getAnalysisUsage(AnalysisUsage
&AU
) const override
{
305 AU
.setPreservesAll();
306 MachineFunctionPass::getAnalysisUsage(AU
);
309 bool runOnMachineFunction(MachineFunction
&MF
) override
{
310 unsigned FoundErrors
= MachineVerifier(this, Banner
.c_str()).verify(MF
);
312 report_fatal_error("Found "+Twine(FoundErrors
)+" machine code errors.");
317 } // end anonymous namespace
319 char MachineVerifierPass::ID
= 0;
321 INITIALIZE_PASS(MachineVerifierPass
, "machineverifier",
322 "Verify generated machine code", false, false)
324 FunctionPass
*llvm::createMachineVerifierPass(const std::string
&Banner
) {
325 return new MachineVerifierPass(Banner
);
328 bool MachineFunction::verify(Pass
*p
, const char *Banner
, bool AbortOnErrors
)
330 MachineFunction
&MF
= const_cast<MachineFunction
&>(*this);
331 unsigned FoundErrors
= MachineVerifier(p
, Banner
).verify(MF
);
332 if (AbortOnErrors
&& FoundErrors
)
333 report_fatal_error("Found "+Twine(FoundErrors
)+" machine code errors.");
334 return FoundErrors
== 0;
337 void MachineVerifier::verifySlotIndexes() const {
338 if (Indexes
== nullptr)
341 // Ensure the IdxMBB list is sorted by slot indexes.
343 for (SlotIndexes::MBBIndexIterator I
= Indexes
->MBBIndexBegin(),
344 E
= Indexes
->MBBIndexEnd(); I
!= E
; ++I
) {
345 assert(!Last
.isValid() || I
->first
> Last
);
350 void MachineVerifier::verifyProperties(const MachineFunction
&MF
) {
351 // If a pass has introduced virtual registers without clearing the
352 // NoVRegs property (or set it without allocating the vregs)
353 // then report an error.
354 if (MF
.getProperties().hasProperty(
355 MachineFunctionProperties::Property::NoVRegs
) &&
356 MRI
->getNumVirtRegs())
357 report("Function has NoVRegs property but there are VReg operands", &MF
);
360 unsigned MachineVerifier::verify(MachineFunction
&MF
) {
364 TM
= &MF
.getTarget();
365 TII
= MF
.getSubtarget().getInstrInfo();
366 TRI
= MF
.getSubtarget().getRegisterInfo();
367 MRI
= &MF
.getRegInfo();
369 const bool isFunctionFailedISel
= MF
.getProperties().hasProperty(
370 MachineFunctionProperties::Property::FailedISel
);
372 // If we're mid-GlobalISel and we already triggered the fallback path then
373 // it's expected that the MIR is somewhat broken but that's ok since we'll
374 // reset it and clear the FailedISel attribute in ResetMachineFunctions.
375 if (isFunctionFailedISel
)
378 isFunctionRegBankSelected
=
379 !isFunctionFailedISel
&&
380 MF
.getProperties().hasProperty(
381 MachineFunctionProperties::Property::RegBankSelected
);
382 isFunctionSelected
= !isFunctionFailedISel
&&
383 MF
.getProperties().hasProperty(
384 MachineFunctionProperties::Property::Selected
);
390 LiveInts
= PASS
->getAnalysisIfAvailable
<LiveIntervals
>();
391 // We don't want to verify LiveVariables if LiveIntervals is available.
393 LiveVars
= PASS
->getAnalysisIfAvailable
<LiveVariables
>();
394 LiveStks
= PASS
->getAnalysisIfAvailable
<LiveStacks
>();
395 Indexes
= PASS
->getAnalysisIfAvailable
<SlotIndexes
>();
400 verifyProperties(MF
);
402 visitMachineFunctionBefore();
403 for (MachineFunction::const_iterator MFI
= MF
.begin(), MFE
= MF
.end();
405 visitMachineBasicBlockBefore(&*MFI
);
406 // Keep track of the current bundle header.
407 const MachineInstr
*CurBundle
= nullptr;
408 // Do we expect the next instruction to be part of the same bundle?
409 bool InBundle
= false;
411 for (MachineBasicBlock::const_instr_iterator MBBI
= MFI
->instr_begin(),
412 MBBE
= MFI
->instr_end(); MBBI
!= MBBE
; ++MBBI
) {
413 if (MBBI
->getParent() != &*MFI
) {
414 report("Bad instruction parent pointer", &*MFI
);
415 errs() << "Instruction: " << *MBBI
;
419 // Check for consistent bundle flags.
420 if (InBundle
&& !MBBI
->isBundledWithPred())
421 report("Missing BundledPred flag, "
422 "BundledSucc was set on predecessor",
424 if (!InBundle
&& MBBI
->isBundledWithPred())
425 report("BundledPred flag is set, "
426 "but BundledSucc not set on predecessor",
429 // Is this a bundle header?
430 if (!MBBI
->isInsideBundle()) {
432 visitMachineBundleAfter(CurBundle
);
434 visitMachineBundleBefore(CurBundle
);
435 } else if (!CurBundle
)
436 report("No bundle header", &*MBBI
);
437 visitMachineInstrBefore(&*MBBI
);
438 for (unsigned I
= 0, E
= MBBI
->getNumOperands(); I
!= E
; ++I
) {
439 const MachineInstr
&MI
= *MBBI
;
440 const MachineOperand
&Op
= MI
.getOperand(I
);
441 if (Op
.getParent() != &MI
) {
442 // Make sure to use correct addOperand / RemoveOperand / ChangeTo
443 // functions when replacing operands of a MachineInstr.
444 report("Instruction has operand with wrong parent set", &MI
);
447 visitMachineOperand(&Op
, I
);
450 visitMachineInstrAfter(&*MBBI
);
452 // Was this the last bundled instruction?
453 InBundle
= MBBI
->isBundledWithSucc();
456 visitMachineBundleAfter(CurBundle
);
458 report("BundledSucc flag set on last instruction in block", &MFI
->back());
459 visitMachineBasicBlockAfter(&*MFI
);
461 visitMachineFunctionAfter();
474 void MachineVerifier::report(const char *msg
, const MachineFunction
*MF
) {
477 if (!foundErrors
++) {
479 errs() << "# " << Banner
<< '\n';
480 if (LiveInts
!= nullptr)
481 LiveInts
->print(errs());
483 MF
->print(errs(), Indexes
);
485 errs() << "*** Bad machine code: " << msg
<< " ***\n"
486 << "- function: " << MF
->getName() << "\n";
489 void MachineVerifier::report(const char *msg
, const MachineBasicBlock
*MBB
) {
491 report(msg
, MBB
->getParent());
492 errs() << "- basic block: " << printMBBReference(*MBB
) << ' '
493 << MBB
->getName() << " (" << (const void *)MBB
<< ')';
495 errs() << " [" << Indexes
->getMBBStartIdx(MBB
)
496 << ';' << Indexes
->getMBBEndIdx(MBB
) << ')';
500 void MachineVerifier::report(const char *msg
, const MachineInstr
*MI
) {
502 report(msg
, MI
->getParent());
503 errs() << "- instruction: ";
504 if (Indexes
&& Indexes
->hasIndex(*MI
))
505 errs() << Indexes
->getInstructionIndex(*MI
) << '\t';
506 MI
->print(errs(), /*SkipOpers=*/true);
509 void MachineVerifier::report(const char *msg
, const MachineOperand
*MO
,
510 unsigned MONum
, LLT MOVRegType
) {
512 report(msg
, MO
->getParent());
513 errs() << "- operand " << MONum
<< ": ";
514 MO
->print(errs(), MOVRegType
, TRI
);
518 void MachineVerifier::report_context(SlotIndex Pos
) const {
519 errs() << "- at: " << Pos
<< '\n';
522 void MachineVerifier::report_context(const LiveInterval
&LI
) const {
523 errs() << "- interval: " << LI
<< '\n';
526 void MachineVerifier::report_context(const LiveRange
&LR
, unsigned VRegUnit
,
527 LaneBitmask LaneMask
) const {
528 report_context_liverange(LR
);
529 report_context_vreg_regunit(VRegUnit
);
531 report_context_lanemask(LaneMask
);
534 void MachineVerifier::report_context(const LiveRange::Segment
&S
) const {
535 errs() << "- segment: " << S
<< '\n';
538 void MachineVerifier::report_context(const VNInfo
&VNI
) const {
539 errs() << "- ValNo: " << VNI
.id
<< " (def " << VNI
.def
<< ")\n";
542 void MachineVerifier::report_context_liverange(const LiveRange
&LR
) const {
543 errs() << "- liverange: " << LR
<< '\n';
546 void MachineVerifier::report_context(MCPhysReg PReg
) const {
547 errs() << "- p. register: " << printReg(PReg
, TRI
) << '\n';
550 void MachineVerifier::report_context_vreg(unsigned VReg
) const {
551 errs() << "- v. register: " << printReg(VReg
, TRI
) << '\n';
554 void MachineVerifier::report_context_vreg_regunit(unsigned VRegOrUnit
) const {
555 if (TargetRegisterInfo::isVirtualRegister(VRegOrUnit
)) {
556 report_context_vreg(VRegOrUnit
);
558 errs() << "- regunit: " << printRegUnit(VRegOrUnit
, TRI
) << '\n';
562 void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask
) const {
563 errs() << "- lanemask: " << PrintLaneMask(LaneMask
) << '\n';
566 void MachineVerifier::markReachable(const MachineBasicBlock
*MBB
) {
567 BBInfo
&MInfo
= MBBInfoMap
[MBB
];
568 if (!MInfo
.reachable
) {
569 MInfo
.reachable
= true;
570 for (MachineBasicBlock::const_succ_iterator SuI
= MBB
->succ_begin(),
571 SuE
= MBB
->succ_end(); SuI
!= SuE
; ++SuI
)
576 void MachineVerifier::visitMachineFunctionBefore() {
577 lastIndex
= SlotIndex();
578 regsReserved
= MRI
->reservedRegsFrozen() ? MRI
->getReservedRegs()
579 : TRI
->getReservedRegs(*MF
);
582 markReachable(&MF
->front());
584 // Build a set of the basic blocks in the function.
585 FunctionBlocks
.clear();
586 for (const auto &MBB
: *MF
) {
587 FunctionBlocks
.insert(&MBB
);
588 BBInfo
&MInfo
= MBBInfoMap
[&MBB
];
590 MInfo
.Preds
.insert(MBB
.pred_begin(), MBB
.pred_end());
591 if (MInfo
.Preds
.size() != MBB
.pred_size())
592 report("MBB has duplicate entries in its predecessor list.", &MBB
);
594 MInfo
.Succs
.insert(MBB
.succ_begin(), MBB
.succ_end());
595 if (MInfo
.Succs
.size() != MBB
.succ_size())
596 report("MBB has duplicate entries in its successor list.", &MBB
);
599 // Check that the register use lists are sane.
600 MRI
->verifyUseLists();
606 // Does iterator point to a and b as the first two elements?
607 static bool matchPair(MachineBasicBlock::const_succ_iterator i
,
608 const MachineBasicBlock
*a
, const MachineBasicBlock
*b
) {
617 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock
*MBB
) {
618 FirstTerminator
= nullptr;
619 FirstNonPHI
= nullptr;
621 if (!MF
->getProperties().hasProperty(
622 MachineFunctionProperties::Property::NoPHIs
) && MRI
->tracksLiveness()) {
623 // If this block has allocatable physical registers live-in, check that
624 // it is an entry block or landing pad.
625 for (const auto &LI
: MBB
->liveins()) {
626 if (isAllocatable(LI
.PhysReg
) && !MBB
->isEHPad() &&
627 MBB
->getIterator() != MBB
->getParent()->begin()) {
628 report("MBB has allocatable live-in, but isn't entry or landing-pad.", MBB
);
629 report_context(LI
.PhysReg
);
634 // Count the number of landing pad successors.
635 SmallPtrSet
<MachineBasicBlock
*, 4> LandingPadSuccs
;
636 for (MachineBasicBlock::const_succ_iterator I
= MBB
->succ_begin(),
637 E
= MBB
->succ_end(); I
!= E
; ++I
) {
639 LandingPadSuccs
.insert(*I
);
640 if (!FunctionBlocks
.count(*I
))
641 report("MBB has successor that isn't part of the function.", MBB
);
642 if (!MBBInfoMap
[*I
].Preds
.count(MBB
)) {
643 report("Inconsistent CFG", MBB
);
644 errs() << "MBB is not in the predecessor list of the successor "
645 << printMBBReference(*(*I
)) << ".\n";
649 // Check the predecessor list.
650 for (MachineBasicBlock::const_pred_iterator I
= MBB
->pred_begin(),
651 E
= MBB
->pred_end(); I
!= E
; ++I
) {
652 if (!FunctionBlocks
.count(*I
))
653 report("MBB has predecessor that isn't part of the function.", MBB
);
654 if (!MBBInfoMap
[*I
].Succs
.count(MBB
)) {
655 report("Inconsistent CFG", MBB
);
656 errs() << "MBB is not in the successor list of the predecessor "
657 << printMBBReference(*(*I
)) << ".\n";
661 const MCAsmInfo
*AsmInfo
= TM
->getMCAsmInfo();
662 const BasicBlock
*BB
= MBB
->getBasicBlock();
663 const Function
&F
= MF
->getFunction();
664 if (LandingPadSuccs
.size() > 1 &&
666 AsmInfo
->getExceptionHandlingType() == ExceptionHandling::SjLj
&&
667 BB
&& isa
<SwitchInst
>(BB
->getTerminator())) &&
668 !isScopedEHPersonality(classifyEHPersonality(F
.getPersonalityFn())))
669 report("MBB has more than one landing pad successor", MBB
);
671 // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
672 MachineBasicBlock
*TBB
= nullptr, *FBB
= nullptr;
673 SmallVector
<MachineOperand
, 4> Cond
;
674 if (!TII
->analyzeBranch(*const_cast<MachineBasicBlock
*>(MBB
), TBB
, FBB
,
676 // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
677 // check whether its answers match up with reality.
679 // Block falls through to its successor.
680 MachineFunction::const_iterator MBBI
= MBB
->getIterator();
682 if (MBBI
== MF
->end()) {
683 // It's possible that the block legitimately ends with a noreturn
684 // call or an unreachable, in which case it won't actually fall
685 // out the bottom of the function.
686 } else if (MBB
->succ_size() == LandingPadSuccs
.size()) {
687 // It's possible that the block legitimately ends with a noreturn
688 // call or an unreachable, in which case it won't actually fall
690 } else if (MBB
->succ_size() != 1+LandingPadSuccs
.size()) {
691 report("MBB exits via unconditional fall-through but doesn't have "
692 "exactly one CFG successor!", MBB
);
693 } else if (!MBB
->isSuccessor(&*MBBI
)) {
694 report("MBB exits via unconditional fall-through but its successor "
695 "differs from its CFG successor!", MBB
);
697 if (!MBB
->empty() && MBB
->back().isBarrier() &&
698 !TII
->isPredicated(MBB
->back())) {
699 report("MBB exits via unconditional fall-through but ends with a "
700 "barrier instruction!", MBB
);
703 report("MBB exits via unconditional fall-through but has a condition!",
706 } else if (TBB
&& !FBB
&& Cond
.empty()) {
707 // Block unconditionally branches somewhere.
708 // If the block has exactly one successor, that happens to be a
709 // landingpad, accept it as valid control flow.
710 if (MBB
->succ_size() != 1+LandingPadSuccs
.size() &&
711 (MBB
->succ_size() != 1 || LandingPadSuccs
.size() != 1 ||
712 *MBB
->succ_begin() != *LandingPadSuccs
.begin())) {
713 report("MBB exits via unconditional branch but doesn't have "
714 "exactly one CFG successor!", MBB
);
715 } else if (!MBB
->isSuccessor(TBB
)) {
716 report("MBB exits via unconditional branch but the CFG "
717 "successor doesn't match the actual successor!", MBB
);
720 report("MBB exits via unconditional branch but doesn't contain "
721 "any instructions!", MBB
);
722 } else if (!MBB
->back().isBarrier()) {
723 report("MBB exits via unconditional branch but doesn't end with a "
724 "barrier instruction!", MBB
);
725 } else if (!MBB
->back().isTerminator()) {
726 report("MBB exits via unconditional branch but the branch isn't a "
727 "terminator instruction!", MBB
);
729 } else if (TBB
&& !FBB
&& !Cond
.empty()) {
730 // Block conditionally branches somewhere, otherwise falls through.
731 MachineFunction::const_iterator MBBI
= MBB
->getIterator();
733 if (MBBI
== MF
->end()) {
734 report("MBB conditionally falls through out of function!", MBB
);
735 } else if (MBB
->succ_size() == 1) {
736 // A conditional branch with only one successor is weird, but allowed.
738 report("MBB exits via conditional branch/fall-through but only has "
739 "one CFG successor!", MBB
);
740 else if (TBB
!= *MBB
->succ_begin())
741 report("MBB exits via conditional branch/fall-through but the CFG "
742 "successor don't match the actual successor!", MBB
);
743 } else if (MBB
->succ_size() != 2) {
744 report("MBB exits via conditional branch/fall-through but doesn't have "
745 "exactly two CFG successors!", MBB
);
746 } else if (!matchPair(MBB
->succ_begin(), TBB
, &*MBBI
)) {
747 report("MBB exits via conditional branch/fall-through but the CFG "
748 "successors don't match the actual successors!", MBB
);
751 report("MBB exits via conditional branch/fall-through but doesn't "
752 "contain any instructions!", MBB
);
753 } else if (MBB
->back().isBarrier()) {
754 report("MBB exits via conditional branch/fall-through but ends with a "
755 "barrier instruction!", MBB
);
756 } else if (!MBB
->back().isTerminator()) {
757 report("MBB exits via conditional branch/fall-through but the branch "
758 "isn't a terminator instruction!", MBB
);
760 } else if (TBB
&& FBB
) {
761 // Block conditionally branches somewhere, otherwise branches
763 if (MBB
->succ_size() == 1) {
764 // A conditional branch with only one successor is weird, but allowed.
766 report("MBB exits via conditional branch/branch through but only has "
767 "one CFG successor!", MBB
);
768 else if (TBB
!= *MBB
->succ_begin())
769 report("MBB exits via conditional branch/branch through but the CFG "
770 "successor don't match the actual successor!", MBB
);
771 } else if (MBB
->succ_size() != 2) {
772 report("MBB exits via conditional branch/branch but doesn't have "
773 "exactly two CFG successors!", MBB
);
774 } else if (!matchPair(MBB
->succ_begin(), TBB
, FBB
)) {
775 report("MBB exits via conditional branch/branch but the CFG "
776 "successors don't match the actual successors!", MBB
);
779 report("MBB exits via conditional branch/branch but doesn't "
780 "contain any instructions!", MBB
);
781 } else if (!MBB
->back().isBarrier()) {
782 report("MBB exits via conditional branch/branch but doesn't end with a "
783 "barrier instruction!", MBB
);
784 } else if (!MBB
->back().isTerminator()) {
785 report("MBB exits via conditional branch/branch but the branch "
786 "isn't a terminator instruction!", MBB
);
789 report("MBB exits via conditional branch/branch but there's no "
793 report("AnalyzeBranch returned invalid data!", MBB
);
798 if (MRI
->tracksLiveness()) {
799 for (const auto &LI
: MBB
->liveins()) {
800 if (!TargetRegisterInfo::isPhysicalRegister(LI
.PhysReg
)) {
801 report("MBB live-in list contains non-physical register", MBB
);
804 for (MCSubRegIterator
SubRegs(LI
.PhysReg
, TRI
, /*IncludeSelf=*/true);
805 SubRegs
.isValid(); ++SubRegs
)
806 regsLive
.insert(*SubRegs
);
810 const MachineFrameInfo
&MFI
= MF
->getFrameInfo();
811 BitVector PR
= MFI
.getPristineRegs(*MF
);
812 for (unsigned I
: PR
.set_bits()) {
813 for (MCSubRegIterator
SubRegs(I
, TRI
, /*IncludeSelf=*/true);
814 SubRegs
.isValid(); ++SubRegs
)
815 regsLive
.insert(*SubRegs
);
822 lastIndex
= Indexes
->getMBBStartIdx(MBB
);
825 // This function gets called for all bundle headers, including normal
826 // stand-alone unbundled instructions.
827 void MachineVerifier::visitMachineBundleBefore(const MachineInstr
*MI
) {
828 if (Indexes
&& Indexes
->hasIndex(*MI
)) {
829 SlotIndex idx
= Indexes
->getInstructionIndex(*MI
);
830 if (!(idx
> lastIndex
)) {
831 report("Instruction index out of order", MI
);
832 errs() << "Last instruction was at " << lastIndex
<< '\n';
837 // Ensure non-terminators don't follow terminators.
838 // Ignore predicated terminators formed by if conversion.
839 // FIXME: If conversion shouldn't need to violate this rule.
840 if (MI
->isTerminator() && !TII
->isPredicated(*MI
)) {
841 if (!FirstTerminator
)
842 FirstTerminator
= MI
;
843 } else if (FirstTerminator
) {
844 report("Non-terminator instruction after the first terminator", MI
);
845 errs() << "First terminator was:\t" << *FirstTerminator
;
849 // The operands on an INLINEASM instruction must follow a template.
850 // Verify that the flag operands make sense.
851 void MachineVerifier::verifyInlineAsm(const MachineInstr
*MI
) {
852 // The first two operands on INLINEASM are the asm string and global flags.
853 if (MI
->getNumOperands() < 2) {
854 report("Too few operands on inline asm", MI
);
857 if (!MI
->getOperand(0).isSymbol())
858 report("Asm string must be an external symbol", MI
);
859 if (!MI
->getOperand(1).isImm())
860 report("Asm flags must be an immediate", MI
);
861 // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
862 // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16,
863 // and Extra_IsConvergent = 32.
864 if (!isUInt
<6>(MI
->getOperand(1).getImm()))
865 report("Unknown asm flags", &MI
->getOperand(1), 1);
867 static_assert(InlineAsm::MIOp_FirstOperand
== 2, "Asm format changed");
869 unsigned OpNo
= InlineAsm::MIOp_FirstOperand
;
871 for (unsigned e
= MI
->getNumOperands(); OpNo
< e
; OpNo
+= NumOps
) {
872 const MachineOperand
&MO
= MI
->getOperand(OpNo
);
873 // There may be implicit ops after the fixed operands.
876 NumOps
= 1 + InlineAsm::getNumOperandRegisters(MO
.getImm());
879 if (OpNo
> MI
->getNumOperands())
880 report("Missing operands in last group", MI
);
882 // An optional MDNode follows the groups.
883 if (OpNo
< MI
->getNumOperands() && MI
->getOperand(OpNo
).isMetadata())
886 // All trailing operands must be implicit registers.
887 for (unsigned e
= MI
->getNumOperands(); OpNo
< e
; ++OpNo
) {
888 const MachineOperand
&MO
= MI
->getOperand(OpNo
);
889 if (!MO
.isReg() || !MO
.isImplicit())
890 report("Expected implicit register after groups", &MO
, OpNo
);
894 /// Check that types are consistent when two operands need to have the same
895 /// number of vector elements.
896 /// \return true if the types are valid.
897 bool MachineVerifier::verifyVectorElementMatch(LLT Ty0
, LLT Ty1
,
898 const MachineInstr
*MI
) {
899 if (Ty0
.isVector() != Ty1
.isVector()) {
900 report("operand types must be all-vector or all-scalar", MI
);
901 // Generally we try to report as many issues as possible at once, but in
902 // this case it's not clear what should we be comparing the size of the
903 // scalar with: the size of the whole vector or its lane. Instead of
904 // making an arbitrary choice and emitting not so helpful message, let's
905 // avoid the extra noise and stop here.
909 if (Ty0
.isVector() && Ty0
.getNumElements() != Ty1
.getNumElements()) {
910 report("operand types must preserve number of vector elements", MI
);
917 void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr
*MI
) {
918 if (isFunctionSelected
)
919 report("Unexpected generic instruction in a Selected function", MI
);
921 const MCInstrDesc
&MCID
= MI
->getDesc();
922 unsigned NumOps
= MI
->getNumOperands();
925 SmallVector
<LLT
, 4> Types
;
926 for (unsigned I
= 0, E
= std::min(MCID
.getNumOperands(), NumOps
);
928 if (!MCID
.OpInfo
[I
].isGenericType())
930 // Generic instructions specify type equality constraints between some of
931 // their operands. Make sure these are consistent.
932 size_t TypeIdx
= MCID
.OpInfo
[I
].getGenericTypeIndex();
933 Types
.resize(std::max(TypeIdx
+ 1, Types
.size()));
935 const MachineOperand
*MO
= &MI
->getOperand(I
);
937 report("generic instruction must use register operands", MI
);
941 LLT OpTy
= MRI
->getType(MO
->getReg());
942 // Don't report a type mismatch if there is no actual mismatch, only a
943 // type missing, to reduce noise:
944 if (OpTy
.isValid()) {
945 // Only the first valid type for a type index will be printed: don't
946 // overwrite it later so it's always clear which type was expected:
947 if (!Types
[TypeIdx
].isValid())
948 Types
[TypeIdx
] = OpTy
;
949 else if (Types
[TypeIdx
] != OpTy
)
950 report("Type mismatch in generic instruction", MO
, I
, OpTy
);
952 // Generic instructions must have types attached to their operands.
953 report("Generic instruction is missing a virtual register type", MO
, I
);
957 // Generic opcodes must not have physical register operands.
958 for (unsigned I
= 0; I
< MI
->getNumOperands(); ++I
) {
959 const MachineOperand
*MO
= &MI
->getOperand(I
);
960 if (MO
->isReg() && TargetRegisterInfo::isPhysicalRegister(MO
->getReg()))
961 report("Generic instruction cannot have physical register", MO
, I
);
964 // Avoid out of bounds in checks below. This was already reported earlier.
965 if (MI
->getNumOperands() < MCID
.getNumOperands())
969 if (!TII
->verifyInstruction(*MI
, ErrorInfo
))
970 report(ErrorInfo
.data(), MI
);
972 // Verify properties of various specific instruction types
973 switch (MI
->getOpcode()) {
974 case TargetOpcode::G_CONSTANT
:
975 case TargetOpcode::G_FCONSTANT
: {
976 if (MI
->getNumOperands() < MCID
.getNumOperands())
979 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
980 if (DstTy
.isVector())
981 report("Instruction cannot use a vector result type", MI
);
983 if (MI
->getOpcode() == TargetOpcode::G_CONSTANT
) {
984 if (!MI
->getOperand(1).isCImm()) {
985 report("G_CONSTANT operand must be cimm", MI
);
989 const ConstantInt
*CI
= MI
->getOperand(1).getCImm();
990 if (CI
->getBitWidth() != DstTy
.getSizeInBits())
991 report("inconsistent constant size", MI
);
993 if (!MI
->getOperand(1).isFPImm()) {
994 report("G_FCONSTANT operand must be fpimm", MI
);
997 const ConstantFP
*CF
= MI
->getOperand(1).getFPImm();
999 if (APFloat::getSizeInBits(CF
->getValueAPF().getSemantics()) !=
1000 DstTy
.getSizeInBits()) {
1001 report("inconsistent constant size", MI
);
1007 case TargetOpcode::G_LOAD
:
1008 case TargetOpcode::G_STORE
:
1009 case TargetOpcode::G_ZEXTLOAD
:
1010 case TargetOpcode::G_SEXTLOAD
: {
1011 LLT ValTy
= MRI
->getType(MI
->getOperand(0).getReg());
1012 LLT PtrTy
= MRI
->getType(MI
->getOperand(1).getReg());
1013 if (!PtrTy
.isPointer())
1014 report("Generic memory instruction must access a pointer", MI
);
1016 // Generic loads and stores must have a single MachineMemOperand
1017 // describing that access.
1018 if (!MI
->hasOneMemOperand()) {
1019 report("Generic instruction accessing memory must have one mem operand",
1022 const MachineMemOperand
&MMO
= **MI
->memoperands_begin();
1023 if (MI
->getOpcode() == TargetOpcode::G_ZEXTLOAD
||
1024 MI
->getOpcode() == TargetOpcode::G_SEXTLOAD
) {
1025 if (MMO
.getSize() * 8 >= ValTy
.getSizeInBits())
1026 report("Generic extload must have a narrower memory type", MI
);
1027 } else if (MI
->getOpcode() == TargetOpcode::G_LOAD
) {
1028 if (MMO
.getSize() > (ValTy
.getSizeInBits() + 7) / 8)
1029 report("load memory size cannot exceed result size", MI
);
1030 } else if (MI
->getOpcode() == TargetOpcode::G_STORE
) {
1031 if ((ValTy
.getSizeInBits() + 7) / 8 < MMO
.getSize())
1032 report("store memory size cannot exceed value size", MI
);
1038 case TargetOpcode::G_PHI
: {
1039 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
1040 if (!DstTy
.isValid() ||
1041 !std::all_of(MI
->operands_begin() + 1, MI
->operands_end(),
1042 [this, &DstTy
](const MachineOperand
&MO
) {
1045 LLT Ty
= MRI
->getType(MO
.getReg());
1046 if (!Ty
.isValid() || (Ty
!= DstTy
))
1050 report("Generic Instruction G_PHI has operands with incompatible/missing "
1055 case TargetOpcode::G_BITCAST
: {
1056 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
1057 LLT SrcTy
= MRI
->getType(MI
->getOperand(1).getReg());
1058 if (!DstTy
.isValid() || !SrcTy
.isValid())
1061 if (SrcTy
.isPointer() != DstTy
.isPointer())
1062 report("bitcast cannot convert between pointers and other types", MI
);
1064 if (SrcTy
.getSizeInBits() != DstTy
.getSizeInBits())
1065 report("bitcast sizes must match", MI
);
1068 case TargetOpcode::G_INTTOPTR
:
1069 case TargetOpcode::G_PTRTOINT
:
1070 case TargetOpcode::G_ADDRSPACE_CAST
: {
1071 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
1072 LLT SrcTy
= MRI
->getType(MI
->getOperand(1).getReg());
1073 if (!DstTy
.isValid() || !SrcTy
.isValid())
1076 verifyVectorElementMatch(DstTy
, SrcTy
, MI
);
1078 DstTy
= DstTy
.getScalarType();
1079 SrcTy
= SrcTy
.getScalarType();
1081 if (MI
->getOpcode() == TargetOpcode::G_INTTOPTR
) {
1082 if (!DstTy
.isPointer())
1083 report("inttoptr result type must be a pointer", MI
);
1084 if (SrcTy
.isPointer())
1085 report("inttoptr source type must not be a pointer", MI
);
1086 } else if (MI
->getOpcode() == TargetOpcode::G_PTRTOINT
) {
1087 if (!SrcTy
.isPointer())
1088 report("ptrtoint source type must be a pointer", MI
);
1089 if (DstTy
.isPointer())
1090 report("ptrtoint result type must not be a pointer", MI
);
1092 assert(MI
->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST
);
1093 if (!SrcTy
.isPointer() || !DstTy
.isPointer())
1094 report("addrspacecast types must be pointers", MI
);
1096 if (SrcTy
.getAddressSpace() == DstTy
.getAddressSpace())
1097 report("addrspacecast must convert different address spaces", MI
);
1103 case TargetOpcode::G_GEP
: {
1104 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
1105 LLT PtrTy
= MRI
->getType(MI
->getOperand(1).getReg());
1106 LLT OffsetTy
= MRI
->getType(MI
->getOperand(2).getReg());
1107 if (!DstTy
.isValid() || !PtrTy
.isValid() || !OffsetTy
.isValid())
1110 if (!PtrTy
.getScalarType().isPointer())
1111 report("gep first operand must be a pointer", MI
);
1113 if (OffsetTy
.getScalarType().isPointer())
1114 report("gep offset operand must not be a pointer", MI
);
1116 // TODO: Is the offset allowed to be a scalar with a vector?
1119 case TargetOpcode::G_SEXT
:
1120 case TargetOpcode::G_ZEXT
:
1121 case TargetOpcode::G_ANYEXT
:
1122 case TargetOpcode::G_TRUNC
:
1123 case TargetOpcode::G_FPEXT
:
1124 case TargetOpcode::G_FPTRUNC
: {
1125 // Number of operands and presense of types is already checked (and
1126 // reported in case of any issues), so no need to report them again. As
1127 // we're trying to report as many issues as possible at once, however, the
1128 // instructions aren't guaranteed to have the right number of operands or
1129 // types attached to them at this point
1130 assert(MCID
.getNumOperands() == 2 && "Expected 2 operands G_*{EXT,TRUNC}");
1131 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
1132 LLT SrcTy
= MRI
->getType(MI
->getOperand(1).getReg());
1133 if (!DstTy
.isValid() || !SrcTy
.isValid())
1136 LLT DstElTy
= DstTy
.getScalarType();
1137 LLT SrcElTy
= SrcTy
.getScalarType();
1138 if (DstElTy
.isPointer() || SrcElTy
.isPointer())
1139 report("Generic extend/truncate can not operate on pointers", MI
);
1141 verifyVectorElementMatch(DstTy
, SrcTy
, MI
);
1143 unsigned DstSize
= DstElTy
.getSizeInBits();
1144 unsigned SrcSize
= SrcElTy
.getSizeInBits();
1145 switch (MI
->getOpcode()) {
1147 if (DstSize
<= SrcSize
)
1148 report("Generic extend has destination type no larger than source", MI
);
1150 case TargetOpcode::G_TRUNC
:
1151 case TargetOpcode::G_FPTRUNC
:
1152 if (DstSize
>= SrcSize
)
1153 report("Generic truncate has destination type no smaller than source",
1159 case TargetOpcode::G_SELECT
: {
1160 LLT SelTy
= MRI
->getType(MI
->getOperand(0).getReg());
1161 LLT CondTy
= MRI
->getType(MI
->getOperand(1).getReg());
1162 if (!SelTy
.isValid() || !CondTy
.isValid())
1165 // Scalar condition select on a vector is valid.
1166 if (CondTy
.isVector())
1167 verifyVectorElementMatch(SelTy
, CondTy
, MI
);
1170 case TargetOpcode::G_MERGE_VALUES
: {
1171 // G_MERGE_VALUES should only be used to merge scalars into a larger scalar,
1172 // e.g. s2N = MERGE sN, sN
1173 // Merging multiple scalars into a vector is not allowed, should use
1174 // G_BUILD_VECTOR for that.
1175 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
1176 LLT SrcTy
= MRI
->getType(MI
->getOperand(1).getReg());
1177 if (DstTy
.isVector() || SrcTy
.isVector())
1178 report("G_MERGE_VALUES cannot operate on vectors", MI
);
1181 case TargetOpcode::G_UNMERGE_VALUES
: {
1182 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
1183 LLT SrcTy
= MRI
->getType(MI
->getOperand(MI
->getNumOperands()-1).getReg());
1184 // For now G_UNMERGE can split vectors.
1185 for (unsigned i
= 0; i
< MI
->getNumOperands()-1; ++i
) {
1186 if (MRI
->getType(MI
->getOperand(i
).getReg()) != DstTy
)
1187 report("G_UNMERGE_VALUES destination types do not match", MI
);
1189 if (SrcTy
.getSizeInBits() !=
1190 (DstTy
.getSizeInBits() * (MI
->getNumOperands() - 1))) {
1191 report("G_UNMERGE_VALUES source operand does not cover dest operands",
1196 case TargetOpcode::G_BUILD_VECTOR
: {
1197 // Source types must be scalars, dest type a vector. Total size of scalars
1198 // must match the dest vector size.
1199 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
1200 LLT SrcEltTy
= MRI
->getType(MI
->getOperand(1).getReg());
1201 if (!DstTy
.isVector() || SrcEltTy
.isVector()) {
1202 report("G_BUILD_VECTOR must produce a vector from scalar operands", MI
);
1206 if (DstTy
.getElementType() != SrcEltTy
)
1207 report("G_BUILD_VECTOR result element type must match source type", MI
);
1209 if (DstTy
.getNumElements() != MI
->getNumOperands() - 1)
1210 report("G_BUILD_VECTOR must have an operand for each elemement", MI
);
1212 for (unsigned i
= 2; i
< MI
->getNumOperands(); ++i
) {
1213 if (MRI
->getType(MI
->getOperand(1).getReg()) !=
1214 MRI
->getType(MI
->getOperand(i
).getReg()))
1215 report("G_BUILD_VECTOR source operand types are not homogeneous", MI
);
1220 case TargetOpcode::G_BUILD_VECTOR_TRUNC
: {
1221 // Source types must be scalars, dest type a vector. Scalar types must be
1222 // larger than the dest vector elt type, as this is a truncating operation.
1223 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
1224 LLT SrcEltTy
= MRI
->getType(MI
->getOperand(1).getReg());
1225 if (!DstTy
.isVector() || SrcEltTy
.isVector())
1226 report("G_BUILD_VECTOR_TRUNC must produce a vector from scalar operands",
1228 for (unsigned i
= 2; i
< MI
->getNumOperands(); ++i
) {
1229 if (MRI
->getType(MI
->getOperand(1).getReg()) !=
1230 MRI
->getType(MI
->getOperand(i
).getReg()))
1231 report("G_BUILD_VECTOR_TRUNC source operand types are not homogeneous",
1234 if (SrcEltTy
.getSizeInBits() <= DstTy
.getElementType().getSizeInBits())
1235 report("G_BUILD_VECTOR_TRUNC source operand types are not larger than "
1240 case TargetOpcode::G_CONCAT_VECTORS
: {
1241 // Source types should be vectors, and total size should match the dest
1243 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
1244 LLT SrcTy
= MRI
->getType(MI
->getOperand(1).getReg());
1245 if (!DstTy
.isVector() || !SrcTy
.isVector())
1246 report("G_CONCAT_VECTOR requires vector source and destination operands",
1248 for (unsigned i
= 2; i
< MI
->getNumOperands(); ++i
) {
1249 if (MRI
->getType(MI
->getOperand(1).getReg()) !=
1250 MRI
->getType(MI
->getOperand(i
).getReg()))
1251 report("G_CONCAT_VECTOR source operand types are not homogeneous", MI
);
1253 if (DstTy
.getNumElements() !=
1254 SrcTy
.getNumElements() * (MI
->getNumOperands() - 1))
1255 report("G_CONCAT_VECTOR num dest and source elements should match", MI
);
1258 case TargetOpcode::G_ICMP
:
1259 case TargetOpcode::G_FCMP
: {
1260 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
1261 LLT SrcTy
= MRI
->getType(MI
->getOperand(2).getReg());
1263 if ((DstTy
.isVector() != SrcTy
.isVector()) ||
1264 (DstTy
.isVector() && DstTy
.getNumElements() != SrcTy
.getNumElements()))
1265 report("Generic vector icmp/fcmp must preserve number of lanes", MI
);
1269 case TargetOpcode::G_EXTRACT
: {
1270 const MachineOperand
&SrcOp
= MI
->getOperand(1);
1271 if (!SrcOp
.isReg()) {
1272 report("extract source must be a register", MI
);
1276 const MachineOperand
&OffsetOp
= MI
->getOperand(2);
1277 if (!OffsetOp
.isImm()) {
1278 report("extract offset must be a constant", MI
);
1282 unsigned DstSize
= MRI
->getType(MI
->getOperand(0).getReg()).getSizeInBits();
1283 unsigned SrcSize
= MRI
->getType(SrcOp
.getReg()).getSizeInBits();
1284 if (SrcSize
== DstSize
)
1285 report("extract source must be larger than result", MI
);
1287 if (DstSize
+ OffsetOp
.getImm() > SrcSize
)
1288 report("extract reads past end of register", MI
);
1296 void MachineVerifier::visitMachineInstrBefore(const MachineInstr
*MI
) {
1297 const MCInstrDesc
&MCID
= MI
->getDesc();
1298 if (MI
->getNumOperands() < MCID
.getNumOperands()) {
1299 report("Too few operands", MI
);
1300 errs() << MCID
.getNumOperands() << " operands expected, but "
1301 << MI
->getNumOperands() << " given.\n";
1305 if (MF
->getProperties().hasProperty(
1306 MachineFunctionProperties::Property::NoPHIs
))
1307 report("Found PHI instruction with NoPHIs property set", MI
);
1310 report("Found PHI instruction after non-PHI", MI
);
1311 } else if (FirstNonPHI
== nullptr)
1314 // Check the tied operands.
1315 if (MI
->isInlineAsm())
1316 verifyInlineAsm(MI
);
1318 // Check the MachineMemOperands for basic consistency.
1319 for (MachineInstr::mmo_iterator I
= MI
->memoperands_begin(),
1320 E
= MI
->memoperands_end();
1322 if ((*I
)->isLoad() && !MI
->mayLoad())
1323 report("Missing mayLoad flag", MI
);
1324 if ((*I
)->isStore() && !MI
->mayStore())
1325 report("Missing mayStore flag", MI
);
1328 // Debug values must not have a slot index.
1329 // Other instructions must have one, unless they are inside a bundle.
1331 bool mapped
= !LiveInts
->isNotInMIMap(*MI
);
1332 if (MI
->isDebugInstr()) {
1334 report("Debug instruction has a slot index", MI
);
1335 } else if (MI
->isInsideBundle()) {
1337 report("Instruction inside bundle has a slot index", MI
);
1340 report("Missing slot index", MI
);
1344 if (isPreISelGenericOpcode(MCID
.getOpcode())) {
1345 verifyPreISelGenericInstruction(MI
);
1349 StringRef ErrorInfo
;
1350 if (!TII
->verifyInstruction(*MI
, ErrorInfo
))
1351 report(ErrorInfo
.data(), MI
);
1353 // Verify properties of various specific instruction types
1354 switch (MI
->getOpcode()) {
1355 case TargetOpcode::COPY
: {
1358 const MachineOperand
&DstOp
= MI
->getOperand(0);
1359 const MachineOperand
&SrcOp
= MI
->getOperand(1);
1360 LLT DstTy
= MRI
->getType(DstOp
.getReg());
1361 LLT SrcTy
= MRI
->getType(SrcOp
.getReg());
1362 if (SrcTy
.isValid() && DstTy
.isValid()) {
1363 // If both types are valid, check that the types are the same.
1364 if (SrcTy
!= DstTy
) {
1365 report("Copy Instruction is illegal with mismatching types", MI
);
1366 errs() << "Def = " << DstTy
<< ", Src = " << SrcTy
<< "\n";
1369 if (SrcTy
.isValid() || DstTy
.isValid()) {
1370 // If one of them have valid types, let's just check they have the same
1372 unsigned SrcSize
= TRI
->getRegSizeInBits(SrcOp
.getReg(), *MRI
);
1373 unsigned DstSize
= TRI
->getRegSizeInBits(DstOp
.getReg(), *MRI
);
1374 assert(SrcSize
&& "Expecting size here");
1375 assert(DstSize
&& "Expecting size here");
1376 if (SrcSize
!= DstSize
)
1377 if (!DstOp
.getSubReg() && !SrcOp
.getSubReg()) {
1378 report("Copy Instruction is illegal with mismatching sizes", MI
);
1379 errs() << "Def Size = " << DstSize
<< ", Src Size = " << SrcSize
1385 case TargetOpcode::STATEPOINT
:
1386 if (!MI
->getOperand(StatepointOpers::IDPos
).isImm() ||
1387 !MI
->getOperand(StatepointOpers::NBytesPos
).isImm() ||
1388 !MI
->getOperand(StatepointOpers::NCallArgsPos
).isImm())
1389 report("meta operands to STATEPOINT not constant!", MI
);
1392 auto VerifyStackMapConstant
= [&](unsigned Offset
) {
1393 if (!MI
->getOperand(Offset
).isImm() ||
1394 MI
->getOperand(Offset
).getImm() != StackMaps::ConstantOp
||
1395 !MI
->getOperand(Offset
+ 1).isImm())
1396 report("stack map constant to STATEPOINT not well formed!", MI
);
1398 const unsigned VarStart
= StatepointOpers(MI
).getVarIdx();
1399 VerifyStackMapConstant(VarStart
+ StatepointOpers::CCOffset
);
1400 VerifyStackMapConstant(VarStart
+ StatepointOpers::FlagsOffset
);
1401 VerifyStackMapConstant(VarStart
+ StatepointOpers::NumDeoptOperandsOffset
);
1403 // TODO: verify we have properly encoded deopt arguments
1409 MachineVerifier::visitMachineOperand(const MachineOperand
*MO
, unsigned MONum
) {
1410 const MachineInstr
*MI
= MO
->getParent();
1411 const MCInstrDesc
&MCID
= MI
->getDesc();
1412 unsigned NumDefs
= MCID
.getNumDefs();
1413 if (MCID
.getOpcode() == TargetOpcode::PATCHPOINT
)
1414 NumDefs
= (MONum
== 0 && MO
->isReg()) ? NumDefs
: 0;
1416 // The first MCID.NumDefs operands must be explicit register defines
1417 if (MONum
< NumDefs
) {
1418 const MCOperandInfo
&MCOI
= MCID
.OpInfo
[MONum
];
1420 report("Explicit definition must be a register", MO
, MONum
);
1421 else if (!MO
->isDef() && !MCOI
.isOptionalDef())
1422 report("Explicit definition marked as use", MO
, MONum
);
1423 else if (MO
->isImplicit())
1424 report("Explicit definition marked as implicit", MO
, MONum
);
1425 } else if (MONum
< MCID
.getNumOperands()) {
1426 const MCOperandInfo
&MCOI
= MCID
.OpInfo
[MONum
];
1427 // Don't check if it's the last operand in a variadic instruction. See,
1428 // e.g., LDM_RET in the arm back end.
1430 !(MI
->isVariadic() && MONum
== MCID
.getNumOperands()-1)) {
1431 if (MO
->isDef() && !MCOI
.isOptionalDef())
1432 report("Explicit operand marked as def", MO
, MONum
);
1433 if (MO
->isImplicit())
1434 report("Explicit operand marked as implicit", MO
, MONum
);
1437 int TiedTo
= MCID
.getOperandConstraint(MONum
, MCOI::TIED_TO
);
1440 report("Tied use must be a register", MO
, MONum
);
1441 else if (!MO
->isTied())
1442 report("Operand should be tied", MO
, MONum
);
1443 else if (unsigned(TiedTo
) != MI
->findTiedOperandIdx(MONum
))
1444 report("Tied def doesn't match MCInstrDesc", MO
, MONum
);
1445 else if (TargetRegisterInfo::isPhysicalRegister(MO
->getReg())) {
1446 const MachineOperand
&MOTied
= MI
->getOperand(TiedTo
);
1447 if (!MOTied
.isReg())
1448 report("Tied counterpart must be a register", &MOTied
, TiedTo
);
1449 else if (TargetRegisterInfo::isPhysicalRegister(MOTied
.getReg()) &&
1450 MO
->getReg() != MOTied
.getReg())
1451 report("Tied physical registers must match.", &MOTied
, TiedTo
);
1453 } else if (MO
->isReg() && MO
->isTied())
1454 report("Explicit operand should not be tied", MO
, MONum
);
1456 // ARM adds %reg0 operands to indicate predicates. We'll allow that.
1457 if (MO
->isReg() && !MO
->isImplicit() && !MI
->isVariadic() && MO
->getReg())
1458 report("Extra explicit operand on non-variadic instruction", MO
, MONum
);
1461 switch (MO
->getType()) {
1462 case MachineOperand::MO_Register
: {
1463 const unsigned Reg
= MO
->getReg();
1466 if (MRI
->tracksLiveness() && !MI
->isDebugValue())
1467 checkLiveness(MO
, MONum
);
1469 // Verify the consistency of tied operands.
1471 unsigned OtherIdx
= MI
->findTiedOperandIdx(MONum
);
1472 const MachineOperand
&OtherMO
= MI
->getOperand(OtherIdx
);
1473 if (!OtherMO
.isReg())
1474 report("Must be tied to a register", MO
, MONum
);
1475 if (!OtherMO
.isTied())
1476 report("Missing tie flags on tied operand", MO
, MONum
);
1477 if (MI
->findTiedOperandIdx(OtherIdx
) != MONum
)
1478 report("Inconsistent tie links", MO
, MONum
);
1479 if (MONum
< MCID
.getNumDefs()) {
1480 if (OtherIdx
< MCID
.getNumOperands()) {
1481 if (-1 == MCID
.getOperandConstraint(OtherIdx
, MCOI::TIED_TO
))
1482 report("Explicit def tied to explicit use without tie constraint",
1485 if (!OtherMO
.isImplicit())
1486 report("Explicit def should be tied to implicit use", MO
, MONum
);
1491 // Verify two-address constraints after leaving SSA form.
1493 if (!MRI
->isSSA() && MO
->isUse() &&
1494 MI
->isRegTiedToDefOperand(MONum
, &DefIdx
) &&
1495 Reg
!= MI
->getOperand(DefIdx
).getReg())
1496 report("Two-address instruction operands must be identical", MO
, MONum
);
1498 // Check register classes.
1499 unsigned SubIdx
= MO
->getSubReg();
1501 if (TargetRegisterInfo::isPhysicalRegister(Reg
)) {
1503 report("Illegal subregister index for physical register", MO
, MONum
);
1506 if (MONum
< MCID
.getNumOperands()) {
1507 if (const TargetRegisterClass
*DRC
=
1508 TII
->getRegClass(MCID
, MONum
, TRI
, *MF
)) {
1509 if (!DRC
->contains(Reg
)) {
1510 report("Illegal physical register for instruction", MO
, MONum
);
1511 errs() << printReg(Reg
, TRI
) << " is not a "
1512 << TRI
->getRegClassName(DRC
) << " register.\n";
1516 if (MO
->isRenamable()) {
1517 if (MRI
->isReserved(Reg
)) {
1518 report("isRenamable set on reserved register", MO
, MONum
);
1522 if (MI
->isDebugValue() && MO
->isUse() && !MO
->isDebug()) {
1523 report("Use-reg is not IsDebug in a DBG_VALUE", MO
, MONum
);
1527 // Virtual register.
1528 const TargetRegisterClass
*RC
= MRI
->getRegClassOrNull(Reg
);
1530 // This is a generic virtual register.
1532 // If we're post-Select, we can't have gvregs anymore.
1533 if (isFunctionSelected
) {
1534 report("Generic virtual register invalid in a Selected function",
1539 // The gvreg must have a type and it must not have a SubIdx.
1540 LLT Ty
= MRI
->getType(Reg
);
1541 if (!Ty
.isValid()) {
1542 report("Generic virtual register must have a valid type", MO
,
1547 const RegisterBank
*RegBank
= MRI
->getRegBankOrNull(Reg
);
1549 // If we're post-RegBankSelect, the gvreg must have a bank.
1550 if (!RegBank
&& isFunctionRegBankSelected
) {
1551 report("Generic virtual register must have a bank in a "
1552 "RegBankSelected function",
1557 // Make sure the register fits into its register bank if any.
1558 if (RegBank
&& Ty
.isValid() &&
1559 RegBank
->getSize() < Ty
.getSizeInBits()) {
1560 report("Register bank is too small for virtual register", MO
,
1562 errs() << "Register bank " << RegBank
->getName() << " too small("
1563 << RegBank
->getSize() << ") to fit " << Ty
.getSizeInBits()
1568 report("Generic virtual register does not allow subregister index", MO
,
1573 // If this is a target specific instruction and this operand
1574 // has register class constraint, the virtual register must
1576 if (!isPreISelGenericOpcode(MCID
.getOpcode()) &&
1577 MONum
< MCID
.getNumOperands() &&
1578 TII
->getRegClass(MCID
, MONum
, TRI
, *MF
)) {
1579 report("Virtual register does not match instruction constraint", MO
,
1581 errs() << "Expect register class "
1582 << TRI
->getRegClassName(
1583 TII
->getRegClass(MCID
, MONum
, TRI
, *MF
))
1584 << " but got nothing\n";
1591 const TargetRegisterClass
*SRC
=
1592 TRI
->getSubClassWithSubReg(RC
, SubIdx
);
1594 report("Invalid subregister index for virtual register", MO
, MONum
);
1595 errs() << "Register class " << TRI
->getRegClassName(RC
)
1596 << " does not support subreg index " << SubIdx
<< "\n";
1600 report("Invalid register class for subregister index", MO
, MONum
);
1601 errs() << "Register class " << TRI
->getRegClassName(RC
)
1602 << " does not fully support subreg index " << SubIdx
<< "\n";
1606 if (MONum
< MCID
.getNumOperands()) {
1607 if (const TargetRegisterClass
*DRC
=
1608 TII
->getRegClass(MCID
, MONum
, TRI
, *MF
)) {
1610 const TargetRegisterClass
*SuperRC
=
1611 TRI
->getLargestLegalSuperClass(RC
, *MF
);
1613 report("No largest legal super class exists.", MO
, MONum
);
1616 DRC
= TRI
->getMatchingSuperRegClass(SuperRC
, DRC
, SubIdx
);
1618 report("No matching super-reg register class.", MO
, MONum
);
1622 if (!RC
->hasSuperClassEq(DRC
)) {
1623 report("Illegal virtual register for instruction", MO
, MONum
);
1624 errs() << "Expected a " << TRI
->getRegClassName(DRC
)
1625 << " register, but got a " << TRI
->getRegClassName(RC
)
1634 case MachineOperand::MO_RegisterMask
:
1635 regMasks
.push_back(MO
->getRegMask());
1638 case MachineOperand::MO_MachineBasicBlock
:
1639 if (MI
->isPHI() && !MO
->getMBB()->isSuccessor(MI
->getParent()))
1640 report("PHI operand is not in the CFG", MO
, MONum
);
1643 case MachineOperand::MO_FrameIndex
:
1644 if (LiveStks
&& LiveStks
->hasInterval(MO
->getIndex()) &&
1645 LiveInts
&& !LiveInts
->isNotInMIMap(*MI
)) {
1646 int FI
= MO
->getIndex();
1647 LiveInterval
&LI
= LiveStks
->getInterval(FI
);
1648 SlotIndex Idx
= LiveInts
->getInstructionIndex(*MI
);
1650 bool stores
= MI
->mayStore();
1651 bool loads
= MI
->mayLoad();
1652 // For a memory-to-memory move, we need to check if the frame
1653 // index is used for storing or loading, by inspecting the
1655 if (stores
&& loads
) {
1656 for (auto *MMO
: MI
->memoperands()) {
1657 const PseudoSourceValue
*PSV
= MMO
->getPseudoValue();
1658 if (PSV
== nullptr) continue;
1659 const FixedStackPseudoSourceValue
*Value
=
1660 dyn_cast
<FixedStackPseudoSourceValue
>(PSV
);
1661 if (Value
== nullptr) continue;
1662 if (Value
->getFrameIndex() != FI
) continue;
1670 if (loads
== stores
)
1671 report("Missing fixed stack memoperand.", MI
);
1673 if (loads
&& !LI
.liveAt(Idx
.getRegSlot(true))) {
1674 report("Instruction loads from dead spill slot", MO
, MONum
);
1675 errs() << "Live stack: " << LI
<< '\n';
1677 if (stores
&& !LI
.liveAt(Idx
.getRegSlot())) {
1678 report("Instruction stores to dead spill slot", MO
, MONum
);
1679 errs() << "Live stack: " << LI
<< '\n';
1689 void MachineVerifier::checkLivenessAtUse(const MachineOperand
*MO
,
1690 unsigned MONum
, SlotIndex UseIdx
, const LiveRange
&LR
, unsigned VRegOrUnit
,
1691 LaneBitmask LaneMask
) {
1692 LiveQueryResult LRQ
= LR
.Query(UseIdx
);
1693 // Check if we have a segment at the use, note however that we only need one
1694 // live subregister range, the others may be dead.
1695 if (!LRQ
.valueIn() && LaneMask
.none()) {
1696 report("No live segment at use", MO
, MONum
);
1697 report_context_liverange(LR
);
1698 report_context_vreg_regunit(VRegOrUnit
);
1699 report_context(UseIdx
);
1701 if (MO
->isKill() && !LRQ
.isKill()) {
1702 report("Live range continues after kill flag", MO
, MONum
);
1703 report_context_liverange(LR
);
1704 report_context_vreg_regunit(VRegOrUnit
);
1706 report_context_lanemask(LaneMask
);
1707 report_context(UseIdx
);
1711 void MachineVerifier::checkLivenessAtDef(const MachineOperand
*MO
,
1712 unsigned MONum
, SlotIndex DefIdx
, const LiveRange
&LR
, unsigned VRegOrUnit
,
1713 bool SubRangeCheck
, LaneBitmask LaneMask
) {
1714 if (const VNInfo
*VNI
= LR
.getVNInfoAt(DefIdx
)) {
1715 assert(VNI
&& "NULL valno is not allowed");
1716 if (VNI
->def
!= DefIdx
) {
1717 report("Inconsistent valno->def", MO
, MONum
);
1718 report_context_liverange(LR
);
1719 report_context_vreg_regunit(VRegOrUnit
);
1721 report_context_lanemask(LaneMask
);
1722 report_context(*VNI
);
1723 report_context(DefIdx
);
1726 report("No live segment at def", MO
, MONum
);
1727 report_context_liverange(LR
);
1728 report_context_vreg_regunit(VRegOrUnit
);
1730 report_context_lanemask(LaneMask
);
1731 report_context(DefIdx
);
1733 // Check that, if the dead def flag is present, LiveInts agree.
1735 LiveQueryResult LRQ
= LR
.Query(DefIdx
);
1736 if (!LRQ
.isDeadDef()) {
1737 assert(TargetRegisterInfo::isVirtualRegister(VRegOrUnit
) &&
1738 "Expecting a virtual register.");
1739 // A dead subreg def only tells us that the specific subreg is dead. There
1740 // could be other non-dead defs of other subregs, or we could have other
1741 // parts of the register being live through the instruction. So unless we
1742 // are checking liveness for a subrange it is ok for the live range to
1743 // continue, given that we have a dead def of a subregister.
1744 if (SubRangeCheck
|| MO
->getSubReg() == 0) {
1745 report("Live range continues after dead def flag", MO
, MONum
);
1746 report_context_liverange(LR
);
1747 report_context_vreg_regunit(VRegOrUnit
);
1749 report_context_lanemask(LaneMask
);
1755 void MachineVerifier::checkLiveness(const MachineOperand
*MO
, unsigned MONum
) {
1756 const MachineInstr
*MI
= MO
->getParent();
1757 const unsigned Reg
= MO
->getReg();
1759 // Both use and def operands can read a register.
1760 if (MO
->readsReg()) {
1762 addRegWithSubRegs(regsKilled
, Reg
);
1764 // Check that LiveVars knows this kill.
1765 if (LiveVars
&& TargetRegisterInfo::isVirtualRegister(Reg
) &&
1767 LiveVariables::VarInfo
&VI
= LiveVars
->getVarInfo(Reg
);
1768 if (!is_contained(VI
.Kills
, MI
))
1769 report("Kill missing from LiveVariables", MO
, MONum
);
1772 // Check LiveInts liveness and kill.
1773 if (LiveInts
&& !LiveInts
->isNotInMIMap(*MI
)) {
1774 SlotIndex UseIdx
= LiveInts
->getInstructionIndex(*MI
);
1775 // Check the cached regunit intervals.
1776 if (TargetRegisterInfo::isPhysicalRegister(Reg
) && !isReserved(Reg
)) {
1777 for (MCRegUnitIterator
Units(Reg
, TRI
); Units
.isValid(); ++Units
) {
1778 if (MRI
->isReservedRegUnit(*Units
))
1780 if (const LiveRange
*LR
= LiveInts
->getCachedRegUnit(*Units
))
1781 checkLivenessAtUse(MO
, MONum
, UseIdx
, *LR
, *Units
);
1785 if (TargetRegisterInfo::isVirtualRegister(Reg
)) {
1786 if (LiveInts
->hasInterval(Reg
)) {
1787 // This is a virtual register interval.
1788 const LiveInterval
&LI
= LiveInts
->getInterval(Reg
);
1789 checkLivenessAtUse(MO
, MONum
, UseIdx
, LI
, Reg
);
1791 if (LI
.hasSubRanges() && !MO
->isDef()) {
1792 unsigned SubRegIdx
= MO
->getSubReg();
1793 LaneBitmask MOMask
= SubRegIdx
!= 0
1794 ? TRI
->getSubRegIndexLaneMask(SubRegIdx
)
1795 : MRI
->getMaxLaneMaskForVReg(Reg
);
1796 LaneBitmask LiveInMask
;
1797 for (const LiveInterval::SubRange
&SR
: LI
.subranges()) {
1798 if ((MOMask
& SR
.LaneMask
).none())
1800 checkLivenessAtUse(MO
, MONum
, UseIdx
, SR
, Reg
, SR
.LaneMask
);
1801 LiveQueryResult LRQ
= SR
.Query(UseIdx
);
1803 LiveInMask
|= SR
.LaneMask
;
1805 // At least parts of the register has to be live at the use.
1806 if ((LiveInMask
& MOMask
).none()) {
1807 report("No live subrange at use", MO
, MONum
);
1809 report_context(UseIdx
);
1813 report("Virtual register has no live interval", MO
, MONum
);
1818 // Use of a dead register.
1819 if (!regsLive
.count(Reg
)) {
1820 if (TargetRegisterInfo::isPhysicalRegister(Reg
)) {
1821 // Reserved registers may be used even when 'dead'.
1822 bool Bad
= !isReserved(Reg
);
1823 // We are fine if just any subregister has a defined value.
1825 for (MCSubRegIterator
SubRegs(Reg
, TRI
); SubRegs
.isValid();
1827 if (regsLive
.count(*SubRegs
)) {
1833 // If there is an additional implicit-use of a super register we stop
1834 // here. By definition we are fine if the super register is not
1835 // (completely) dead, if the complete super register is dead we will
1836 // get a report for its operand.
1838 for (const MachineOperand
&MOP
: MI
->uses()) {
1839 if (!MOP
.isReg() || !MOP
.isImplicit())
1842 if (!TargetRegisterInfo::isPhysicalRegister(MOP
.getReg()))
1845 for (MCSubRegIterator
SubRegs(MOP
.getReg(), TRI
); SubRegs
.isValid();
1847 if (*SubRegs
== Reg
) {
1855 report("Using an undefined physical register", MO
, MONum
);
1856 } else if (MRI
->def_empty(Reg
)) {
1857 report("Reading virtual register without a def", MO
, MONum
);
1859 BBInfo
&MInfo
= MBBInfoMap
[MI
->getParent()];
1860 // We don't know which virtual registers are live in, so only complain
1861 // if vreg was killed in this MBB. Otherwise keep track of vregs that
1862 // must be live in. PHI instructions are handled separately.
1863 if (MInfo
.regsKilled
.count(Reg
))
1864 report("Using a killed virtual register", MO
, MONum
);
1865 else if (!MI
->isPHI())
1866 MInfo
.vregsLiveIn
.insert(std::make_pair(Reg
, MI
));
1872 // Register defined.
1873 // TODO: verify that earlyclobber ops are not used.
1875 addRegWithSubRegs(regsDead
, Reg
);
1877 addRegWithSubRegs(regsDefined
, Reg
);
1880 if (MRI
->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg
) &&
1881 std::next(MRI
->def_begin(Reg
)) != MRI
->def_end())
1882 report("Multiple virtual register defs in SSA form", MO
, MONum
);
1884 // Check LiveInts for a live segment, but only for virtual registers.
1885 if (LiveInts
&& !LiveInts
->isNotInMIMap(*MI
)) {
1886 SlotIndex DefIdx
= LiveInts
->getInstructionIndex(*MI
);
1887 DefIdx
= DefIdx
.getRegSlot(MO
->isEarlyClobber());
1889 if (TargetRegisterInfo::isVirtualRegister(Reg
)) {
1890 if (LiveInts
->hasInterval(Reg
)) {
1891 const LiveInterval
&LI
= LiveInts
->getInterval(Reg
);
1892 checkLivenessAtDef(MO
, MONum
, DefIdx
, LI
, Reg
);
1894 if (LI
.hasSubRanges()) {
1895 unsigned SubRegIdx
= MO
->getSubReg();
1896 LaneBitmask MOMask
= SubRegIdx
!= 0
1897 ? TRI
->getSubRegIndexLaneMask(SubRegIdx
)
1898 : MRI
->getMaxLaneMaskForVReg(Reg
);
1899 for (const LiveInterval::SubRange
&SR
: LI
.subranges()) {
1900 if ((SR
.LaneMask
& MOMask
).none())
1902 checkLivenessAtDef(MO
, MONum
, DefIdx
, SR
, Reg
, true, SR
.LaneMask
);
1906 report("Virtual register has no Live interval", MO
, MONum
);
1913 void MachineVerifier::visitMachineInstrAfter(const MachineInstr
*MI
) {}
1915 // This function gets called after visiting all instructions in a bundle. The
1916 // argument points to the bundle header.
1917 // Normal stand-alone instructions are also considered 'bundles', and this
1918 // function is called for all of them.
1919 void MachineVerifier::visitMachineBundleAfter(const MachineInstr
*MI
) {
1920 BBInfo
&MInfo
= MBBInfoMap
[MI
->getParent()];
1921 set_union(MInfo
.regsKilled
, regsKilled
);
1922 set_subtract(regsLive
, regsKilled
); regsKilled
.clear();
1923 // Kill any masked registers.
1924 while (!regMasks
.empty()) {
1925 const uint32_t *Mask
= regMasks
.pop_back_val();
1926 for (RegSet::iterator I
= regsLive
.begin(), E
= regsLive
.end(); I
!= E
; ++I
)
1927 if (TargetRegisterInfo::isPhysicalRegister(*I
) &&
1928 MachineOperand::clobbersPhysReg(Mask
, *I
))
1929 regsDead
.push_back(*I
);
1931 set_subtract(regsLive
, regsDead
); regsDead
.clear();
1932 set_union(regsLive
, regsDefined
); regsDefined
.clear();
1936 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock
*MBB
) {
1937 MBBInfoMap
[MBB
].regsLiveOut
= regsLive
;
1941 SlotIndex stop
= Indexes
->getMBBEndIdx(MBB
);
1942 if (!(stop
> lastIndex
)) {
1943 report("Block ends before last instruction index", MBB
);
1944 errs() << "Block ends at " << stop
1945 << " last instruction was at " << lastIndex
<< '\n';
1951 // Calculate the largest possible vregsPassed sets. These are the registers that
1952 // can pass through an MBB live, but may not be live every time. It is assumed
1953 // that all vregsPassed sets are empty before the call.
1954 void MachineVerifier::calcRegsPassed() {
1955 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
1956 // have any vregsPassed.
1957 SmallPtrSet
<const MachineBasicBlock
*, 8> todo
;
1958 for (const auto &MBB
: *MF
) {
1959 BBInfo
&MInfo
= MBBInfoMap
[&MBB
];
1960 if (!MInfo
.reachable
)
1962 for (MachineBasicBlock::const_succ_iterator SuI
= MBB
.succ_begin(),
1963 SuE
= MBB
.succ_end(); SuI
!= SuE
; ++SuI
) {
1964 BBInfo
&SInfo
= MBBInfoMap
[*SuI
];
1965 if (SInfo
.addPassed(MInfo
.regsLiveOut
))
1970 // Iteratively push vregsPassed to successors. This will converge to the same
1971 // final state regardless of DenseSet iteration order.
1972 while (!todo
.empty()) {
1973 const MachineBasicBlock
*MBB
= *todo
.begin();
1975 BBInfo
&MInfo
= MBBInfoMap
[MBB
];
1976 for (MachineBasicBlock::const_succ_iterator SuI
= MBB
->succ_begin(),
1977 SuE
= MBB
->succ_end(); SuI
!= SuE
; ++SuI
) {
1980 BBInfo
&SInfo
= MBBInfoMap
[*SuI
];
1981 if (SInfo
.addPassed(MInfo
.vregsPassed
))
1987 // Calculate the set of virtual registers that must be passed through each basic
1988 // block in order to satisfy the requirements of successor blocks. This is very
1989 // similar to calcRegsPassed, only backwards.
1990 void MachineVerifier::calcRegsRequired() {
1991 // First push live-in regs to predecessors' vregsRequired.
1992 SmallPtrSet
<const MachineBasicBlock
*, 8> todo
;
1993 for (const auto &MBB
: *MF
) {
1994 BBInfo
&MInfo
= MBBInfoMap
[&MBB
];
1995 for (MachineBasicBlock::const_pred_iterator PrI
= MBB
.pred_begin(),
1996 PrE
= MBB
.pred_end(); PrI
!= PrE
; ++PrI
) {
1997 BBInfo
&PInfo
= MBBInfoMap
[*PrI
];
1998 if (PInfo
.addRequired(MInfo
.vregsLiveIn
))
2003 // Iteratively push vregsRequired to predecessors. This will converge to the
2004 // same final state regardless of DenseSet iteration order.
2005 while (!todo
.empty()) {
2006 const MachineBasicBlock
*MBB
= *todo
.begin();
2008 BBInfo
&MInfo
= MBBInfoMap
[MBB
];
2009 for (MachineBasicBlock::const_pred_iterator PrI
= MBB
->pred_begin(),
2010 PrE
= MBB
->pred_end(); PrI
!= PrE
; ++PrI
) {
2013 BBInfo
&SInfo
= MBBInfoMap
[*PrI
];
2014 if (SInfo
.addRequired(MInfo
.vregsRequired
))
2020 // Check PHI instructions at the beginning of MBB. It is assumed that
2021 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
2022 void MachineVerifier::checkPHIOps(const MachineBasicBlock
&MBB
) {
2023 BBInfo
&MInfo
= MBBInfoMap
[&MBB
];
2025 SmallPtrSet
<const MachineBasicBlock
*, 8> seen
;
2026 for (const MachineInstr
&Phi
: MBB
) {
2031 const MachineOperand
&MODef
= Phi
.getOperand(0);
2032 if (!MODef
.isReg() || !MODef
.isDef()) {
2033 report("Expected first PHI operand to be a register def", &MODef
, 0);
2036 if (MODef
.isTied() || MODef
.isImplicit() || MODef
.isInternalRead() ||
2037 MODef
.isEarlyClobber() || MODef
.isDebug())
2038 report("Unexpected flag on PHI operand", &MODef
, 0);
2039 unsigned DefReg
= MODef
.getReg();
2040 if (!TargetRegisterInfo::isVirtualRegister(DefReg
))
2041 report("Expected first PHI operand to be a virtual register", &MODef
, 0);
2043 for (unsigned I
= 1, E
= Phi
.getNumOperands(); I
!= E
; I
+= 2) {
2044 const MachineOperand
&MO0
= Phi
.getOperand(I
);
2046 report("Expected PHI operand to be a register", &MO0
, I
);
2049 if (MO0
.isImplicit() || MO0
.isInternalRead() || MO0
.isEarlyClobber() ||
2050 MO0
.isDebug() || MO0
.isTied())
2051 report("Unexpected flag on PHI operand", &MO0
, I
);
2053 const MachineOperand
&MO1
= Phi
.getOperand(I
+ 1);
2055 report("Expected PHI operand to be a basic block", &MO1
, I
+ 1);
2059 const MachineBasicBlock
&Pre
= *MO1
.getMBB();
2060 if (!Pre
.isSuccessor(&MBB
)) {
2061 report("PHI input is not a predecessor block", &MO1
, I
+ 1);
2065 if (MInfo
.reachable
) {
2067 BBInfo
&PrInfo
= MBBInfoMap
[&Pre
];
2068 if (!MO0
.isUndef() && PrInfo
.reachable
&&
2069 !PrInfo
.isLiveOut(MO0
.getReg()))
2070 report("PHI operand is not live-out from predecessor", &MO0
, I
);
2074 // Did we see all predecessors?
2075 if (MInfo
.reachable
) {
2076 for (MachineBasicBlock
*Pred
: MBB
.predecessors()) {
2077 if (!seen
.count(Pred
)) {
2078 report("Missing PHI operand", &Phi
);
2079 errs() << printMBBReference(*Pred
)
2080 << " is a predecessor according to the CFG.\n";
2087 void MachineVerifier::visitMachineFunctionAfter() {
2090 for (const MachineBasicBlock
&MBB
: *MF
)
2093 // Now check liveness info if available
2096 // Check for killed virtual registers that should be live out.
2097 for (const auto &MBB
: *MF
) {
2098 BBInfo
&MInfo
= MBBInfoMap
[&MBB
];
2099 for (RegSet::iterator
2100 I
= MInfo
.vregsRequired
.begin(), E
= MInfo
.vregsRequired
.end(); I
!= E
;
2102 if (MInfo
.regsKilled
.count(*I
)) {
2103 report("Virtual register killed in block, but needed live out.", &MBB
);
2104 errs() << "Virtual register " << printReg(*I
)
2105 << " is used after the block.\n";
2110 BBInfo
&MInfo
= MBBInfoMap
[&MF
->front()];
2111 for (RegSet::iterator
2112 I
= MInfo
.vregsRequired
.begin(), E
= MInfo
.vregsRequired
.end(); I
!= E
;
2114 report("Virtual register defs don't dominate all uses.", MF
);
2115 report_context_vreg(*I
);
2120 verifyLiveVariables();
2122 verifyLiveIntervals();
2125 void MachineVerifier::verifyLiveVariables() {
2126 assert(LiveVars
&& "Don't call verifyLiveVariables without LiveVars");
2127 for (unsigned i
= 0, e
= MRI
->getNumVirtRegs(); i
!= e
; ++i
) {
2128 unsigned Reg
= TargetRegisterInfo::index2VirtReg(i
);
2129 LiveVariables::VarInfo
&VI
= LiveVars
->getVarInfo(Reg
);
2130 for (const auto &MBB
: *MF
) {
2131 BBInfo
&MInfo
= MBBInfoMap
[&MBB
];
2133 // Our vregsRequired should be identical to LiveVariables' AliveBlocks
2134 if (MInfo
.vregsRequired
.count(Reg
)) {
2135 if (!VI
.AliveBlocks
.test(MBB
.getNumber())) {
2136 report("LiveVariables: Block missing from AliveBlocks", &MBB
);
2137 errs() << "Virtual register " << printReg(Reg
)
2138 << " must be live through the block.\n";
2141 if (VI
.AliveBlocks
.test(MBB
.getNumber())) {
2142 report("LiveVariables: Block should not be in AliveBlocks", &MBB
);
2143 errs() << "Virtual register " << printReg(Reg
)
2144 << " is not needed live through the block.\n";
2151 void MachineVerifier::verifyLiveIntervals() {
2152 assert(LiveInts
&& "Don't call verifyLiveIntervals without LiveInts");
2153 for (unsigned i
= 0, e
= MRI
->getNumVirtRegs(); i
!= e
; ++i
) {
2154 unsigned Reg
= TargetRegisterInfo::index2VirtReg(i
);
2156 // Spilling and splitting may leave unused registers around. Skip them.
2157 if (MRI
->reg_nodbg_empty(Reg
))
2160 if (!LiveInts
->hasInterval(Reg
)) {
2161 report("Missing live interval for virtual register", MF
);
2162 errs() << printReg(Reg
, TRI
) << " still has defs or uses\n";
2166 const LiveInterval
&LI
= LiveInts
->getInterval(Reg
);
2167 assert(Reg
== LI
.reg
&& "Invalid reg to interval mapping");
2168 verifyLiveInterval(LI
);
2171 // Verify all the cached regunit intervals.
2172 for (unsigned i
= 0, e
= TRI
->getNumRegUnits(); i
!= e
; ++i
)
2173 if (const LiveRange
*LR
= LiveInts
->getCachedRegUnit(i
))
2174 verifyLiveRange(*LR
, i
);
2177 void MachineVerifier::verifyLiveRangeValue(const LiveRange
&LR
,
2178 const VNInfo
*VNI
, unsigned Reg
,
2179 LaneBitmask LaneMask
) {
2180 if (VNI
->isUnused())
2183 const VNInfo
*DefVNI
= LR
.getVNInfoAt(VNI
->def
);
2186 report("Value not live at VNInfo def and not marked unused", MF
);
2187 report_context(LR
, Reg
, LaneMask
);
2188 report_context(*VNI
);
2192 if (DefVNI
!= VNI
) {
2193 report("Live segment at def has different VNInfo", MF
);
2194 report_context(LR
, Reg
, LaneMask
);
2195 report_context(*VNI
);
2199 const MachineBasicBlock
*MBB
= LiveInts
->getMBBFromIndex(VNI
->def
);
2201 report("Invalid VNInfo definition index", MF
);
2202 report_context(LR
, Reg
, LaneMask
);
2203 report_context(*VNI
);
2207 if (VNI
->isPHIDef()) {
2208 if (VNI
->def
!= LiveInts
->getMBBStartIdx(MBB
)) {
2209 report("PHIDef VNInfo is not defined at MBB start", MBB
);
2210 report_context(LR
, Reg
, LaneMask
);
2211 report_context(*VNI
);
2217 const MachineInstr
*MI
= LiveInts
->getInstructionFromIndex(VNI
->def
);
2219 report("No instruction at VNInfo def index", MBB
);
2220 report_context(LR
, Reg
, LaneMask
);
2221 report_context(*VNI
);
2226 bool hasDef
= false;
2227 bool isEarlyClobber
= false;
2228 for (ConstMIBundleOperands
MOI(*MI
); MOI
.isValid(); ++MOI
) {
2229 if (!MOI
->isReg() || !MOI
->isDef())
2231 if (TargetRegisterInfo::isVirtualRegister(Reg
)) {
2232 if (MOI
->getReg() != Reg
)
2235 if (!TargetRegisterInfo::isPhysicalRegister(MOI
->getReg()) ||
2236 !TRI
->hasRegUnit(MOI
->getReg(), Reg
))
2239 if (LaneMask
.any() &&
2240 (TRI
->getSubRegIndexLaneMask(MOI
->getSubReg()) & LaneMask
).none())
2243 if (MOI
->isEarlyClobber())
2244 isEarlyClobber
= true;
2248 report("Defining instruction does not modify register", MI
);
2249 report_context(LR
, Reg
, LaneMask
);
2250 report_context(*VNI
);
2253 // Early clobber defs begin at USE slots, but other defs must begin at
2255 if (isEarlyClobber
) {
2256 if (!VNI
->def
.isEarlyClobber()) {
2257 report("Early clobber def must be at an early-clobber slot", MBB
);
2258 report_context(LR
, Reg
, LaneMask
);
2259 report_context(*VNI
);
2261 } else if (!VNI
->def
.isRegister()) {
2262 report("Non-PHI, non-early clobber def must be at a register slot", MBB
);
2263 report_context(LR
, Reg
, LaneMask
);
2264 report_context(*VNI
);
2269 void MachineVerifier::verifyLiveRangeSegment(const LiveRange
&LR
,
2270 const LiveRange::const_iterator I
,
2271 unsigned Reg
, LaneBitmask LaneMask
)
2273 const LiveRange::Segment
&S
= *I
;
2274 const VNInfo
*VNI
= S
.valno
;
2275 assert(VNI
&& "Live segment has no valno");
2277 if (VNI
->id
>= LR
.getNumValNums() || VNI
!= LR
.getValNumInfo(VNI
->id
)) {
2278 report("Foreign valno in live segment", MF
);
2279 report_context(LR
, Reg
, LaneMask
);
2281 report_context(*VNI
);
2284 if (VNI
->isUnused()) {
2285 report("Live segment valno is marked unused", MF
);
2286 report_context(LR
, Reg
, LaneMask
);
2290 const MachineBasicBlock
*MBB
= LiveInts
->getMBBFromIndex(S
.start
);
2292 report("Bad start of live segment, no basic block", MF
);
2293 report_context(LR
, Reg
, LaneMask
);
2297 SlotIndex MBBStartIdx
= LiveInts
->getMBBStartIdx(MBB
);
2298 if (S
.start
!= MBBStartIdx
&& S
.start
!= VNI
->def
) {
2299 report("Live segment must begin at MBB entry or valno def", MBB
);
2300 report_context(LR
, Reg
, LaneMask
);
2304 const MachineBasicBlock
*EndMBB
=
2305 LiveInts
->getMBBFromIndex(S
.end
.getPrevSlot());
2307 report("Bad end of live segment, no basic block", MF
);
2308 report_context(LR
, Reg
, LaneMask
);
2313 // No more checks for live-out segments.
2314 if (S
.end
== LiveInts
->getMBBEndIdx(EndMBB
))
2317 // RegUnit intervals are allowed dead phis.
2318 if (!TargetRegisterInfo::isVirtualRegister(Reg
) && VNI
->isPHIDef() &&
2319 S
.start
== VNI
->def
&& S
.end
== VNI
->def
.getDeadSlot())
2322 // The live segment is ending inside EndMBB
2323 const MachineInstr
*MI
=
2324 LiveInts
->getInstructionFromIndex(S
.end
.getPrevSlot());
2326 report("Live segment doesn't end at a valid instruction", EndMBB
);
2327 report_context(LR
, Reg
, LaneMask
);
2332 // The block slot must refer to a basic block boundary.
2333 if (S
.end
.isBlock()) {
2334 report("Live segment ends at B slot of an instruction", EndMBB
);
2335 report_context(LR
, Reg
, LaneMask
);
2339 if (S
.end
.isDead()) {
2340 // Segment ends on the dead slot.
2341 // That means there must be a dead def.
2342 if (!SlotIndex::isSameInstr(S
.start
, S
.end
)) {
2343 report("Live segment ending at dead slot spans instructions", EndMBB
);
2344 report_context(LR
, Reg
, LaneMask
);
2349 // A live segment can only end at an early-clobber slot if it is being
2350 // redefined by an early-clobber def.
2351 if (S
.end
.isEarlyClobber()) {
2352 if (I
+1 == LR
.end() || (I
+1)->start
!= S
.end
) {
2353 report("Live segment ending at early clobber slot must be "
2354 "redefined by an EC def in the same instruction", EndMBB
);
2355 report_context(LR
, Reg
, LaneMask
);
2360 // The following checks only apply to virtual registers. Physreg liveness
2361 // is too weird to check.
2362 if (TargetRegisterInfo::isVirtualRegister(Reg
)) {
2363 // A live segment can end with either a redefinition, a kill flag on a
2364 // use, or a dead flag on a def.
2365 bool hasRead
= false;
2366 bool hasSubRegDef
= false;
2367 bool hasDeadDef
= false;
2368 for (ConstMIBundleOperands
MOI(*MI
); MOI
.isValid(); ++MOI
) {
2369 if (!MOI
->isReg() || MOI
->getReg() != Reg
)
2371 unsigned Sub
= MOI
->getSubReg();
2372 LaneBitmask SLM
= Sub
!= 0 ? TRI
->getSubRegIndexLaneMask(Sub
)
2373 : LaneBitmask::getAll();
2376 hasSubRegDef
= true;
2377 // An operand %0:sub0 reads %0:sub1..n. Invert the lane
2378 // mask for subregister defs. Read-undef defs will be handled by
2385 if (LaneMask
.any() && (LaneMask
& SLM
).none())
2387 if (MOI
->readsReg())
2390 if (S
.end
.isDead()) {
2391 // Make sure that the corresponding machine operand for a "dead" live
2392 // range has the dead flag. We cannot perform this check for subregister
2393 // liveranges as partially dead values are allowed.
2394 if (LaneMask
.none() && !hasDeadDef
) {
2395 report("Instruction ending live segment on dead slot has no dead flag",
2397 report_context(LR
, Reg
, LaneMask
);
2402 // When tracking subregister liveness, the main range must start new
2403 // values on partial register writes, even if there is no read.
2404 if (!MRI
->shouldTrackSubRegLiveness(Reg
) || LaneMask
.any() ||
2406 report("Instruction ending live segment doesn't read the register",
2408 report_context(LR
, Reg
, LaneMask
);
2415 // Now check all the basic blocks in this live segment.
2416 MachineFunction::const_iterator MFI
= MBB
->getIterator();
2417 // Is this live segment the beginning of a non-PHIDef VN?
2418 if (S
.start
== VNI
->def
&& !VNI
->isPHIDef()) {
2419 // Not live-in to any blocks.
2426 SmallVector
<SlotIndex
, 4> Undefs
;
2427 if (LaneMask
.any()) {
2428 LiveInterval
&OwnerLI
= LiveInts
->getInterval(Reg
);
2429 OwnerLI
.computeSubRangeUndefs(Undefs
, LaneMask
, *MRI
, *Indexes
);
2433 assert(LiveInts
->isLiveInToMBB(LR
, &*MFI
));
2434 // We don't know how to track physregs into a landing pad.
2435 if (!TargetRegisterInfo::isVirtualRegister(Reg
) &&
2437 if (&*MFI
== EndMBB
)
2443 // Is VNI a PHI-def in the current block?
2444 bool IsPHI
= VNI
->isPHIDef() &&
2445 VNI
->def
== LiveInts
->getMBBStartIdx(&*MFI
);
2447 // Check that VNI is live-out of all predecessors.
2448 for (MachineBasicBlock::const_pred_iterator PI
= MFI
->pred_begin(),
2449 PE
= MFI
->pred_end(); PI
!= PE
; ++PI
) {
2450 SlotIndex PEnd
= LiveInts
->getMBBEndIdx(*PI
);
2451 const VNInfo
*PVNI
= LR
.getVNInfoBefore(PEnd
);
2453 // All predecessors must have a live-out value. However for a phi
2454 // instruction with subregister intervals
2455 // only one of the subregisters (not necessarily the current one) needs to
2457 if (!PVNI
&& (LaneMask
.none() || !IsPHI
)) {
2458 if (LiveRangeCalc::isJointlyDominated(*PI
, Undefs
, *Indexes
))
2460 report("Register not marked live out of predecessor", *PI
);
2461 report_context(LR
, Reg
, LaneMask
);
2462 report_context(*VNI
);
2463 errs() << " live into " << printMBBReference(*MFI
) << '@'
2464 << LiveInts
->getMBBStartIdx(&*MFI
) << ", not live before "
2469 // Only PHI-defs can take different predecessor values.
2470 if (!IsPHI
&& PVNI
!= VNI
) {
2471 report("Different value live out of predecessor", *PI
);
2472 report_context(LR
, Reg
, LaneMask
);
2473 errs() << "Valno #" << PVNI
->id
<< " live out of "
2474 << printMBBReference(*(*PI
)) << '@' << PEnd
<< "\nValno #"
2475 << VNI
->id
<< " live into " << printMBBReference(*MFI
) << '@'
2476 << LiveInts
->getMBBStartIdx(&*MFI
) << '\n';
2479 if (&*MFI
== EndMBB
)
2485 void MachineVerifier::verifyLiveRange(const LiveRange
&LR
, unsigned Reg
,
2486 LaneBitmask LaneMask
) {
2487 for (const VNInfo
*VNI
: LR
.valnos
)
2488 verifyLiveRangeValue(LR
, VNI
, Reg
, LaneMask
);
2490 for (LiveRange::const_iterator I
= LR
.begin(), E
= LR
.end(); I
!= E
; ++I
)
2491 verifyLiveRangeSegment(LR
, I
, Reg
, LaneMask
);
2494 void MachineVerifier::verifyLiveInterval(const LiveInterval
&LI
) {
2495 unsigned Reg
= LI
.reg
;
2496 assert(TargetRegisterInfo::isVirtualRegister(Reg
));
2497 verifyLiveRange(LI
, Reg
);
2500 LaneBitmask MaxMask
= MRI
->getMaxLaneMaskForVReg(Reg
);
2501 for (const LiveInterval::SubRange
&SR
: LI
.subranges()) {
2502 if ((Mask
& SR
.LaneMask
).any()) {
2503 report("Lane masks of sub ranges overlap in live interval", MF
);
2506 if ((SR
.LaneMask
& ~MaxMask
).any()) {
2507 report("Subrange lanemask is invalid", MF
);
2511 report("Subrange must not be empty", MF
);
2512 report_context(SR
, LI
.reg
, SR
.LaneMask
);
2514 Mask
|= SR
.LaneMask
;
2515 verifyLiveRange(SR
, LI
.reg
, SR
.LaneMask
);
2516 if (!LI
.covers(SR
)) {
2517 report("A Subrange is not covered by the main range", MF
);
2522 // Check the LI only has one connected component.
2523 ConnectedVNInfoEqClasses
ConEQ(*LiveInts
);
2524 unsigned NumComp
= ConEQ
.Classify(LI
);
2526 report("Multiple connected components in live interval", MF
);
2528 for (unsigned comp
= 0; comp
!= NumComp
; ++comp
) {
2529 errs() << comp
<< ": valnos";
2530 for (LiveInterval::const_vni_iterator I
= LI
.vni_begin(),
2531 E
= LI
.vni_end(); I
!=E
; ++I
)
2532 if (comp
== ConEQ
.getEqClass(*I
))
2533 errs() << ' ' << (*I
)->id
;
2541 // FrameSetup and FrameDestroy can have zero adjustment, so using a single
2542 // integer, we can't tell whether it is a FrameSetup or FrameDestroy if the
2544 // We use a bool plus an integer to capture the stack state.
2545 struct StackStateOfBB
{
2546 StackStateOfBB() = default;
2547 StackStateOfBB(int EntryVal
, int ExitVal
, bool EntrySetup
, bool ExitSetup
) :
2548 EntryValue(EntryVal
), ExitValue(ExitVal
), EntryIsSetup(EntrySetup
),
2549 ExitIsSetup(ExitSetup
) {}
2551 // Can be negative, which means we are setting up a frame.
2554 bool EntryIsSetup
= false;
2555 bool ExitIsSetup
= false;
2558 } // end anonymous namespace
2560 /// Make sure on every path through the CFG, a FrameSetup <n> is always followed
2561 /// by a FrameDestroy <n>, stack adjustments are identical on all
2562 /// CFG edges to a merge point, and frame is destroyed at end of a return block.
2563 void MachineVerifier::verifyStackFrame() {
2564 unsigned FrameSetupOpcode
= TII
->getCallFrameSetupOpcode();
2565 unsigned FrameDestroyOpcode
= TII
->getCallFrameDestroyOpcode();
2566 if (FrameSetupOpcode
== ~0u && FrameDestroyOpcode
== ~0u)
2569 SmallVector
<StackStateOfBB
, 8> SPState
;
2570 SPState
.resize(MF
->getNumBlockIDs());
2571 df_iterator_default_set
<const MachineBasicBlock
*> Reachable
;
2573 // Visit the MBBs in DFS order.
2574 for (df_ext_iterator
<const MachineFunction
*,
2575 df_iterator_default_set
<const MachineBasicBlock
*>>
2576 DFI
= df_ext_begin(MF
, Reachable
), DFE
= df_ext_end(MF
, Reachable
);
2577 DFI
!= DFE
; ++DFI
) {
2578 const MachineBasicBlock
*MBB
= *DFI
;
2580 StackStateOfBB BBState
;
2581 // Check the exit state of the DFS stack predecessor.
2582 if (DFI
.getPathLength() >= 2) {
2583 const MachineBasicBlock
*StackPred
= DFI
.getPath(DFI
.getPathLength() - 2);
2584 assert(Reachable
.count(StackPred
) &&
2585 "DFS stack predecessor is already visited.\n");
2586 BBState
.EntryValue
= SPState
[StackPred
->getNumber()].ExitValue
;
2587 BBState
.EntryIsSetup
= SPState
[StackPred
->getNumber()].ExitIsSetup
;
2588 BBState
.ExitValue
= BBState
.EntryValue
;
2589 BBState
.ExitIsSetup
= BBState
.EntryIsSetup
;
2592 // Update stack state by checking contents of MBB.
2593 for (const auto &I
: *MBB
) {
2594 if (I
.getOpcode() == FrameSetupOpcode
) {
2595 if (BBState
.ExitIsSetup
)
2596 report("FrameSetup is after another FrameSetup", &I
);
2597 BBState
.ExitValue
-= TII
->getFrameTotalSize(I
);
2598 BBState
.ExitIsSetup
= true;
2601 if (I
.getOpcode() == FrameDestroyOpcode
) {
2602 int Size
= TII
->getFrameTotalSize(I
);
2603 if (!BBState
.ExitIsSetup
)
2604 report("FrameDestroy is not after a FrameSetup", &I
);
2605 int AbsSPAdj
= BBState
.ExitValue
< 0 ? -BBState
.ExitValue
:
2607 if (BBState
.ExitIsSetup
&& AbsSPAdj
!= Size
) {
2608 report("FrameDestroy <n> is after FrameSetup <m>", &I
);
2609 errs() << "FrameDestroy <" << Size
<< "> is after FrameSetup <"
2610 << AbsSPAdj
<< ">.\n";
2612 BBState
.ExitValue
+= Size
;
2613 BBState
.ExitIsSetup
= false;
2616 SPState
[MBB
->getNumber()] = BBState
;
2618 // Make sure the exit state of any predecessor is consistent with the entry
2620 for (MachineBasicBlock::const_pred_iterator I
= MBB
->pred_begin(),
2621 E
= MBB
->pred_end(); I
!= E
; ++I
) {
2622 if (Reachable
.count(*I
) &&
2623 (SPState
[(*I
)->getNumber()].ExitValue
!= BBState
.EntryValue
||
2624 SPState
[(*I
)->getNumber()].ExitIsSetup
!= BBState
.EntryIsSetup
)) {
2625 report("The exit stack state of a predecessor is inconsistent.", MBB
);
2626 errs() << "Predecessor " << printMBBReference(*(*I
))
2627 << " has exit state (" << SPState
[(*I
)->getNumber()].ExitValue
2628 << ", " << SPState
[(*I
)->getNumber()].ExitIsSetup
<< "), while "
2629 << printMBBReference(*MBB
) << " has entry state ("
2630 << BBState
.EntryValue
<< ", " << BBState
.EntryIsSetup
<< ").\n";
2634 // Make sure the entry state of any successor is consistent with the exit
2636 for (MachineBasicBlock::const_succ_iterator I
= MBB
->succ_begin(),
2637 E
= MBB
->succ_end(); I
!= E
; ++I
) {
2638 if (Reachable
.count(*I
) &&
2639 (SPState
[(*I
)->getNumber()].EntryValue
!= BBState
.ExitValue
||
2640 SPState
[(*I
)->getNumber()].EntryIsSetup
!= BBState
.ExitIsSetup
)) {
2641 report("The entry stack state of a successor is inconsistent.", MBB
);
2642 errs() << "Successor " << printMBBReference(*(*I
))
2643 << " has entry state (" << SPState
[(*I
)->getNumber()].EntryValue
2644 << ", " << SPState
[(*I
)->getNumber()].EntryIsSetup
<< "), while "
2645 << printMBBReference(*MBB
) << " has exit state ("
2646 << BBState
.ExitValue
<< ", " << BBState
.ExitIsSetup
<< ").\n";
2650 // Make sure a basic block with return ends with zero stack adjustment.
2651 if (!MBB
->empty() && MBB
->back().isReturn()) {
2652 if (BBState
.ExitIsSetup
)
2653 report("A return block ends with a FrameSetup.", MBB
);
2654 if (BBState
.ExitValue
)
2655 report("A return block ends with a nonzero stack adjustment.", MBB
);