lib/CodeGen/TargetPassConfig.cpp

   1 //===- TargetPassConfig.cpp - Target independent code generation passes ---===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines interfaces to access the target independent code
  10 // generation passes provided by the LLVM backend.
  11 //
  12 //===---------------------------------------------------------------------===//
  13
  14 #include "llvm/CodeGen/TargetPassConfig.h"
  15 #include "llvm/ADT/DenseMap.h"
  16 #include "llvm/ADT/SmallVector.h"
  17 #include "llvm/ADT/StringRef.h"
  18 #include "llvm/Analysis/BasicAliasAnalysis.h"
  19 #include "llvm/Analysis/CFLAndersAliasAnalysis.h"
  20 #include "llvm/Analysis/CFLSteensAliasAnalysis.h"
  21 #include "llvm/Analysis/CallGraphSCCPass.h"
  22 #include "llvm/Analysis/ScopedNoAliasAA.h"
  23 #include "llvm/Analysis/TargetTransformInfo.h"
  24 #include "llvm/Analysis/TypeBasedAliasAnalysis.h"
  25 #include "llvm/CodeGen/MachineFunctionPass.h"
  26 #include "llvm/CodeGen/MachinePassRegistry.h"
  27 #include "llvm/CodeGen/Passes.h"
  28 #include "llvm/CodeGen/RegAllocRegistry.h"
  29 #include "llvm/IR/IRPrintingPasses.h"
  30 #include "llvm/IR/LegacyPassManager.h"
  31 #include "llvm/IR/Verifier.h"
  32 #include "llvm/MC/MCAsmInfo.h"
  33 #include "llvm/MC/MCTargetOptions.h"
  34 #include "llvm/Pass.h"
  35 #include "llvm/Support/CodeGen.h"
  36 #include "llvm/Support/CommandLine.h"
  37 #include "llvm/Support/Compiler.h"
  38 #include "llvm/Support/Debug.h"
  39 #include "llvm/Support/ErrorHandling.h"
  40 #include "llvm/Support/Threading.h"
  41 #include "llvm/Support/SaveAndRestore.h"
  42 #include "llvm/Target/TargetMachine.h"
  43 #include "llvm/Transforms/Scalar.h"
  44 #include "llvm/Transforms/Utils.h"
  45 #include "llvm/Transforms/Utils/SymbolRewriter.h"
  46 #include <cassert>
  47 #include <string>
  48
  49 using namespace llvm;
  50
  51 cl::opt<bool> EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
  52                          cl::desc("Enable interprocedural register allocation "
  53                                   "to reduce load/store at procedure calls."));
  54 static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
  55     cl::desc("Disable Post Regalloc Scheduler"));
  56 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
  57     cl::desc("Disable branch folding"));
  58 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
  59     cl::desc("Disable tail duplication"));
  60 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
  61     cl::desc("Disable pre-register allocation tail duplication"));
  62 static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
  63     cl::Hidden, cl::desc("Disable probability-driven block placement"));
  64 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
  65     cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
  66 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
  67     cl::desc("Disable Stack Slot Coloring"));
  68 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
  69     cl::desc("Disable Machine Dead Code Elimination"));
  70 static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
  71     cl::desc("Disable Early If-conversion"));
  72 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
  73     cl::desc("Disable Machine LICM"));
  74 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
  75     cl::desc("Disable Machine Common Subexpression Elimination"));
  76 static cl::opt<cl::boolOrDefault> OptimizeRegAlloc(
  77     "optimize-regalloc", cl::Hidden,
  78     cl::desc("Enable optimized register allocation compilation path."));
  79 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
  80     cl::Hidden,
  81     cl::desc("Disable Machine LICM"));
  82 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
  83     cl::desc("Disable Machine Sinking"));
  84 static cl::opt<bool> DisablePostRAMachineSink("disable-postra-machine-sink",
  85     cl::Hidden,
  86     cl::desc("Disable PostRA Machine Sinking"));
  87 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
  88     cl::desc("Disable Loop Strength Reduction Pass"));
  89 static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
  90     cl::Hidden, cl::desc("Disable ConstantHoisting"));
  91 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
  92     cl::desc("Disable Codegen Prepare"));
  93 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
  94     cl::desc("Disable Copy Propagation pass"));
  95 static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
  96     cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
  97 static cl::opt<bool> EnableImplicitNullChecks(
  98     "enable-implicit-null-checks",
  99     cl::desc("Fold null checks into faulting memory operations"),
 100     cl::init(false), cl::Hidden);
 101 static cl::opt<bool> DisableMergeICmps("disable-mergeicmps",
 102     cl::desc("Disable MergeICmps Pass"),
 103     cl::init(false), cl::Hidden);
 104 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
 105     cl::desc("Print LLVM IR produced by the loop-reduce pass"));
 106 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
 107     cl::desc("Print LLVM IR input to isel pass"));
 108 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
 109     cl::desc("Dump garbage collector data"));
 110 static cl::opt<cl::boolOrDefault>
 111     VerifyMachineCode("verify-machineinstrs", cl::Hidden,
 112                       cl::desc("Verify generated machine code"),
 113                       cl::ZeroOrMore);
 114 enum RunOutliner { AlwaysOutline, NeverOutline, TargetDefault };
 115 // Enable or disable the MachineOutliner.
 116 static cl::opt<RunOutliner> EnableMachineOutliner(
 117     "enable-machine-outliner", cl::desc("Enable the machine outliner"),
 118     cl::Hidden, cl::ValueOptional, cl::init(TargetDefault),
 119     cl::values(clEnumValN(AlwaysOutline, "always",
 120                           "Run on all functions guaranteed to be beneficial"),
 121                clEnumValN(NeverOutline, "never", "Disable all outlining"),
 122                // Sentinel value for unspecified option.
 123                clEnumValN(AlwaysOutline, "", "")));
 124 // Enable or disable FastISel. Both options are needed, because
 125 // FastISel is enabled by default with -fast, and we wish to be
 126 // able to enable or disable fast-isel independently from -O0.
 127 static cl::opt<cl::boolOrDefault>
 128 EnableFastISelOption("fast-isel", cl::Hidden,
 129   cl::desc("Enable the \"fast\" instruction selector"));
 130
 131 static cl::opt<cl::boolOrDefault> EnableGlobalISelOption(
 132     "global-isel", cl::Hidden,
 133     cl::desc("Enable the \"global\" instruction selector"));
 134
 135 static cl::opt<std::string> PrintMachineInstrs(
 136     "print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"),
 137     cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden);
 138
 139 static cl::opt<GlobalISelAbortMode> EnableGlobalISelAbort(
 140     "global-isel-abort", cl::Hidden,
 141     cl::desc("Enable abort calls when \"global\" instruction selection "
 142              "fails to lower/select an instruction"),
 143     cl::values(
 144         clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"),
 145         clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"),
 146         clEnumValN(GlobalISelAbortMode::DisableWithDiag, "2",
 147                    "Disable the abort but emit a diagnostic on failure")));
 148
 149 // Temporary option to allow experimenting with MachineScheduler as a post-RA
 150 // scheduler. Targets can "properly" enable this with
 151 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
 152 // Targets can return true in targetSchedulesPostRAScheduling() and
 153 // insert a PostRA scheduling pass wherever it wants.
 154 cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
 155   cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
 156
 157 // Experimental option to run live interval analysis early.
 158 static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
 159     cl::desc("Run live interval analysis earlier in the pipeline"));
 160
 161 // Experimental option to use CFL-AA in codegen
 162 enum class CFLAAType { None, Steensgaard, Andersen, Both };
 163 static cl::opt<CFLAAType> UseCFLAA(
 164     "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
 165     cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"),
 166     cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"),
 167                clEnumValN(CFLAAType::Steensgaard, "steens",
 168                           "Enable unification-based CFL-AA"),
 169                clEnumValN(CFLAAType::Andersen, "anders",
 170                           "Enable inclusion-based CFL-AA"),
 171                clEnumValN(CFLAAType::Both, "both",
 172                           "Enable both variants of CFL-AA")));
 173
 174 /// Option names for limiting the codegen pipeline.
 175 /// Those are used in error reporting and we didn't want
 176 /// to duplicate their names all over the place.
 177 const char *StartAfterOptName = "start-after";
 178 const char *StartBeforeOptName = "start-before";
 179 const char *StopAfterOptName = "stop-after";
 180 const char *StopBeforeOptName = "stop-before";
 181
 182 static cl::opt<std::string>
 183     StartAfterOpt(StringRef(StartAfterOptName),
 184                   cl::desc("Resume compilation after a specific pass"),
 185                   cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
 186
 187 static cl::opt<std::string>
 188     StartBeforeOpt(StringRef(StartBeforeOptName),
 189                    cl::desc("Resume compilation before a specific pass"),
 190                    cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
 191
 192 static cl::opt<std::string>
 193     StopAfterOpt(StringRef(StopAfterOptName),
 194                  cl::desc("Stop compilation after a specific pass"),
 195                  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
 196
 197 static cl::opt<std::string>
 198     StopBeforeOpt(StringRef(StopBeforeOptName),
 199                   cl::desc("Stop compilation before a specific pass"),
 200                   cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
 201
 202 /// Allow standard passes to be disabled by command line options. This supports
 203 /// simple binary flags that either suppress the pass or do nothing.
 204 /// i.e. -disable-mypass=false has no effect.
 205 /// These should be converted to boolOrDefault in order to use applyOverride.
 206 static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID,
 207                                        bool Override) {
 208   if (Override)
 209     return IdentifyingPassPtr();
 210   return PassID;
 211 }
 212
 213 /// Allow standard passes to be disabled by the command line, regardless of who
 214 /// is adding the pass.
 215 ///
 216 /// StandardID is the pass identified in the standard pass pipeline and provided
 217 /// to addPass(). It may be a target-specific ID in the case that the target
 218 /// directly adds its own pass, but in that case we harmlessly fall through.
 219 ///
 220 /// TargetID is the pass that the target has configured to override StandardID.
 221 ///
 222 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
 223 /// pass to run. This allows multiple options to control a single pass depending
 224 /// on where in the pipeline that pass is added.
 225 static IdentifyingPassPtr overridePass(AnalysisID StandardID,
 226                                        IdentifyingPassPtr TargetID) {
 227   if (StandardID == &PostRASchedulerID)
 228     return applyDisable(TargetID, DisablePostRASched);
 229
 230   if (StandardID == &BranchFolderPassID)
 231     return applyDisable(TargetID, DisableBranchFold);
 232
 233   if (StandardID == &TailDuplicateID)
 234     return applyDisable(TargetID, DisableTailDuplicate);
 235
 236   if (StandardID == &EarlyTailDuplicateID)
 237     return applyDisable(TargetID, DisableEarlyTailDup);
 238
 239   if (StandardID == &MachineBlockPlacementID)
 240     return applyDisable(TargetID, DisableBlockPlacement);
 241
 242   if (StandardID == &StackSlotColoringID)
 243     return applyDisable(TargetID, DisableSSC);
 244
 245   if (StandardID == &DeadMachineInstructionElimID)
 246     return applyDisable(TargetID, DisableMachineDCE);
 247
 248   if (StandardID == &EarlyIfConverterID)
 249     return applyDisable(TargetID, DisableEarlyIfConversion);
 250
 251   if (StandardID == &EarlyMachineLICMID)
 252     return applyDisable(TargetID, DisableMachineLICM);
 253
 254   if (StandardID == &MachineCSEID)
 255     return applyDisable(TargetID, DisableMachineCSE);
 256
 257   if (StandardID == &MachineLICMID)
 258     return applyDisable(TargetID, DisablePostRAMachineLICM);
 259
 260   if (StandardID == &MachineSinkingID)
 261     return applyDisable(TargetID, DisableMachineSink);
 262
 263   if (StandardID == &PostRAMachineSinkingID)
 264     return applyDisable(TargetID, DisablePostRAMachineSink);
 265
 266   if (StandardID == &MachineCopyPropagationID)
 267     return applyDisable(TargetID, DisableCopyProp);
 268
 269   return TargetID;
 270 }
 271
 272 //===---------------------------------------------------------------------===//
 273 /// TargetPassConfig
 274 //===---------------------------------------------------------------------===//
 275
 276 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
 277                 "Target Pass Configuration", false, false)
 278 char TargetPassConfig::ID = 0;
 279
 280 namespace {
 281
 282 struct InsertedPass {
 283   AnalysisID TargetPassID;
 284   IdentifyingPassPtr InsertedPassID;
 285   bool VerifyAfter;
 286   bool PrintAfter;
 287
 288   InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
 289                bool VerifyAfter, bool PrintAfter)
 290       : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
 291         VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {}
 292
 293   Pass *getInsertedPass() const {
 294     assert(InsertedPassID.isValid() && "Illegal Pass ID!");
 295     if (InsertedPassID.isInstance())
 296       return InsertedPassID.getInstance();
 297     Pass *NP = Pass::createPass(InsertedPassID.getID());
 298     assert(NP && "Pass ID not registered");
 299     return NP;
 300   }
 301 };
 302
 303 } // end anonymous namespace
 304
 305 namespace llvm {
 306
 307 class PassConfigImpl {
 308 public:
 309   // List of passes explicitly substituted by this target. Normally this is
 310   // empty, but it is a convenient way to suppress or replace specific passes
 311   // that are part of a standard pass pipeline without overridding the entire
 312   // pipeline. This mechanism allows target options to inherit a standard pass's
 313   // user interface. For example, a target may disable a standard pass by
 314   // default by substituting a pass ID of zero, and the user may still enable
 315   // that standard pass with an explicit command line option.
 316   DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses;
 317
 318   /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
 319   /// is inserted after each instance of the first one.
 320   SmallVector<InsertedPass, 4> InsertedPasses;
 321 };
 322
 323 } // end namespace llvm
 324
 325 // Out of line virtual method.
 326 TargetPassConfig::~TargetPassConfig() {
 327   delete Impl;
 328 }
 329
 330 static const PassInfo *getPassInfo(StringRef PassName) {
 331   if (PassName.empty())
 332     return nullptr;
 333
 334   const PassRegistry &PR = *PassRegistry::getPassRegistry();
 335   const PassInfo *PI = PR.getPassInfo(PassName);
 336   if (!PI)
 337     report_fatal_error(Twine('\"') + Twine(PassName) +
 338                        Twine("\" pass is not registered."));
 339   return PI;
 340 }
 341
 342 static AnalysisID getPassIDFromName(StringRef PassName) {
 343   const PassInfo *PI = getPassInfo(PassName);
 344   return PI ? PI->getTypeInfo() : nullptr;
 345 }
 346
 347 static std::pair<StringRef, unsigned>
 348 getPassNameAndInstanceNum(StringRef PassName) {
 349   StringRef Name, InstanceNumStr;
 350   std::tie(Name, InstanceNumStr) = PassName.split(',');
 351
 352   unsigned InstanceNum = 0;
 353   if (!InstanceNumStr.empty() && InstanceNumStr.getAsInteger(10, InstanceNum))
 354     report_fatal_error("invalid pass instance specifier " + PassName);
 355
 356   return std::make_pair(Name, InstanceNum);
 357 }
 358
 359 void TargetPassConfig::setStartStopPasses() {
 360   StringRef StartBeforeName;
 361   std::tie(StartBeforeName, StartBeforeInstanceNum) =
 362     getPassNameAndInstanceNum(StartBeforeOpt);
 363
 364   StringRef StartAfterName;
 365   std::tie(StartAfterName, StartAfterInstanceNum) =
 366     getPassNameAndInstanceNum(StartAfterOpt);
 367
 368   StringRef StopBeforeName;
 369   std::tie(StopBeforeName, StopBeforeInstanceNum)
 370     = getPassNameAndInstanceNum(StopBeforeOpt);
 371
 372   StringRef StopAfterName;
 373   std::tie(StopAfterName, StopAfterInstanceNum)
 374     = getPassNameAndInstanceNum(StopAfterOpt);
 375
 376   StartBefore = getPassIDFromName(StartBeforeName);
 377   StartAfter = getPassIDFromName(StartAfterName);
 378   StopBefore = getPassIDFromName(StopBeforeName);
 379   StopAfter = getPassIDFromName(StopAfterName);
 380   if (StartBefore && StartAfter)
 381     report_fatal_error(Twine(StartBeforeOptName) + Twine(" and ") +
 382                        Twine(StartAfterOptName) + Twine(" specified!"));
 383   if (StopBefore && StopAfter)
 384     report_fatal_error(Twine(StopBeforeOptName) + Twine(" and ") +
 385                        Twine(StopAfterOptName) + Twine(" specified!"));
 386   Started = (StartAfter == nullptr) && (StartBefore == nullptr);
 387 }
 388
 389 // Out of line constructor provides default values for pass options and
 390 // registers all common codegen passes.
 391 TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm)
 392     : ImmutablePass(ID), PM(&pm), TM(&TM) {
 393   Impl = new PassConfigImpl();
 394
 395   // Register all target independent codegen passes to activate their PassIDs,
 396   // including this pass itself.
 397   initializeCodeGen(*PassRegistry::getPassRegistry());
 398
 399   // Also register alias analysis passes required by codegen passes.
 400   initializeBasicAAWrapperPassPass(*PassRegistry::getPassRegistry());
 401   initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
 402
 403   if (StringRef(PrintMachineInstrs.getValue()).equals(""))
 404     TM.Options.PrintMachineCode = true;
 405
 406   if (EnableIPRA.getNumOccurrences())
 407     TM.Options.EnableIPRA = EnableIPRA;
 408   else {
 409     // If not explicitly specified, use target default.
 410     TM.Options.EnableIPRA = TM.useIPRA();
 411   }
 412
 413   if (TM.Options.EnableIPRA)
 414     setRequiresCodeGenSCCOrder();
 415
 416   if (EnableGlobalISelAbort.getNumOccurrences())
 417     TM.Options.GlobalISelAbort = EnableGlobalISelAbort;
 418
 419   setStartStopPasses();
 420 }
 421
 422 CodeGenOpt::Level TargetPassConfig::getOptLevel() const {
 423   return TM->getOptLevel();
 424 }
 425
 426 /// Insert InsertedPassID pass after TargetPassID.
 427 void TargetPassConfig::insertPass(AnalysisID TargetPassID,
 428                                   IdentifyingPassPtr InsertedPassID,
 429                                   bool VerifyAfter, bool PrintAfter) {
 430   assert(((!InsertedPassID.isInstance() &&
 431            TargetPassID != InsertedPassID.getID()) ||
 432           (InsertedPassID.isInstance() &&
 433            TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
 434          "Insert a pass after itself!");
 435   Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter,
 436                                     PrintAfter);
 437 }
 438
 439 /// createPassConfig - Create a pass configuration object to be used by
 440 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
 441 ///
 442 /// Targets may override this to extend TargetPassConfig.
 443 TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
 444   return new TargetPassConfig(*this, PM);
 445 }
 446
 447 TargetPassConfig::TargetPassConfig()
 448   : ImmutablePass(ID) {
 449   report_fatal_error("Trying to construct TargetPassConfig without a target "
 450                      "machine. Scheduling a CodeGen pass without a target "
 451                      "triple set?");
 452 }
 453
 454 bool TargetPassConfig::willCompleteCodeGenPipeline() {
 455   return StopBeforeOpt.empty() && StopAfterOpt.empty();
 456 }
 457
 458 bool TargetPassConfig::hasLimitedCodeGenPipeline() {
 459   return !StartBeforeOpt.empty() || !StartAfterOpt.empty() ||
 460          !willCompleteCodeGenPipeline();
 461 }
 462
 463 std::string
 464 TargetPassConfig::getLimitedCodeGenPipelineReason(const char *Separator) const {
 465   if (!hasLimitedCodeGenPipeline())
 466     return std::string();
 467   std::string Res;
 468   static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
 469                                               &StopAfterOpt, &StopBeforeOpt};
 470   static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
 471                                    StopAfterOptName, StopBeforeOptName};
 472   bool IsFirst = true;
 473   for (int Idx = 0; Idx < 4; ++Idx)
 474     if (!PassNames[Idx]->empty()) {
 475       if (!IsFirst)
 476         Res += Separator;
 477       IsFirst = false;
 478       Res += OptNames[Idx];
 479     }
 480   return Res;
 481 }
 482
 483 // Helper to verify the analysis is really immutable.
 484 void TargetPassConfig::setOpt(bool &Opt, bool Val) {
 485   assert(!Initialized && "PassConfig is immutable");
 486   Opt = Val;
 487 }
 488
 489 void TargetPassConfig::substitutePass(AnalysisID StandardID,
 490                                       IdentifyingPassPtr TargetID) {
 491   Impl->TargetPasses[StandardID] = TargetID;
 492 }
 493
 494 IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
 495   DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator
 496     I = Impl->TargetPasses.find(ID);
 497   if (I == Impl->TargetPasses.end())
 498     return ID;
 499   return I->second;
 500 }
 501
 502 bool TargetPassConfig::isPassSubstitutedOrOverridden(AnalysisID ID) const {
 503   IdentifyingPassPtr TargetID = getPassSubstitution(ID);
 504   IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
 505   return !FinalPtr.isValid() || FinalPtr.isInstance() ||
 506       FinalPtr.getID() != ID;
 507 }
 508
 509 /// Add a pass to the PassManager if that pass is supposed to be run.  If the
 510 /// Started/Stopped flags indicate either that the compilation should start at
 511 /// a later pass or that it should stop after an earlier pass, then do not add
 512 /// the pass.  Finally, compare the current pass against the StartAfter
 513 /// and StopAfter options and change the Started/Stopped flags accordingly.
 514 void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
 515   assert(!Initialized && "PassConfig is immutable");
 516
 517   // Cache the Pass ID here in case the pass manager finds this pass is
 518   // redundant with ones already scheduled / available, and deletes it.
 519   // Fundamentally, once we add the pass to the manager, we no longer own it
 520   // and shouldn't reference it.
 521   AnalysisID PassID = P->getPassID();
 522
 523   if (StartBefore == PassID && StartBeforeCount++ == StartBeforeInstanceNum)
 524     Started = true;
 525   if (StopBefore == PassID && StopBeforeCount++ == StopBeforeInstanceNum)
 526     Stopped = true;
 527   if (Started && !Stopped) {
 528     std::string Banner;
 529     // Construct banner message before PM->add() as that may delete the pass.
 530     if (AddingMachinePasses && (printAfter || verifyAfter))
 531       Banner = std::string("After ") + std::string(P->getPassName());
 532     PM->add(P);
 533     if (AddingMachinePasses) {
 534       if (printAfter)
 535         addPrintPass(Banner);
 536       if (verifyAfter)
 537         addVerifyPass(Banner);
 538     }
 539
 540     // Add the passes after the pass P if there is any.
 541     for (auto IP : Impl->InsertedPasses) {
 542       if (IP.TargetPassID == PassID)
 543         addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter);
 544     }
 545   } else {
 546     delete P;
 547   }
 548
 549   if (StopAfter == PassID && StopAfterCount++ == StopAfterInstanceNum)
 550     Stopped = true;
 551
 552   if (StartAfter == PassID && StartAfterCount++ == StartAfterInstanceNum)
 553     Started = true;
 554   if (Stopped && !Started)
 555     report_fatal_error("Cannot stop compilation after pass that is not run");
 556 }
 557
 558 /// Add a CodeGen pass at this point in the pipeline after checking for target
 559 /// and command line overrides.
 560 ///
 561 /// addPass cannot return a pointer to the pass instance because is internal the
 562 /// PassManager and the instance we create here may already be freed.
 563 AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
 564                                      bool printAfter) {
 565   IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
 566   IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
 567   if (!FinalPtr.isValid())
 568     return nullptr;
 569
 570   Pass *P;
 571   if (FinalPtr.isInstance())
 572     P = FinalPtr.getInstance();
 573   else {
 574     P = Pass::createPass(FinalPtr.getID());
 575     if (!P)
 576       llvm_unreachable("Pass ID not registered");
 577   }
 578   AnalysisID FinalID = P->getPassID();
 579   addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
 580
 581   return FinalID;
 582 }
 583
 584 void TargetPassConfig::printAndVerify(const std::string &Banner) {
 585   addPrintPass(Banner);
 586   addVerifyPass(Banner);
 587 }
 588
 589 void TargetPassConfig::addPrintPass(const std::string &Banner) {
 590   if (TM->shouldPrintMachineCode())
 591     PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
 592 }
 593
 594 void TargetPassConfig::addVerifyPass(const std::string &Banner) {
 595   bool Verify = VerifyMachineCode == cl::BOU_TRUE;
 596 #ifdef EXPENSIVE_CHECKS
 597   if (VerifyMachineCode == cl::BOU_UNSET)
 598     Verify = TM->isMachineVerifierClean();
 599 #endif
 600   if (Verify)
 601     PM->add(createMachineVerifierPass(Banner));
 602 }
 603
 604 /// Add common target configurable passes that perform LLVM IR to IR transforms
 605 /// following machine independent optimization.
 606 void TargetPassConfig::addIRPasses() {
 607   switch (UseCFLAA) {
 608   case CFLAAType::Steensgaard:
 609     addPass(createCFLSteensAAWrapperPass());
 610     break;
 611   case CFLAAType::Andersen:
 612     addPass(createCFLAndersAAWrapperPass());
 613     break;
 614   case CFLAAType::Both:
 615     addPass(createCFLAndersAAWrapperPass());
 616     addPass(createCFLSteensAAWrapperPass());
 617     break;
 618   default:
 619     break;
 620   }
 621
 622   // Basic AliasAnalysis support.
 623   // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
 624   // BasicAliasAnalysis wins if they disagree. This is intended to help
 625   // support "obvious" type-punning idioms.
 626   addPass(createTypeBasedAAWrapperPass());
 627   addPass(createScopedNoAliasAAWrapperPass());
 628   addPass(createBasicAAWrapperPass());
 629
 630   // Before running any passes, run the verifier to determine if the input
 631   // coming from the front-end and/or optimizer is valid.
 632   if (!DisableVerify)
 633     addPass(createVerifierPass());
 634
 635   // Run loop strength reduction before anything else.
 636   if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
 637     addPass(createLoopStrengthReducePass());
 638     if (PrintLSR)
 639       addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
 640   }
 641
 642   if (getOptLevel() != CodeGenOpt::None) {
 643     // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
 644     // loads and compares. ExpandMemCmpPass then tries to expand those calls
 645     // into optimally-sized loads and compares. The transforms are enabled by a
 646     // target lowering hook.
 647     if (!DisableMergeICmps)
 648       addPass(createMergeICmpsPass());
 649     addPass(createExpandMemCmpPass());
 650   }
 651
 652   // Run GC lowering passes for builtin collectors
 653   // TODO: add a pass insertion point here
 654   addPass(createGCLoweringPass());
 655   addPass(createShadowStackGCLoweringPass());
 656
 657   // Make sure that no unreachable blocks are instruction selected.
 658   addPass(createUnreachableBlockEliminationPass());
 659
 660   // Prepare expensive constants for SelectionDAG.
 661   if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting)
 662     addPass(createConstantHoistingPass());
 663
 664   if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining)
 665     addPass(createPartiallyInlineLibCallsPass());
 666
 667   // Instrument function entry and exit, e.g. with calls to mcount().
 668   addPass(createPostInlineEntryExitInstrumenterPass());
 669
 670   // Add scalarization of target's unsupported masked memory intrinsics pass.
 671   // the unsupported intrinsic will be replaced with a chain of basic blocks,
 672   // that stores/loads element one-by-one if the appropriate mask bit is set.
 673   addPass(createScalarizeMaskedMemIntrinPass());
 674
 675   // Expand reduction intrinsics into shuffle sequences if the target wants to.
 676   addPass(createExpandReductionsPass());
 677 }
 678
 679 /// Turn exception handling constructs into something the code generators can
 680 /// handle.
 681 void TargetPassConfig::addPassesToHandleExceptions() {
 682   const MCAsmInfo *MCAI = TM->getMCAsmInfo();
 683   assert(MCAI && "No MCAsmInfo");
 684   switch (MCAI->getExceptionHandlingType()) {
 685   case ExceptionHandling::SjLj:
 686     // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
 687     // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
 688     // catch info can get misplaced when a selector ends up more than one block
 689     // removed from the parent invoke(s). This could happen when a landing
 690     // pad is shared by multiple invokes and is also a target of a normal
 691     // edge from elsewhere.
 692     addPass(createSjLjEHPreparePass());
 693     LLVM_FALLTHROUGH;
 694   case ExceptionHandling::DwarfCFI:
 695   case ExceptionHandling::ARM:
 696     addPass(createDwarfEHPass());
 697     break;
 698   case ExceptionHandling::WinEH:
 699     // We support using both GCC-style and MSVC-style exceptions on Windows, so
 700     // add both preparation passes. Each pass will only actually run if it
 701     // recognizes the personality function.
 702     addPass(createWinEHPass());
 703     addPass(createDwarfEHPass());
 704     break;
 705   case ExceptionHandling::Wasm:
 706     // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
 707     // on catchpads and cleanuppads because it does not outline them into
 708     // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
 709     // should remove PHIs there.
 710     addPass(createWinEHPass(/*DemoteCatchSwitchPHIOnly=*/false));
 711     addPass(createWasmEHPass());
 712     break;
 713   case ExceptionHandling::None:
 714     addPass(createLowerInvokePass());
 715
 716     // The lower invoke pass may create unreachable code. Remove it.
 717     addPass(createUnreachableBlockEliminationPass());
 718     break;
 719   }
 720 }
 721
 722 /// Add pass to prepare the LLVM IR for code generation. This should be done
 723 /// before exception handling preparation passes.
 724 void TargetPassConfig::addCodeGenPrepare() {
 725   if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
 726     addPass(createCodeGenPreparePass());
 727   addPass(createRewriteSymbolsPass());
 728 }
 729
 730 /// Add common passes that perform LLVM IR to IR transforms in preparation for
 731 /// instruction selection.
 732 void TargetPassConfig::addISelPrepare() {
 733   addPreISel();
 734
 735   // Force codegen to run according to the callgraph.
 736   if (requiresCodeGenSCCOrder())
 737     addPass(new DummyCGSCCPass);
 738
 739   // Add both the safe stack and the stack protection passes: each of them will
 740   // only protect functions that have corresponding attributes.
 741   addPass(createSafeStackPass());
 742   addPass(createStackProtectorPass());
 743
 744   if (PrintISelInput)
 745     addPass(createPrintFunctionPass(
 746         dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
 747
 748   // All passes which modify the LLVM IR are now complete; run the verifier
 749   // to ensure that the IR is valid.
 750   if (!DisableVerify)
 751     addPass(createVerifierPass());
 752 }
 753
 754 bool TargetPassConfig::addCoreISelPasses() {
 755   // Enable FastISel with -fast-isel, but allow that to be overridden.
 756   TM->setO0WantsFastISel(EnableFastISelOption != cl::BOU_FALSE);
 757
 758   // Determine an instruction selector.
 759   enum class SelectorType { SelectionDAG, FastISel, GlobalISel };
 760   SelectorType Selector;
 761
 762   if (EnableFastISelOption == cl::BOU_TRUE)
 763     Selector = SelectorType::FastISel;
 764   else if (EnableGlobalISelOption == cl::BOU_TRUE ||
 765            (TM->Options.EnableGlobalISel &&
 766             EnableGlobalISelOption != cl::BOU_FALSE))
 767     Selector = SelectorType::GlobalISel;
 768   else if (TM->getOptLevel() == CodeGenOpt::None && TM->getO0WantsFastISel())
 769     Selector = SelectorType::FastISel;
 770   else
 771     Selector = SelectorType::SelectionDAG;
 772
 773   // Set consistently TM->Options.EnableFastISel and EnableGlobalISel.
 774   if (Selector == SelectorType::FastISel) {
 775     TM->setFastISel(true);
 776     TM->setGlobalISel(false);
 777   } else if (Selector == SelectorType::GlobalISel) {
 778     TM->setFastISel(false);
 779     TM->setGlobalISel(true);
 780   }
 781
 782   // Add instruction selector passes.
 783   if (Selector == SelectorType::GlobalISel) {
 784     SaveAndRestore<bool> SavedAddingMachinePasses(AddingMachinePasses, true);
 785     if (addIRTranslator())
 786       return true;
 787
 788     addPreLegalizeMachineIR();
 789
 790     if (addLegalizeMachineIR())
 791       return true;
 792
 793     // Before running the register bank selector, ask the target if it
 794     // wants to run some passes.
 795     addPreRegBankSelect();
 796
 797     if (addRegBankSelect())
 798       return true;
 799
 800     addPreGlobalInstructionSelect();
 801
 802     if (addGlobalInstructionSelect())
 803       return true;
 804
 805     // Pass to reset the MachineFunction if the ISel failed.
 806     addPass(createResetMachineFunctionPass(
 807         reportDiagnosticWhenGlobalISelFallback(), isGlobalISelAbortEnabled()));
 808
 809     // Provide a fallback path when we do not want to abort on
 810     // not-yet-supported input.
 811     if (!isGlobalISelAbortEnabled() && addInstSelector())
 812       return true;
 813
 814   } else if (addInstSelector())
 815     return true;
 816
 817   return false;
 818 }
 819
 820 bool TargetPassConfig::addISelPasses() {
 821   if (TM->useEmulatedTLS())
 822     addPass(createLowerEmuTLSPass());
 823
 824   addPass(createPreISelIntrinsicLoweringPass());
 825   addPass(createTargetTransformInfoWrapperPass(TM->getTargetIRAnalysis()));
 826   addIRPasses();
 827   addCodeGenPrepare();
 828   addPassesToHandleExceptions();
 829   addISelPrepare();
 830
 831   return addCoreISelPasses();
 832 }
 833
 834 /// -regalloc=... command line option.
 835 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
 836 static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
 837                RegisterPassParser<RegisterRegAlloc>>
 838     RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
 839              cl::desc("Register allocator to use"));
 840
 841 /// Add the complete set of target-independent postISel code generator passes.
 842 ///
 843 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
 844 /// with nontrivial configuration or multiple passes are broken out below in
 845 /// add%Stage routines.
 846 ///
 847 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
 848 /// addPre/Post methods with empty header implementations allow injecting
 849 /// target-specific fixups just before or after major stages. Additionally,
 850 /// targets have the flexibility to change pass order within a stage by
 851 /// overriding default implementation of add%Stage routines below. Each
 852 /// technique has maintainability tradeoffs because alternate pass orders are
 853 /// not well supported. addPre/Post works better if the target pass is easily
 854 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
 855 /// the target should override the stage instead.
 856 ///
 857 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
 858 /// before/after any target-independent pass. But it's currently overkill.
 859 void TargetPassConfig::addMachinePasses() {
 860   AddingMachinePasses = true;
 861
 862   // Insert a machine instr printer pass after the specified pass.
 863   StringRef PrintMachineInstrsPassName = PrintMachineInstrs.getValue();
 864   if (!PrintMachineInstrsPassName.equals("") &&
 865       !PrintMachineInstrsPassName.equals("option-unspecified")) {
 866     if (const PassInfo *TPI = getPassInfo(PrintMachineInstrsPassName)) {
 867       const PassRegistry *PR = PassRegistry::getPassRegistry();
 868       const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
 869       assert(IPI && "failed to get \"machineinstr-printer\" PassInfo!");
 870       const char *TID = (const char *)(TPI->getTypeInfo());
 871       const char *IID = (const char *)(IPI->getTypeInfo());
 872       insertPass(TID, IID);
 873     }
 874   }
 875
 876   // Print the instruction selected machine code...
 877   printAndVerify("After Instruction Selection");
 878
 879   // Expand pseudo-instructions emitted by ISel.
 880   addPass(&ExpandISelPseudosID);
 881
 882   // Add passes that optimize machine instructions in SSA form.
 883   if (getOptLevel() != CodeGenOpt::None) {
 884     addMachineSSAOptimization();
 885   } else {
 886     // If the target requests it, assign local variables to stack slots relative
 887     // to one another and simplify frame index references where possible.
 888     addPass(&LocalStackSlotAllocationID, false);
 889   }
 890
 891   if (TM->Options.EnableIPRA)
 892     addPass(createRegUsageInfoPropPass());
 893
 894   // Run pre-ra passes.
 895   addPreRegAlloc();
 896
 897   // Run register allocation and passes that are tightly coupled with it,
 898   // including phi elimination and scheduling.
 899   if (getOptimizeRegAlloc())
 900     addOptimizedRegAlloc(createRegAllocPass(true));
 901   else {
 902     if (RegAlloc != &useDefaultRegisterAllocator &&
 903         RegAlloc != &createFastRegisterAllocator)
 904       report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
 905     addFastRegAlloc(createRegAllocPass(false));
 906   }
 907
 908   // Run post-ra passes.
 909   addPostRegAlloc();
 910
 911   // Insert prolog/epilog code.  Eliminate abstract frame index references...
 912   if (getOptLevel() != CodeGenOpt::None) {
 913     addPass(&PostRAMachineSinkingID);
 914     addPass(&ShrinkWrapID);
 915   }
 916
 917   // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
 918   // do so if it hasn't been disabled, substituted, or overridden.
 919   if (!isPassSubstitutedOrOverridden(&PrologEpilogCodeInserterID))
 920       addPass(createPrologEpilogInserterPass());
 921
 922   /// Add passes that optimize machine instructions after register allocation.
 923   if (getOptLevel() != CodeGenOpt::None)
 924     addMachineLateOptimization();
 925
 926   // Expand pseudo instructions before second scheduling pass.
 927   addPass(&ExpandPostRAPseudosID);
 928
 929   // Run pre-sched2 passes.
 930   addPreSched2();
 931
 932   if (EnableImplicitNullChecks)
 933     addPass(&ImplicitNullChecksID);
 934
 935   // Second pass scheduler.
 936   // Let Target optionally insert this pass by itself at some other
 937   // point.
 938   if (getOptLevel() != CodeGenOpt::None &&
 939       !TM->targetSchedulesPostRAScheduling()) {
 940     if (MISchedPostRA)
 941       addPass(&PostMachineSchedulerID);
 942     else
 943       addPass(&PostRASchedulerID);
 944   }
 945
 946   // GC
 947   if (addGCPasses()) {
 948     if (PrintGCInfo)
 949       addPass(createGCInfoPrinter(dbgs()), false, false);
 950   }
 951
 952   // Basic block placement.
 953   if (getOptLevel() != CodeGenOpt::None)
 954     addBlockPlacement();
 955
 956   addPreEmitPass();
 957
 958   if (TM->Options.EnableIPRA)
 959     // Collect register usage information and produce a register mask of
 960     // clobbered registers, to be used to optimize call sites.
 961     addPass(createRegUsageInfoCollector());
 962
 963   addPass(&FuncletLayoutID, false);
 964
 965   addPass(&StackMapLivenessID, false);
 966   addPass(&LiveDebugValuesID, false);
 967
 968   // Insert before XRay Instrumentation.
 969   addPass(&FEntryInserterID, false);
 970
 971   addPass(&XRayInstrumentationID, false);
 972   addPass(&PatchableFunctionID, false);
 973
 974   if (TM->Options.EnableMachineOutliner && getOptLevel() != CodeGenOpt::None &&
 975       EnableMachineOutliner != NeverOutline) {
 976     bool RunOnAllFunctions = (EnableMachineOutliner == AlwaysOutline);
 977     bool AddOutliner = RunOnAllFunctions ||
 978                        TM->Options.SupportsDefaultOutlining;
 979     if (AddOutliner)
 980       addPass(createMachineOutlinerPass(RunOnAllFunctions));
 981   }
 982
 983   // Add passes that directly emit MI after all other MI passes.
 984   addPreEmitPass2();
 985
 986   AddingMachinePasses = false;
 987 }
 988
 989 /// Add passes that optimize machine instructions in SSA form.
 990 void TargetPassConfig::addMachineSSAOptimization() {
 991   // Pre-ra tail duplication.
 992   addPass(&EarlyTailDuplicateID);
 993
 994   // Optimize PHIs before DCE: removing dead PHI cycles may make more
 995   // instructions dead.
 996   addPass(&OptimizePHIsID, false);
 997
 998   // This pass merges large allocas. StackSlotColoring is a different pass
 999   // which merges spill slots.
1000   addPass(&StackColoringID, false);
1001
1002   // If the target requests it, assign local variables to stack slots relative
1003   // to one another and simplify frame index references where possible.
1004   addPass(&LocalStackSlotAllocationID, false);
1005
1006   // With optimization, dead code should already be eliminated. However
1007   // there is one known exception: lowered code for arguments that are only
1008   // used by tail calls, where the tail calls reuse the incoming stack
1009   // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
1010   addPass(&DeadMachineInstructionElimID);
1011
1012   // Allow targets to insert passes that improve instruction level parallelism,
1013   // like if-conversion. Such passes will typically need dominator trees and
1014   // loop info, just like LICM and CSE below.
1015   addILPOpts();
1016
1017   addPass(&EarlyMachineLICMID, false);
1018   addPass(&MachineCSEID, false);
1019
1020   addPass(&MachineSinkingID);
1021
1022   addPass(&PeepholeOptimizerID);
1023   // Clean-up the dead code that may have been generated by peephole
1024   // rewriting.
1025   addPass(&DeadMachineInstructionElimID);
1026 }
1027
1028 //===---------------------------------------------------------------------===//
1029 /// Register Allocation Pass Configuration
1030 //===---------------------------------------------------------------------===//
1031
1032 bool TargetPassConfig::getOptimizeRegAlloc() const {
1033   switch (OptimizeRegAlloc) {
1034   case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
1035   case cl::BOU_TRUE:  return true;
1036   case cl::BOU_FALSE: return false;
1037   }
1038   llvm_unreachable("Invalid optimize-regalloc state");
1039 }
1040
1041 /// RegisterRegAlloc's global Registry tracks allocator registration.
1042 MachinePassRegistry<RegisterRegAlloc::FunctionPassCtor>
1043     RegisterRegAlloc::Registry;
1044
1045 /// A dummy default pass factory indicates whether the register allocator is
1046 /// overridden on the command line.
1047 static llvm::once_flag InitializeDefaultRegisterAllocatorFlag;
1048
1049 static RegisterRegAlloc
1050 defaultRegAlloc("default",
1051                 "pick register allocator based on -O option",
1052                 useDefaultRegisterAllocator);
1053
1054 static void initializeDefaultRegisterAllocatorOnce() {
1055   RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
1056
1057   if (!Ctor) {
1058     Ctor = RegAlloc;
1059     RegisterRegAlloc::setDefault(RegAlloc);
1060   }
1061 }
1062
1063 /// Instantiate the default register allocator pass for this target for either
1064 /// the optimized or unoptimized allocation path. This will be added to the pass
1065 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
1066 /// in the optimized case.
1067 ///
1068 /// A target that uses the standard regalloc pass order for fast or optimized
1069 /// allocation may still override this for per-target regalloc
1070 /// selection. But -regalloc=... always takes precedence.
1071 FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
1072   if (Optimized)
1073     return createGreedyRegisterAllocator();
1074   else
1075     return createFastRegisterAllocator();
1076 }
1077
1078 /// Find and instantiate the register allocation pass requested by this target
1079 /// at the current optimization level.  Different register allocators are
1080 /// defined as separate passes because they may require different analysis.
1081 ///
1082 /// This helper ensures that the regalloc= option is always available,
1083 /// even for targets that override the default allocator.
1084 ///
1085 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
1086 /// this can be folded into addPass.
1087 FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
1088   // Initialize the global default.
1089   llvm::call_once(InitializeDefaultRegisterAllocatorFlag,
1090                   initializeDefaultRegisterAllocatorOnce);
1091
1092   RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
1093   if (Ctor != useDefaultRegisterAllocator)
1094     return Ctor();
1095
1096   // With no -regalloc= override, ask the target for a regalloc pass.
1097   return createTargetRegisterAllocator(Optimized);
1098 }
1099
1100 /// Return true if the default global register allocator is in use and
1101 /// has not be overriden on the command line with '-regalloc=...'
1102 bool TargetPassConfig::usingDefaultRegAlloc() const {
1103   return RegAlloc.getNumOccurrences() == 0;
1104 }
1105
1106 /// Add the minimum set of target-independent passes that are required for
1107 /// register allocation. No coalescing or scheduling.
1108 void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
1109   addPass(&PHIEliminationID, false);
1110   addPass(&TwoAddressInstructionPassID, false);
1111
1112   if (RegAllocPass)
1113     addPass(RegAllocPass);
1114 }
1115
1116 /// Add standard target-independent passes that are tightly coupled with
1117 /// optimized register allocation, including coalescing, machine instruction
1118 /// scheduling, and register allocation itself.
1119 void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
1120   addPass(&DetectDeadLanesID, false);
1121
1122   addPass(&ProcessImplicitDefsID, false);
1123
1124   // LiveVariables currently requires pure SSA form.
1125   //
1126   // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
1127   // LiveVariables can be removed completely, and LiveIntervals can be directly
1128   // computed. (We still either need to regenerate kill flags after regalloc, or
1129   // preferably fix the scavenger to not depend on them).
1130   addPass(&LiveVariablesID, false);
1131
1132   // Edge splitting is smarter with machine loop info.
1133   addPass(&MachineLoopInfoID, false);
1134   addPass(&PHIEliminationID, false);
1135
1136   // Eventually, we want to run LiveIntervals before PHI elimination.
1137   if (EarlyLiveIntervals)
1138     addPass(&LiveIntervalsID, false);
1139
1140   addPass(&TwoAddressInstructionPassID, false);
1141   addPass(&RegisterCoalescerID);
1142
1143   // The machine scheduler may accidentally create disconnected components
1144   // when moving subregister definitions around, avoid this by splitting them to
1145   // separate vregs before. Splitting can also improve reg. allocation quality.
1146   addPass(&RenameIndependentSubregsID);
1147
1148   // PreRA instruction scheduling.
1149   addPass(&MachineSchedulerID);
1150
1151   if (RegAllocPass) {
1152     // Add the selected register allocation pass.
1153     addPass(RegAllocPass);
1154
1155     // Allow targets to change the register assignments before rewriting.
1156     addPreRewrite();
1157
1158     // Finally rewrite virtual registers.
1159     addPass(&VirtRegRewriterID);
1160
1161     // Perform stack slot coloring and post-ra machine LICM.
1162     //
1163     // FIXME: Re-enable coloring with register when it's capable of adding
1164     // kill markers.
1165     addPass(&StackSlotColoringID);
1166
1167     // Copy propagate to forward register uses and try to eliminate COPYs that
1168     // were not coalesced.
1169     addPass(&MachineCopyPropagationID);
1170
1171     // Run post-ra machine LICM to hoist reloads / remats.
1172     //
1173     // FIXME: can this move into MachineLateOptimization?
1174     addPass(&MachineLICMID);
1175   }
1176 }
1177
1178 //===---------------------------------------------------------------------===//
1179 /// Post RegAlloc Pass Configuration
1180 //===---------------------------------------------------------------------===//
1181
1182 /// Add passes that optimize machine instructions after register allocation.
1183 void TargetPassConfig::addMachineLateOptimization() {
1184   // Branch folding must be run after regalloc and prolog/epilog insertion.
1185   addPass(&BranchFolderPassID);
1186
1187   // Tail duplication.
1188   // Note that duplicating tail just increases code size and degrades
1189   // performance for targets that require Structured Control Flow.
1190   // In addition it can also make CFG irreducible. Thus we disable it.
1191   if (!TM->requiresStructuredCFG())
1192     addPass(&TailDuplicateID);
1193
1194   // Copy propagation.
1195   addPass(&MachineCopyPropagationID);
1196 }
1197
1198 /// Add standard GC passes.
1199 bool TargetPassConfig::addGCPasses() {
1200   addPass(&GCMachineCodeAnalysisID, false);
1201   return true;
1202 }
1203
1204 /// Add standard basic block placement passes.
1205 void TargetPassConfig::addBlockPlacement() {
1206   if (addPass(&MachineBlockPlacementID)) {
1207     // Run a separate pass to collect block placement statistics.
1208     if (EnableBlockPlacementStats)
1209       addPass(&MachineBlockPlacementStatsID);
1210   }
1211 }
1212
1213 //===---------------------------------------------------------------------===//
1214 /// GlobalISel Configuration
1215 //===---------------------------------------------------------------------===//
1216 bool TargetPassConfig::isGlobalISelAbortEnabled() const {
1217   return TM->Options.GlobalISelAbort == GlobalISelAbortMode::Enable;
1218 }
1219
1220 bool TargetPassConfig::reportDiagnosticWhenGlobalISelFallback() const {
1221   return TM->Options.GlobalISelAbort == GlobalISelAbortMode::DisableWithDiag;
1222 }
1223
1224 bool TargetPassConfig::isGISelCSEEnabled() const {
1225   return getOptLevel() != CodeGenOpt::Level::None;
1226 }