lib/MCA/Context.cpp

   1 //===---------------------------- Context.cpp -------------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 /// \file
   9 ///
  10 /// This file defines a class for holding ownership of various simulated
  11 /// hardware units.  A Context also provides a utility routine for constructing
  12 /// a default out-of-order pipeline with fetch, dispatch, execute, and retire
  13 /// stages.
  14 ///
  15 //===----------------------------------------------------------------------===//
  16
  17 #include "llvm/MCA/Context.h"
  18 #include "llvm/MCA/HardwareUnits/RegisterFile.h"
  19 #include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
  20 #include "llvm/MCA/HardwareUnits/Scheduler.h"
  21 #include "llvm/MCA/Stages/DispatchStage.h"
  22 #include "llvm/MCA/Stages/EntryStage.h"
  23 #include "llvm/MCA/Stages/ExecuteStage.h"
  24 #include "llvm/MCA/Stages/RetireStage.h"
  25
  26 namespace llvm {
  27 namespace mca {
  28
  29 std::unique_ptr<Pipeline>
  30 Context::createDefaultPipeline(const PipelineOptions &Opts, InstrBuilder &IB,
  31                                SourceMgr &SrcMgr) {
  32   const MCSchedModel &SM = STI.getSchedModel();
  33
  34   // Create the hardware units defining the backend.
  35   auto RCU = llvm::make_unique<RetireControlUnit>(SM);
  36   auto PRF = llvm::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
  37   auto LSU = llvm::make_unique<LSUnit>(SM, Opts.LoadQueueSize,
  38                                        Opts.StoreQueueSize, Opts.AssumeNoAlias);
  39   auto HWS = llvm::make_unique<Scheduler>(SM, *LSU);
  40
  41   // Create the pipeline stages.
  42   auto Fetch = llvm::make_unique<EntryStage>(SrcMgr);
  43   auto Dispatch = llvm::make_unique<DispatchStage>(STI, MRI, Opts.DispatchWidth,
  44                                                    *RCU, *PRF);
  45   auto Execute = llvm::make_unique<ExecuteStage>(*HWS);
  46   auto Retire = llvm::make_unique<RetireStage>(*RCU, *PRF);
  47
  48   // Pass the ownership of all the hardware units to this Context.
  49   addHardwareUnit(std::move(RCU));
  50   addHardwareUnit(std::move(PRF));
  51   addHardwareUnit(std::move(LSU));
  52   addHardwareUnit(std::move(HWS));
  53
  54   // Build the pipeline.
  55   auto StagePipeline = llvm::make_unique<Pipeline>();
  56   StagePipeline->appendStage(std::move(Fetch));
  57   StagePipeline->appendStage(std::move(Dispatch));
  58   StagePipeline->appendStage(std::move(Execute));
  59   StagePipeline->appendStage(std::move(Retire));
  60   return StagePipeline;
  61 }
  62
  63 } // namespace mca
  64 } // namespace llvm