lib/Target/AArch64/AArch64.td

   1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 //
  10 //===----------------------------------------------------------------------===//
  11
  12 //===----------------------------------------------------------------------===//
  13 // Target-independent interfaces which we are implementing.
  14 //===----------------------------------------------------------------------===//
  15
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // AArch64 Subtarget features.
  20 //
  21
  22 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
  23                                        "Enable ARMv8 FP">;
  24
  25 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  26   "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
  27
  28 def FeatureSM4 : SubtargetFeature<
  29     "sm4", "HasSM4", "true",
  30     "Enable SM3 and SM4 support", [FeatureNEON]>;
  31
  32 def FeatureSHA2 : SubtargetFeature<
  33     "sha2", "HasSHA2", "true",
  34     "Enable SHA1 and SHA256 support", [FeatureNEON]>;
  35
  36 def FeatureSHA3 : SubtargetFeature<
  37     "sha3", "HasSHA3", "true",
  38     "Enable SHA512 and SHA3 support", [FeatureNEON, FeatureSHA2]>;
  39
  40 def FeatureAES : SubtargetFeature<
  41     "aes", "HasAES", "true",
  42     "Enable AES support", [FeatureNEON]>;
  43
  44 // Crypto has been split up and any combination is now valid (see the
  45 // crypto defintions above). Also, crypto is now context sensitive:
  46 // it has a different meaning for e.g. Armv8.4 than it has for Armv8.2.
  47 // Therefore, we rely on Clang, the user interacing tool, to pass on the
  48 // appropriate crypto options. But here in the backend, crypto has very little
  49 // meaning anymore. We kept the Crypto defintion here for backward
  50 // compatibility, and now imply features SHA2 and AES, which was the
  51 // "traditional" meaning of Crypto.
  52 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
  53   "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>;
  54
  55 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
  56   "Enable ARMv8 CRC-32 checksum instructions">;
  57
  58 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
  59   "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
  60
  61 def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
  62   "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">;
  63
  64 def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true",
  65   "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">;
  66
  67 def FeaturePAN : SubtargetFeature<
  68     "pan", "HasPAN", "true",
  69     "Enables ARM v8.1 Privileged Access-Never extension">;
  70
  71 def FeatureLOR : SubtargetFeature<
  72     "lor", "HasLOR", "true",
  73     "Enables ARM v8.1 Limited Ordering Regions extension">;
  74
  75 def FeatureVH : SubtargetFeature<
  76     "vh", "HasVH", "true",
  77     "Enables ARM v8.1 Virtual Host extension">;
  78
  79 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
  80   "Enable ARMv8 PMUv3 Performance Monitors extension">;
  81
  82 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
  83   "Full FP16", [FeatureFPARMv8]>;
  84
  85 def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true",
  86   "Enable FP16 FML instructions", [FeatureFullFP16]>;
  87
  88 def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
  89   "Enable Statistical Profiling extension">;
  90
  91 def FeaturePAN_RWV : SubtargetFeature<
  92     "pan-rwv", "HasPAN_RWV", "true",
  93     "Enable v8.2 PAN s1e1R and s1e1W Variants",
  94     [FeaturePAN]>;
  95
  96 // UAO PState
  97 def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true",
  98     "Enable v8.2 UAO PState">;
  99
 100 def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP",
 101     "true", "Enable v8.2 data Cache Clean to Point of Persistence" >;
 102
 103 def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true",
 104   "Enable Scalable Vector Extension (SVE) instructions">;
 105
 106 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
 107                                         "Has zero-cycle register moves">;
 108 def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true",
 109                                         "Has zero-cycle zeroing instructions for generic registers">;
 110
 111 def FeatureZCZeroingFP : SubtargetFeature<"zcz-fp", "HasZeroCycleZeroingFP", "true",
 112                                         "Has zero-cycle zeroing instructions for FP registers">;
 113
 114 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
 115                                         "Has zero-cycle zeroing instructions",
 116                                         [FeatureZCZeroingGP, FeatureZCZeroingFP]>;
 117
 118 /// ... but the floating-point version doesn't quite work in rare cases on older
 119 /// CPUs.
 120 def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround",
 121     "HasZeroCycleZeroingFPWorkaround", "true",
 122     "The zero-cycle floating-point zeroing instruction has a bug">;
 123
 124 def FeatureStrictAlign : SubtargetFeature<"strict-align",
 125                                           "StrictAlign", "true",
 126                                           "Disallow all unaligned memory "
 127                                           "access">;
 128
 129 foreach i = {1-7,9-15,18,20-28} in
 130     def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true",
 131                                              "Reserve X"#i#", making it unavailable "
 132                                              "as a GPR">;
 133
 134 foreach i = {8-15,18} in
 135     def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i,
 136          "CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">;
 137
 138 def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
 139                                     "Use alias analysis during codegen">;
 140
 141 def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
 142     "true",
 143     "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
 144
 145 def FeaturePredictableSelectIsExpensive : SubtargetFeature<
 146     "predictable-select-expensive", "PredictableSelectIsExpensive", "true",
 147     "Prefer likely predicted branches over selects">;
 148
 149 def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move",
 150     "CustomAsCheapAsMove", "true",
 151     "Use custom handling of cheap instructions">;
 152
 153 def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move",
 154     "ExynosAsCheapAsMove", "true",
 155     "Use Exynos specific handling of cheap instructions",
 156     [FeatureCustomCheapAsMoveHandling]>;
 157
 158 def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
 159     "UsePostRAScheduler", "true", "Schedule again after register allocation">;
 160
 161 def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
 162     "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">;
 163
 164 def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",
 165     "Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">;
 166
 167 def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "STRQroIsSlow",
 168     "true", "STR of Q register with register offset is slow">;
 169
 170 def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
 171     "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
 172     "true", "Use alternative pattern for sextload convert to f32">;
 173
 174 def FeatureArithmeticBccFusion : SubtargetFeature<
 175     "arith-bcc-fusion", "HasArithmeticBccFusion", "true",
 176     "CPU fuses arithmetic+bcc operations">;
 177
 178 def FeatureArithmeticCbzFusion : SubtargetFeature<
 179     "arith-cbz-fusion", "HasArithmeticCbzFusion", "true",
 180     "CPU fuses arithmetic + cbz/cbnz operations">;
 181
 182 def FeatureFuseAddress : SubtargetFeature<
 183     "fuse-address", "HasFuseAddress", "true",
 184     "CPU fuses address generation and memory operations">;
 185
 186 def FeatureFuseAES : SubtargetFeature<
 187     "fuse-aes", "HasFuseAES", "true",
 188     "CPU fuses AES crypto operations">;
 189
 190 def FeatureFuseArithmeticLogic : SubtargetFeature<
 191     "fuse-arith-logic", "HasFuseArithmeticLogic", "true",
 192     "CPU fuses arithmetic and logic operations">;
 193
 194 def FeatureFuseCCSelect : SubtargetFeature<
 195     "fuse-csel", "HasFuseCCSelect", "true",
 196     "CPU fuses conditional select operations">;
 197
 198 def FeatureFuseCryptoEOR : SubtargetFeature<
 199     "fuse-crypto-eor", "HasFuseCryptoEOR", "true",
 200     "CPU fuses AES/PMULL and EOR operations">;
 201
 202 def FeatureFuseLiterals : SubtargetFeature<
 203     "fuse-literals", "HasFuseLiterals", "true",
 204     "CPU fuses literal generation operations">;
 205
 206 def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
 207     "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
 208     "Disable latency scheduling heuristic">;
 209
 210 def FeatureForce32BitJumpTables
 211    : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true",
 212                       "Force jump table entries to be 32-bits wide except at MinSize">;
 213
 214 def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true",
 215                                    "Enable support for RCPC extension">;
 216
 217 def FeatureUseRSqrt : SubtargetFeature<
 218     "use-reciprocal-square-root", "UseRSqrt", "true",
 219     "Use the reciprocal square root approximation">;
 220
 221 def FeatureDotProd : SubtargetFeature<
 222     "dotprod", "HasDotProd", "true",
 223     "Enable dot product support">;
 224
 225 def FeaturePA : SubtargetFeature<
 226     "pa", "HasPA", "true",
 227     "Enable v8.3-A Pointer Authentication enchancement">;
 228
 229 def FeatureJS : SubtargetFeature<
 230     "jsconv", "HasJS", "true",
 231     "Enable v8.3-A JavaScript FP conversion enchancement",
 232     [FeatureFPARMv8]>;
 233
 234 def FeatureCCIDX : SubtargetFeature<
 235     "ccidx", "HasCCIDX", "true",
 236     "Enable v8.3-A Extend of the CCSIDR number of sets">;
 237
 238 def FeatureComplxNum : SubtargetFeature<
 239     "complxnum", "HasComplxNum", "true",
 240     "Enable v8.3-A Floating-point complex number support",
 241     [FeatureNEON]>;
 242
 243 def FeatureNV : SubtargetFeature<
 244     "nv", "HasNV", "true",
 245     "Enable v8.4-A Nested Virtualization Enchancement">;
 246
 247 def FeatureRASv8_4 : SubtargetFeature<
 248     "rasv8_4", "HasRASv8_4", "true",
 249     "Enable v8.4-A Reliability, Availability and Serviceability extension",
 250     [FeatureRAS]>;
 251
 252 def FeatureMPAM : SubtargetFeature<
 253     "mpam", "HasMPAM", "true",
 254     "Enable v8.4-A Memory system Partitioning and Monitoring extension">;
 255
 256 def FeatureDIT : SubtargetFeature<
 257     "dit", "HasDIT", "true",
 258     "Enable v8.4-A Data Independent Timing instructions">;
 259
 260 def FeatureTRACEV8_4 : SubtargetFeature<
 261     "tracev8.4", "HasTRACEV8_4", "true",
 262     "Enable v8.4-A Trace extension">;
 263
 264 def FeatureAM : SubtargetFeature<
 265     "am", "HasAM", "true",
 266     "Enable v8.4-A Activity Monitors extension">;
 267
 268 def FeatureSEL2 : SubtargetFeature<
 269     "sel2", "HasSEL2", "true",
 270     "Enable v8.4-A Secure Exception Level 2 extension">;
 271
 272 def FeatureTLB_RMI : SubtargetFeature<
 273     "tlb-rmi", "HasTLB_RMI", "true",
 274     "Enable v8.4-A TLB Range and Maintenance Instructions">;
 275
 276 def FeatureFMI : SubtargetFeature<
 277     "fmi", "HasFMI", "true",
 278     "Enable v8.4-A Flag Manipulation Instructions">;
 279
 280 // 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset
 281 def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true",
 282     "Enable v8.4-A RCPC instructions with Immediate Offsets",
 283     [FeatureRCPC]>;
 284
 285 def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
 286                                         "NegativeImmediates", "false",
 287                                         "Convert immediates and instructions "
 288                                         "to their negated or complemented "
 289                                         "equivalent when the immediate does "
 290                                         "not fit in the encoding.">;
 291
 292 def FeatureLSLFast : SubtargetFeature<
 293     "lsl-fast", "HasLSLFast", "true",
 294     "CPU has a fastpath logical shift of up to 3 places">;
 295
 296 def FeatureAggressiveFMA :
 297   SubtargetFeature<"aggressive-fma",
 298                    "HasAggressiveFMA",
 299                    "true",
 300                    "Enable Aggressive FMA for floating-point.">;
 301
 302 def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true",
 303   "Enable alternative NZCV format for floating point comparisons">;
 304
 305 def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true",
 306   "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to "
 307   "an integer (in FP format) forcing it to fit into a 32- or 64-bit int" >;
 308
 309 def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict",
 310   "true", "Enable architectural speculation restriction" >;
 311
 312 def FeatureSB : SubtargetFeature<"sb", "HasSB",
 313   "true", "Enable v8.5 Speculation Barrier" >;
 314
 315 def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS",
 316   "true", "Enable Speculative Store Bypass Safe bit" >;
 317
 318 def FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true",
 319   "Enable v8.5a execution and data prediction invalidation instructions" >;
 320
 321 def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP",
 322     "true", "Enable v8.5 Cache Clean to Point of Deep Persistence" >;
 323
 324 def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI",
 325     "true", "Enable Branch Target Identification" >;
 326
 327 def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen",
 328     "true", "Enable Random Number generation instructions" >;
 329
 330 def FeatureMTE : SubtargetFeature<"mte", "HasMTE",
 331     "true", "Enable Memory Tagging Extension" >;
 332
 333 //===----------------------------------------------------------------------===//
 334 // Architectures.
 335 //
 336
 337 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
 338   "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM,
 339   FeaturePAN, FeatureLOR, FeatureVH]>;
 340
 341 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
 342   "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO,
 343   FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>;
 344
 345 def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
 346   "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePA,
 347   FeatureJS, FeatureCCIDX, FeatureComplxNum]>;
 348
 349 def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
 350   "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd,
 351   FeatureNV, FeatureRASv8_4, FeatureMPAM, FeatureDIT,
 352   FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI,
 353   FeatureFMI, FeatureRCPC_IMMO]>;
 354
 355 def HasV8_5aOps : SubtargetFeature<
 356   "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
 357   [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
 358    FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist,
 359    FeatureBranchTargetId]
 360 >;
 361
 362 //===----------------------------------------------------------------------===//
 363 // Register File Description
 364 //===----------------------------------------------------------------------===//
 365
 366 include "AArch64RegisterInfo.td"
 367 include "AArch64RegisterBanks.td"
 368 include "AArch64CallingConvention.td"
 369
 370 //===----------------------------------------------------------------------===//
 371 // Instruction Descriptions
 372 //===----------------------------------------------------------------------===//
 373
 374 include "AArch64Schedule.td"
 375 include "AArch64InstrInfo.td"
 376 include "AArch64SchedPredicates.td"
 377 include "AArch64SchedPredExynos.td"
 378
 379 def AArch64InstrInfo : InstrInfo;
 380
 381 //===----------------------------------------------------------------------===//
 382 // Named operands for MRS/MSR/TLBI/...
 383 //===----------------------------------------------------------------------===//
 384
 385 include "AArch64SystemOperands.td"
 386
 387 //===----------------------------------------------------------------------===//
 388 // AArch64 Processors supported.
 389 //
 390 include "AArch64SchedA53.td"
 391 include "AArch64SchedA57.td"
 392 include "AArch64SchedCyclone.td"
 393 include "AArch64SchedFalkor.td"
 394 include "AArch64SchedKryo.td"
 395 include "AArch64SchedExynosM1.td"
 396 include "AArch64SchedExynosM3.td"
 397 include "AArch64SchedExynosM4.td"
 398 include "AArch64SchedThunderX.td"
 399 include "AArch64SchedThunderX2T99.td"
 400
 401 def ProcA35     : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
 402                                    "Cortex-A35 ARM processors", [
 403                                    FeatureCRC,
 404                                    FeatureCrypto,
 405                                    FeatureFPARMv8,
 406                                    FeatureNEON,
 407                                    FeaturePerfMon
 408                                    ]>;
 409
 410 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
 411                                    "Cortex-A53 ARM processors", [
 412                                    FeatureBalanceFPOps,
 413                                    FeatureCRC,
 414                                    FeatureCrypto,
 415                                    FeatureCustomCheapAsMoveHandling,
 416                                    FeatureFPARMv8,
 417                                    FeatureFuseAES,
 418                                    FeatureNEON,
 419                                    FeaturePerfMon,
 420                                    FeaturePostRAScheduler,
 421                                    FeatureUseAA
 422                                    ]>;
 423
 424 def ProcA55     : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
 425                                    "Cortex-A55 ARM processors", [
 426                                    HasV8_2aOps,
 427                                    FeatureCrypto,
 428                                    FeatureFPARMv8,
 429                                    FeatureFuseAES,
 430                                    FeatureNEON,
 431                                    FeatureFullFP16,
 432                                    FeatureDotProd,
 433                                    FeatureRCPC,
 434                                    FeaturePerfMon
 435                                    ]>;
 436
 437 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
 438                                    "Cortex-A57 ARM processors", [
 439                                    FeatureBalanceFPOps,
 440                                    FeatureCRC,
 441                                    FeatureCrypto,
 442                                    FeatureCustomCheapAsMoveHandling,
 443                                    FeatureFPARMv8,
 444                                    FeatureFuseAES,
 445                                    FeatureFuseLiterals,
 446                                    FeatureNEON,
 447                                    FeaturePerfMon,
 448                                    FeaturePostRAScheduler,
 449                                    FeaturePredictableSelectIsExpensive
 450                                    ]>;
 451
 452 def ProcA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
 453                                    "Cortex-A72 ARM processors", [
 454                                    FeatureCRC,
 455                                    FeatureCrypto,
 456                                    FeatureFPARMv8,
 457                                    FeatureFuseAES,
 458                                    FeatureNEON,
 459                                    FeaturePerfMon
 460                                    ]>;
 461
 462 def ProcA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
 463                                    "Cortex-A73 ARM processors", [
 464                                    FeatureCRC,
 465                                    FeatureCrypto,
 466                                    FeatureFPARMv8,
 467                                    FeatureFuseAES,
 468                                    FeatureNEON,
 469                                    FeaturePerfMon
 470                                    ]>;
 471
 472 def ProcA75     : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
 473                                    "Cortex-A75 ARM processors", [
 474                                    HasV8_2aOps,
 475                                    FeatureCrypto,
 476                                    FeatureFPARMv8,
 477                                    FeatureFuseAES,
 478                                    FeatureNEON,
 479                                    FeatureFullFP16,
 480                                    FeatureDotProd,
 481                                    FeatureRCPC,
 482                                    FeaturePerfMon
 483                                    ]>;
 484
 485 // Note that cyclone does not fuse AES instructions, but newer apple chips do
 486 // perform the fusion and cyclone is used by default when targetting apple OSes.
 487 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
 488                                    "Cyclone", [
 489                                    FeatureAlternateSExtLoadCVTF32Pattern,
 490                                    FeatureArithmeticBccFusion,
 491                                    FeatureArithmeticCbzFusion,
 492                                    FeatureCrypto,
 493                                    FeatureDisableLatencySchedHeuristic,
 494                                    FeatureFPARMv8,
 495                                    FeatureFuseAES,
 496                                    FeatureFuseCryptoEOR,
 497                                    FeatureNEON,
 498                                    FeaturePerfMon,
 499                                    FeatureZCRegMove,
 500                                    FeatureZCZeroing,
 501                                    FeatureZCZeroingFPWorkaround
 502                                    ]>;
 503
 504 def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
 505                                     "Samsung Exynos-M1 processors",
 506                                     [FeatureSlowPaired128,
 507                                      FeatureCRC,
 508                                      FeatureCrypto,
 509                                      FeatureExynosCheapAsMoveHandling,
 510                                      FeatureForce32BitJumpTables,
 511                                      FeatureFuseAES,
 512                                      FeaturePerfMon,
 513                                      FeaturePostRAScheduler,
 514                                      FeatureSlowMisaligned128Store,
 515                                      FeatureUseRSqrt,
 516                                      FeatureZCZeroingFP]>;
 517
 518 def ProcExynosM2 : SubtargetFeature<"exynosm2", "ARMProcFamily", "ExynosM1",
 519                                     "Samsung Exynos-M2 processors",
 520                                     [FeatureSlowPaired128,
 521                                      FeatureCRC,
 522                                      FeatureCrypto,
 523                                      FeatureExynosCheapAsMoveHandling,
 524                                      FeatureForce32BitJumpTables,
 525                                      FeatureFuseAES,
 526                                      FeaturePerfMon,
 527                                      FeaturePostRAScheduler,
 528                                      FeatureSlowMisaligned128Store,
 529                                      FeatureZCZeroingFP]>;
 530
 531 def ProcExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3",
 532                                     "Samsung Exynos-M3 processors",
 533                                     [FeatureCRC,
 534                                      FeatureCrypto,
 535                                      FeatureExynosCheapAsMoveHandling,
 536                                      FeatureForce32BitJumpTables,
 537                                      FeatureFuseAddress,
 538                                      FeatureFuseAES,
 539                                      FeatureFuseCCSelect,
 540                                      FeatureFuseLiterals,
 541                                      FeatureLSLFast,
 542                                      FeaturePerfMon,
 543                                      FeaturePostRAScheduler,
 544                                      FeaturePredictableSelectIsExpensive,
 545                                      FeatureZCZeroingFP]>;
 546
 547 def ProcExynosM4 : SubtargetFeature<"exynosm4", "ARMProcFamily", "ExynosM3",
 548                                     "Samsung Exynos-M4 processors",
 549                                     [HasV8_2aOps,
 550                                      FeatureArithmeticBccFusion,
 551                                      FeatureArithmeticCbzFusion,
 552                                      FeatureCrypto,
 553                                      FeatureDotProd,
 554                                      FeatureExynosCheapAsMoveHandling,
 555                                      FeatureForce32BitJumpTables,
 556                                      FeatureFP16FML,
 557                                      FeatureFuseAddress,
 558                                      FeatureFuseAES,
 559                                      FeatureFuseArithmeticLogic,
 560                                      FeatureFuseCCSelect,
 561                                      FeatureFuseLiterals,
 562                                      FeatureLSLFast,
 563                                      FeaturePerfMon,
 564                                      FeaturePostRAScheduler,
 565                                      FeatureZCZeroing]>;
 566
 567 def ProcKryo    : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
 568                                    "Qualcomm Kryo processors", [
 569                                    FeatureCRC,
 570                                    FeatureCrypto,
 571                                    FeatureCustomCheapAsMoveHandling,
 572                                    FeatureFPARMv8,
 573                                    FeatureNEON,
 574                                    FeaturePerfMon,
 575                                    FeaturePostRAScheduler,
 576                                    FeaturePredictableSelectIsExpensive,
 577                                    FeatureZCZeroing,
 578                                    FeatureLSLFast
 579                                    ]>;
 580
 581 def ProcFalkor  : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
 582                                    "Qualcomm Falkor processors", [
 583                                    FeatureCRC,
 584                                    FeatureCrypto,
 585                                    FeatureCustomCheapAsMoveHandling,
 586                                    FeatureFPARMv8,
 587                                    FeatureNEON,
 588                                    FeaturePerfMon,
 589                                    FeaturePostRAScheduler,
 590                                    FeaturePredictableSelectIsExpensive,
 591                                    FeatureRDM,
 592                                    FeatureZCZeroing,
 593                                    FeatureLSLFast,
 594                                    FeatureSlowSTRQro
 595                                    ]>;
 596
 597 def ProcSaphira  : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira",
 598                                    "Qualcomm Saphira processors", [
 599                                    FeatureCrypto,
 600                                    FeatureCustomCheapAsMoveHandling,
 601                                    FeatureFPARMv8,
 602                                    FeatureNEON,
 603                                    FeatureSPE,
 604                                    FeaturePerfMon,
 605                                    FeaturePostRAScheduler,
 606                                    FeaturePredictableSelectIsExpensive,
 607                                    FeatureZCZeroing,
 608                                    FeatureLSLFast,
 609                                    HasV8_4aOps]>;
 610
 611 def ProcThunderX2T99  : SubtargetFeature<"thunderx2t99", "ARMProcFamily",
 612                                          "ThunderX2T99",
 613                                          "Cavium ThunderX2 processors", [
 614                                           FeatureAggressiveFMA,
 615                                           FeatureCRC,
 616                                           FeatureCrypto,
 617                                           FeatureFPARMv8,
 618                                           FeatureArithmeticBccFusion,
 619                                           FeatureNEON,
 620                                           FeaturePostRAScheduler,
 621                                           FeaturePredictableSelectIsExpensive,
 622                                           FeatureLSE,
 623                                           HasV8_1aOps]>;
 624
 625 def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX",
 626                                     "Cavium ThunderX processors", [
 627                                     FeatureCRC,
 628                                     FeatureCrypto,
 629                                     FeatureFPARMv8,
 630                                     FeaturePerfMon,
 631                                     FeaturePostRAScheduler,
 632                                     FeaturePredictableSelectIsExpensive,
 633                                     FeatureNEON]>;
 634
 635 def ProcThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily",
 636                                        "ThunderXT88",
 637                                        "Cavium ThunderX processors", [
 638                                        FeatureCRC,
 639                                        FeatureCrypto,
 640                                        FeatureFPARMv8,
 641                                        FeaturePerfMon,
 642                                        FeaturePostRAScheduler,
 643                                        FeaturePredictableSelectIsExpensive,
 644                                        FeatureNEON]>;
 645
 646 def ProcThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily",
 647                                        "ThunderXT81",
 648                                        "Cavium ThunderX processors", [
 649                                        FeatureCRC,
 650                                        FeatureCrypto,
 651                                        FeatureFPARMv8,
 652                                        FeaturePerfMon,
 653                                        FeaturePostRAScheduler,
 654                                        FeaturePredictableSelectIsExpensive,
 655                                        FeatureNEON]>;
 656
 657 def ProcThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily",
 658                                        "ThunderXT83",
 659                                        "Cavium ThunderX processors", [
 660                                        FeatureCRC,
 661                                        FeatureCrypto,
 662                                        FeatureFPARMv8,
 663                                        FeaturePerfMon,
 664                                        FeaturePostRAScheduler,
 665                                        FeaturePredictableSelectIsExpensive,
 666                                        FeatureNEON]>;
 667
 668 def ProcTSV110 : SubtargetFeature<"tsv110", "ARMProcFamily", "TSV110",
 669                                   "HiSilicon TS-V110 processors", [
 670                                   HasV8_2aOps,
 671                                   FeatureCrypto,
 672                                   FeatureCustomCheapAsMoveHandling,
 673                                   FeatureFPARMv8,
 674                                   FeatureFuseAES,
 675                                   FeatureNEON,
 676                                   FeaturePerfMon,
 677                                   FeaturePostRAScheduler,
 678                                   FeatureSPE,
 679                                   FeatureFullFP16,
 680                                   FeatureFP16FML,
 681                                   FeatureDotProd]>;
 682
 683 def : ProcessorModel<"generic", NoSchedModel, [
 684                      FeatureFPARMv8,
 685                      FeatureFuseAES,
 686                      FeatureNEON,
 687                      FeaturePerfMon,
 688                      FeaturePostRAScheduler
 689                      ]>;
 690
 691 // FIXME: Cortex-A35 and Cortex-A55 are currently modeled as a Cortex-A53.
 692 def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
 693 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
 694 def : ProcessorModel<"cortex-a55", CortexA53Model, [ProcA55]>;
 695 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
 696 // FIXME: Cortex-A72, Cortex-A73 and Cortex-A75 are currently modeled as a Cortex-A57.
 697 def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
 698 def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
 699 def : ProcessorModel<"cortex-a75", CortexA57Model, [ProcA75]>;
 700 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
 701 def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
 702 def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>;
 703 def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>;
 704 def : ProcessorModel<"exynos-m4", ExynosM4Model, [ProcExynosM4]>;
 705 def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;
 706 def : ProcessorModel<"saphira", FalkorModel, [ProcSaphira]>;
 707 def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;
 708 // Cavium ThunderX/ThunderX T8X  Processors
 709 def : ProcessorModel<"thunderx", ThunderXT8XModel,  [ProcThunderX]>;
 710 def : ProcessorModel<"thunderxt88", ThunderXT8XModel,  [ProcThunderXT88]>;
 711 def : ProcessorModel<"thunderxt81", ThunderXT8XModel,  [ProcThunderXT81]>;
 712 def : ProcessorModel<"thunderxt83", ThunderXT8XModel,  [ProcThunderXT83]>;
 713 // Cavium ThunderX2T9X  Processors. Formerly Broadcom Vulcan.
 714 def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, [ProcThunderX2T99]>;
 715 // FIXME: HiSilicon TSV110 is currently modeled as a Cortex-A57.
 716 def : ProcessorModel<"tsv110", CortexA57Model, [ProcTSV110]>;
 717
 718 // Alias for the latest Apple processor model supported by LLVM.
 719 def : ProcessorModel<"apple-latest", CycloneModel, [ProcCyclone]>;
 720
 721 //===----------------------------------------------------------------------===//
 722 // Assembly parser
 723 //===----------------------------------------------------------------------===//
 724
 725 def GenericAsmParserVariant : AsmParserVariant {
 726   int Variant = 0;
 727   string Name = "generic";
 728   string BreakCharacters = ".";
 729   string TokenizingCharacters = "[]*!/";
 730 }
 731
 732 def AppleAsmParserVariant : AsmParserVariant {
 733   int Variant = 1;
 734   string Name = "apple-neon";
 735   string BreakCharacters = ".";
 736   string TokenizingCharacters = "[]*!/";
 737 }
 738
 739 //===----------------------------------------------------------------------===//
 740 // Assembly printer
 741 //===----------------------------------------------------------------------===//
 742 // AArch64 Uses the MC printer for asm output, so make sure the TableGen
 743 // AsmWriter bits get associated with the correct class.
 744 def GenericAsmWriter : AsmWriter {
 745   string AsmWriterClassName  = "InstPrinter";
 746   int PassSubtarget = 1;
 747   int Variant = 0;
 748   bit isMCAsmWriter = 1;
 749 }
 750
 751 def AppleAsmWriter : AsmWriter {
 752   let AsmWriterClassName = "AppleInstPrinter";
 753   int PassSubtarget = 1;
 754   int Variant = 1;
 755   int isMCAsmWriter = 1;
 756 }
 757
 758 //===----------------------------------------------------------------------===//
 759 // Target Declaration
 760 //===----------------------------------------------------------------------===//
 761
 762 def AArch64 : Target {
 763   let InstructionSet = AArch64InstrInfo;
 764   let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
 765   let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
 766   let AllowRegisterRenaming = 1;
 767 }
 768
 769 //===----------------------------------------------------------------------===//
 770 // Pfm Counters
 771 //===----------------------------------------------------------------------===//
 772
 773 include "AArch64PfmCounters.td"