lib/Target/AArch64/AArch64SchedExynosM4.td

   1 //=- AArch64SchedExynosM4.td - Samsung Exynos M4 Sched Defs --*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the machine model for the Samsung Exynos M4 to support
  10 // instruction scheduling and other instruction cost heuristics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // The Exynos-M4 is an advanced superscalar microprocessor with a 6-wide
  16 // in-order stage for decode and dispatch and a wider issue stage.
  17 // The execution units and loads and stores are out-of-order.
  18
  19 def ExynosM4Model : SchedMachineModel {
  20   let IssueWidth            =   6; // Up to 6 uops per cycle.
  21   let MicroOpBufferSize     = 228; // ROB size.
  22   let LoopMicroOpBufferSize =  48; // Based on the instruction queue size.
  23   let LoadLatency           =   4; // Optimistic load cases.
  24   let MispredictPenalty     =  16; // Minimum branch misprediction penalty.
  25   let CompleteModel         =   1; // Use the default model otherwise.
  26
  27   list<Predicate> UnsupportedFeatures = [HasSVE];
  28 }
  29
  30 //===----------------------------------------------------------------------===//
  31 // Define each kind of processor resource and number available on the Exynos-M4.
  32
  33 let SchedModel = ExynosM4Model in {
  34
  35 def M4UnitA  : ProcResource<2>; // Simple integer
  36 def M4UnitC  : ProcResource<2>; // Simple and complex integer
  37 let Super =  M4UnitC, BufferSize = 1 in
  38 def M4UnitD  : ProcResource<1>; // Integer division (inside C0, serialized)
  39 let Super =  M4UnitC in
  40 def M4UnitE  : ProcResource<1>; // CRC (inside C0)
  41 def M4UnitB  : ProcResource<2>; // Branch
  42 def M4UnitL0 : ProcResource<1>; // Load
  43 def M4UnitS0 : ProcResource<1>; // Store
  44 def M4PipeLS : ProcResource<1>; // Load/Store
  45 let Super = M4PipeLS in {
  46   def M4UnitL1 : ProcResource<1>;
  47   def M4UnitS1 : ProcResource<1>;
  48 }
  49 def M4PipeF0 : ProcResource<1>; // FP #0
  50 let Super = M4PipeF0 in {
  51   def M4UnitFMAC0 : ProcResource<1>; // FP multiplication
  52   def M4UnitFADD0 : ProcResource<1>; // Simple FP
  53   def M4UnitFCVT0 : ProcResource<1>; // FP conversion
  54   def M4UnitNALU0 : ProcResource<1>; // Simple vector
  55   def M4UnitNHAD  : ProcResource<1>; // Horizontal vector
  56   def M4UnitNMSC  : ProcResource<1>; // FP and vector miscellanea
  57   def M4UnitNMUL0 : ProcResource<1>; // Vector multiplication
  58   def M4UnitNSHT0 : ProcResource<1>; // Vector shifting
  59   def M4UnitNSHF0 : ProcResource<1>; // Vector shuffling
  60   def M4UnitNCRY0 : ProcResource<1>; // Cryptographic
  61 }
  62 def M4PipeF1 : ProcResource<1>; // FP #1
  63 let Super = M4PipeF1 in {
  64   def M4UnitFMAC1 : ProcResource<1>; // FP multiplication
  65   def M4UnitFADD1 : ProcResource<1>; // Simple FP
  66   def M4UnitFDIV0 : ProcResource<2>; // FP division (serialized)
  67   def M4UnitFSQR0 : ProcResource<2>; // FP square root (serialized)
  68   def M4UnitFST0  : ProcResource<1>; // FP store
  69   def M4UnitNALU1 : ProcResource<1>; // Simple vector
  70   def M4UnitNSHT1 : ProcResource<1>; // Vector shifting
  71   def M4UnitNSHF1 : ProcResource<1>; // Vector shuffling
  72 }
  73 def M4PipeF2 : ProcResource<1>; // FP #2
  74 let Super = M4PipeF2 in {
  75   def M4UnitFMAC2 : ProcResource<1>; // FP multiplication
  76   def M4UnitFADD2 : ProcResource<1>; // Simple FP
  77   def M4UnitFCVT1 : ProcResource<1>; // FP conversion
  78   def M4UnitFDIV1 : ProcResource<2>; // FP division (serialized)
  79   def M4UnitFSQR1 : ProcResource<2>; // FP square root (serialized)
  80   def M4UnitFST1  : ProcResource<1>; // FP store
  81   def M4UnitNALU2 : ProcResource<1>; // Simple vector
  82   def M4UnitNMUL1 : ProcResource<1>; // Vector multiplication
  83   def M4UnitNSHT2 : ProcResource<1>; // Vector shifting
  84   def M4UnitNCRY1 : ProcResource<1>; // Cryptographic
  85 }
  86
  87 def M4UnitALU   : ProcResGroup<[M4UnitA,
  88                                 M4UnitC]>;
  89 def M4UnitL     : ProcResGroup<[M4UnitL0,
  90                                 M4UnitL1]>;
  91 def M4UnitS     : ProcResGroup<[M4UnitS0,
  92                                 M4UnitS1]>;
  93 def M4UnitFMAC  : ProcResGroup<[M4UnitFMAC0,
  94                                 M4UnitFMAC1,
  95                                 M4UnitFMAC2]>;
  96 def M4UnitFMACH : ProcResGroup<[M4UnitFMAC0,
  97                                 M4UnitFMAC1]>;
  98 def M4UnitFADD  : ProcResGroup<[M4UnitFADD0,
  99                                 M4UnitFADD1,
 100                                 M4UnitFADD2]>;
 101 def M4UnitFADDH : ProcResGroup<[M4UnitFADD0,
 102                                 M4UnitFADD1]>;
 103 def M4UnitFCVT  : ProcResGroup<[M4UnitFCVT0,
 104                                 M4UnitFCVT1]>;
 105 def M4UnitFCVTH : ProcResGroup<[M4UnitFCVT0]>;
 106 def M4UnitFDIV  : ProcResGroup<[M4UnitFDIV0,
 107                                 M4UnitFDIV1]>;
 108 def M4UnitFDIVH : ProcResGroup<[M4UnitFDIV0]>;
 109 def M4UnitFSQR  : ProcResGroup<[M4UnitFSQR0,
 110                                 M4UnitFSQR1]>;
 111 def M4UnitFSQRH : ProcResGroup<[M4UnitFSQR0]>;
 112 def M4UnitFST   : ProcResGroup<[M4UnitFST0,
 113                                 M4UnitFST1]>;
 114 def M4UnitNALU  : ProcResGroup<[M4UnitNALU0,
 115                                 M4UnitNALU1,
 116                                 M4UnitNALU2]>;
 117 def M4UnitNALUH : ProcResGroup<[M4UnitNALU0,
 118                                 M4UnitNALU1]>;
 119 def M4UnitNMUL  : ProcResGroup<[M4UnitNMUL0,
 120                                 M4UnitNMUL1]>;
 121 def M4UnitNSHT  : ProcResGroup<[M4UnitNSHT0,
 122                                 M4UnitNSHT1,
 123                                 M4UnitNSHT2]>;
 124 def M4UnitNSHF  : ProcResGroup<[M4UnitNSHF0,
 125                                 M4UnitNSHF1]>;
 126 def M4UnitNSHFH : ProcResGroup<[M4UnitNSHF0]>;
 127 def M4UnitNCRY  : ProcResGroup<[M4UnitNCRY0,
 128                                 M4UnitNCRY1]>;
 129
 130 //===----------------------------------------------------------------------===//
 131 // Resources details.
 132
 133 def M4WriteZ0 : SchedWriteRes<[]> { let Latency = 0; }
 134 def M4WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
 135                                     let NumMicroOps = 0; }
 136 def M4WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
 137                                     let NumMicroOps = 0; }
 138
 139 def M4WriteA1 : SchedWriteRes<[M4UnitALU]> { let Latency = 1; }
 140 def M4WriteA2 : SchedWriteRes<[M4UnitALU]> { let Latency = 2; }
 141 def M4WriteAA : SchedWriteRes<[M4UnitALU]> { let Latency = 2;
 142                                              let ResourceCycles = [2]; }
 143 def M4WriteAB : SchedWriteRes<[M4UnitALU,
 144                                M4UnitC]>   { let Latency = 2;
 145                                              let NumMicroOps = 2; }
 146 def M4WriteAC : SchedWriteRes<[M4UnitALU,
 147                                M4UnitALU,
 148                                M4UnitC]>   { let Latency = 3;
 149                                              let NumMicroOps = 3; }
 150 def M4WriteAD : SchedWriteRes<[M4UnitALU,
 151                                M4UnitC]>   { let Latency = 2;
 152                                              let NumMicroOps = 2; }
 153 def M4WriteAF : SchedWriteRes<[M4UnitALU]> { let Latency = 2;
 154                                              let NumMicroOps = 2; }
 155 def M4WriteAU : SchedWriteVariant<[SchedVar<IsCopyIdiomPred,   [M4WriteZ0]>,
 156                                    SchedVar<ExynosArithPred,   [M4WriteA1]>,
 157                                    SchedVar<ExynosLogicExPred, [M4WriteA1]>,
 158                                    SchedVar<NoSchedPred,       [M4WriteAA]>]>;
 159 def M4WriteAV : SchedWriteVariant<[SchedVar<ExynosResetPred, [M4WriteZ0]>,
 160                                    SchedVar<NoSchedPred,     [M4WriteAA]>]>;
 161 def M4WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred,   [M4WriteA1]>,
 162                                    SchedVar<ExynosLogicExPred, [M4WriteA1]>,
 163                                    SchedVar<NoSchedPred,       [M4WriteAA]>]>;
 164 def M4WriteAY : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M4WriteA1]>,
 165                                    SchedVar<NoSchedPred,              [M4WriteAF]>]>;
 166
 167 def M4WriteB1 : SchedWriteRes<[M4UnitB]> { let Latency = 1; }
 168 def M4WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M4WriteAC]>,
 169                                    SchedVar<NoSchedPred,            [M4WriteAB]>]>;
 170
 171 def M4WriteC1 : SchedWriteRes<[M4UnitC]> { let Latency = 1; }
 172 def M4WriteC3 : SchedWriteRes<[M4UnitC]> { let Latency = 3; }
 173 def M4WriteCA : SchedWriteRes<[M4UnitC]> { let Latency = 4;
 174                                            let ResourceCycles = [2]; }
 175
 176 def M4WriteD12 : SchedWriteRes<[M4UnitD]> { let Latency = 12; }
 177 def M4WriteD21 : SchedWriteRes<[M4UnitD]> { let Latency = 21; }
 178
 179 def M4WriteE2 : SchedWriteRes<[M4UnitE]> { let Latency = 2; }
 180
 181 def M4WriteL4 : SchedWriteRes<[M4UnitL]> { let Latency = 4; }
 182 def M4WriteL5 : SchedWriteRes<[M4UnitL]> { let Latency = 5; }
 183 def M4WriteLA : SchedWriteRes<[M4UnitL,
 184                                M4UnitL]> { let Latency = 5;
 185                                            let NumMicroOps = 1; }
 186 def M4WriteLB : SchedWriteRes<[M4UnitA,
 187                                M4UnitL]> { let Latency = 5;
 188                                            let NumMicroOps = 2; }
 189 def M4WriteLC : SchedWriteRes<[M4UnitA,
 190                                M4UnitL,
 191                                M4UnitL]> { let Latency = 5;
 192                                            let NumMicroOps = 2; }
 193 def M4WriteLD : SchedWriteRes<[M4UnitA,
 194                                M4UnitL]> { let Latency = 4;
 195                                            let NumMicroOps = 2; }
 196 def M4WriteLE : SchedWriteRes<[M4UnitA,
 197                                M4UnitL]> { let Latency = 6;
 198                                            let NumMicroOps = 2; }
 199 def M4WriteLH : SchedWriteRes<[]>        { let Latency = 5;
 200                                            let NumMicroOps = 0; }
 201 def M4WriteLX : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M4WriteL5]>,
 202                                    SchedVar<NoSchedPred,   [M4WriteL4]>]>;
 203
 204 def M4WriteS1 : SchedWriteRes<[M4UnitS]>  { let Latency = 1; }
 205 def M4WriteSA : SchedWriteRes<[M4UnitS0]> { let Latency = 3; }
 206 def M4WriteSB : SchedWriteRes<[M4UnitA,
 207                                M4UnitS]>  { let Latency = 2;
 208                                             let NumMicroOps = 1; }
 209 def M4WriteSX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteSB]>,
 210                                    SchedVar<NoSchedPred,         [M4WriteS1]>]>;
 211
 212 def M4ReadAdrBase : SchedReadVariant<[SchedVar<
 213                                         MCSchedPredicate<
 214                                           CheckAny<
 215                                             [ScaledIdxFn,
 216                                              ExynosScaledIdxFn]>>, [ReadDefault]>,
 217                                       SchedVar<NoSchedPred,        [ReadDefault]>]>;
 218
 219 def M4WriteNEONA   : SchedWriteRes<[M4UnitNSHF,
 220                                     M4UnitFADD]>  { let Latency = 3;
 221                                                     let NumMicroOps = 2; }
 222 def M4WriteNEONB   : SchedWriteRes<[M4UnitNALU,
 223                                     M4UnitS0]>    { let Latency = 5;
 224                                                     let NumMicroOps = 2; }
 225 def M4WriteNEOND   : SchedWriteRes<[M4UnitNSHF,
 226                                     M4UnitFST]>   { let Latency = 6;
 227                                                     let NumMicroOps = 2; }
 228 def M4WriteNEONH   : SchedWriteRes<[M4UnitNALU,
 229                                     M4UnitS0]>    { let Latency = 5;
 230                                                     let NumMicroOps = 2; }
 231 def M4WriteNEONI   : SchedWriteRes<[M4UnitNSHF,
 232                                     M4UnitS0]>    { let Latency = 2;
 233                                                     let NumMicroOps = 2; }
 234 def M4WriteNEONJ   : SchedWriteRes<[M4UnitNMSC,
 235                                     M4UnitS0]>    { let Latency = 4; }
 236 def M4WriteNEONK   : SchedWriteRes<[M4UnitNSHF,
 237                                     M4UnitNMSC,
 238                                     M4UnitS0]>    { let Latency = 5;
 239                                                     let NumMicroOps = 2; }
 240 def M4WriteNEONL   : SchedWriteRes<[M4UnitNMUL]>  { let Latency = 3; }
 241 def M4WriteNEONM   : SchedWriteRes<[M4UnitNMUL]>  { let Latency = 3; }
 242 def M4WriteNEONN   : SchedWriteRes<[M4UnitNMSC,
 243                                     M4UnitNMSC]>  { let Latency = 5;
 244                                                     let NumMicroOps = 2; }
 245 def M4WriteNEONO   : SchedWriteRes<[M4UnitNMSC,
 246                                     M4UnitNMSC,
 247                                     M4UnitNMSC]>  { let Latency = 8;
 248                                                     let NumMicroOps = 3; }
 249 def M4WriteNEONP   : SchedWriteRes<[M4UnitNSHF,
 250                                     M4UnitNMSC]>  { let Latency = 4;
 251                                                     let NumMicroOps = 2; }
 252 def M4WriteNEONQ   : SchedWriteRes<[M4UnitNMSC,
 253                                     M4UnitC]>     { let Latency = 3;
 254                                                     let NumMicroOps = 1; }
 255 def M4WriteNEONR   : SchedWriteRes<[M4UnitFCVT0,
 256                                     M4UnitS0]>    { let Latency = 4;
 257                                                     let NumMicroOps = 1; }
 258 def M4WriteNEONV   : SchedWriteRes<[M4UnitFDIV,
 259                                     M4UnitFDIV]>  { let Latency = 7;
 260                                                     let ResourceCycles = [6, 6]; }
 261 def M4WriteNEONVH  : SchedWriteRes<[M4UnitFDIVH,
 262                                     M4UnitFDIVH]> { let Latency = 7;
 263                                                     let ResourceCycles = [6, 6]; }
 264 def M4WriteNEONW   : SchedWriteRes<[M4UnitFDIV,
 265                                     M4UnitFDIV]>  { let Latency = 12;
 266                                                     let ResourceCycles = [9, 9]; }
 267 def M4WriteNEONX   : SchedWriteRes<[M4UnitFSQR,
 268                                     M4UnitFSQR]>  { let Latency = 8;
 269                                                     let ResourceCycles = [7, 7]; }
 270 def M4WriteNEONXH  : SchedWriteRes<[M4UnitFSQRH,
 271                                     M4UnitFSQRH]> { let Latency = 7;
 272                                                     let ResourceCycles = [6, 6]; }
 273 def M4WriteNEONY   : SchedWriteRes<[M4UnitFSQR,
 274                                     M4UnitFSQR]>  { let Latency = 12;
 275                                                     let ResourceCycles = [9, 9]; }
 276 def M4WriteNEONZ   : SchedWriteVariant<[SchedVar<ExynosQFormPred, [M4WriteNEONO]>,
 277                                         SchedVar<NoSchedPred,     [M4WriteNEONN]>]>;
 278
 279 def M4WriteFADD2   : SchedWriteRes<[M4UnitFADD]>  { let Latency = 2; }
 280 def M4WriteFADD2H  : SchedWriteRes<[M4UnitFADDH]> { let Latency = 2; }
 281
 282 def M4WriteFCVT2   : SchedWriteRes<[M4UnitFCVT]>  { let Latency = 2; }
 283 def M4WriteFCVT2A  : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 2; }
 284 def M4WriteFCVT2H  : SchedWriteRes<[M4UnitFCVTH]> { let Latency = 2; }
 285 def M4WriteFCVT3   : SchedWriteRes<[M4UnitFCVT]>  { let Latency = 3; }
 286 def M4WriteFCVT3A  : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 3; }
 287 def M4WriteFCVT3H  : SchedWriteRes<[M4UnitFCVTH]> { let Latency = 3; }
 288 def M4WriteFCVT4   : SchedWriteRes<[M4UnitFCVT]>  { let Latency = 4; }
 289 def M4WriteFCVT4A  : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 4; }
 290 def M4WriteFCVT6A  : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 6; }
 291
 292 def M4WriteFDIV7   : SchedWriteRes<[M4UnitFDIV]>  { let Latency = 7;
 293                                                     let ResourceCycles = [6]; }
 294 def M4WriteFDIV7H  : SchedWriteRes<[M4UnitFDIVH]> { let Latency = 7;
 295                                                     let ResourceCycles = [6]; }
 296 def M4WriteFDIV12  : SchedWriteRes<[M4UnitFDIV]>  { let Latency = 12;
 297                                                     let ResourceCycles = [9]; }
 298
 299 def M4WriteFMAC2H  : SchedWriteRes<[M4UnitFMACH]> { let Latency = 2; }
 300 def M4WriteFMAC3H  : SchedWriteRes<[M4UnitFMACH]> { let Latency = 3; }
 301 def M4WriteFMAC3   : SchedWriteRes<[M4UnitFMAC]>  { let Latency = 3; }
 302 def M4WriteFMAC4   : SchedWriteRes<[M4UnitFMAC]>  { let Latency = 4; }
 303 def M4WriteFMAC4H  : SchedWriteRes<[M4UnitFMACH]> { let Latency = 4; }
 304 def M4WriteFMAC5   : SchedWriteRes<[M4UnitFMAC]>  { let Latency = 5; }
 305
 306 def M4WriteFSQR7H  : SchedWriteRes<[M4UnitFSQRH]> { let Latency = 7;
 307                                                     let ResourceCycles = [6]; }
 308 def M4WriteFSQR8   : SchedWriteRes<[M4UnitFSQR]>  { let Latency = 8;
 309                                                     let ResourceCycles = [7]; }
 310 def M4WriteFSQR12  : SchedWriteRes<[M4UnitFSQR]>  { let Latency = 12;
 311                                                     let ResourceCycles = [9]; }
 312
 313 def M4WriteNALU1   : SchedWriteRes<[M4UnitNALU]>  { let Latency = 1; }
 314 def M4WriteNALU1H  : SchedWriteRes<[M4UnitNALUH]> { let Latency = 1; }
 315
 316 def M4WriteNCRY1   : SchedWriteRes<[M4UnitNCRY]>  { let Latency = 1; }
 317 def M4WriteNCRY1A  : SchedWriteRes<[M4UnitNCRY0]> { let Latency = 1; }
 318 def M4WriteNCRY3A  : SchedWriteRes<[M4UnitNCRY0]> { let Latency = 3; }
 319 def M4WriteNCRY5A  : SchedWriteRes<[M4UnitNCRY]>  { let Latency = 5; }
 320
 321 def M4WriteNHAD1   : SchedWriteRes<[M4UnitNHAD]>  { let Latency = 1; }
 322 def M4WriteNHAD3   : SchedWriteRes<[M4UnitNHAD]>  { let Latency = 3; }
 323
 324 def M4WriteNMSC1   : SchedWriteRes<[M4UnitNMSC]>  { let Latency = 1; }
 325 def M4WriteNMSC2   : SchedWriteRes<[M4UnitNMSC]>  { let Latency = 2; }
 326 def M4WriteNMSC3   : SchedWriteRes<[M4UnitNMSC]>  { let Latency = 3; }
 327
 328 def M4WriteNMUL3   : SchedWriteRes<[M4UnitNMUL]>  { let Latency = 3; }
 329
 330 def M4WriteNSHF1   : SchedWriteRes<[M4UnitNSHF]>  { let Latency = 1; }
 331 def M4WriteNSHF1H  : SchedWriteRes<[M4UnitNSHFH]> { let Latency = 1; }
 332 def M4WriteNSHF3   : SchedWriteRes<[M4UnitNSHF]>  { let Latency = 3; }
 333 def M4WriteNSHFA   : SchedWriteRes<[M4UnitNSHF]>  { let Latency = 1;
 334                                                     let ResourceCycles = [2]; }
 335 def M4WriteNSHFB   : SchedWriteRes<[M4UnitNSHF]>  { let Latency = 2;
 336                                                     let NumMicroOps = 2;
 337                                                     let ResourceCycles = [2]; }
 338 def M4WriteNSHFC   : SchedWriteRes<[M4UnitNSHF]>  { let Latency = 3;
 339                                                     let NumMicroOps = 3;
 340                                                     let ResourceCycles = [4]; }
 341 def M4WriteNSHFD   : SchedWriteRes<[M4UnitNSHF]>  { let Latency = 4;
 342                                                     let NumMicroOps = 4;
 343                                                     let ResourceCycles = [4]; }
 344
 345 def M4WriteNSHT1   : SchedWriteRes<[M4UnitNSHT]>  { let Latency = 1; }
 346 def M4WriteNSHT2   : SchedWriteRes<[M4UnitNSHT]>  { let Latency = 2; }
 347 def M4WriteNSHT3   : SchedWriteRes<[M4UnitNSHT]>  { let Latency = 3; }
 348 def M4WriteNSHT4A  : SchedWriteRes<[M4UnitNSHT1]> { let Latency = 4; }
 349
 350 def M4WriteVLDA    : SchedWriteRes<[M4UnitL,
 351                                     M4UnitL]>     { let Latency = 5;
 352                                                     let NumMicroOps = 2; }
 353 def M4WriteVLDB    : SchedWriteRes<[M4UnitL,
 354                                     M4UnitL,
 355                                     M4UnitL]>     { let Latency = 6;
 356                                                     let NumMicroOps = 3; }
 357 def M4WriteVLDC    : SchedWriteRes<[M4UnitL,
 358                                     M4UnitL,
 359                                     M4UnitL,
 360                                     M4UnitL]>     { let Latency = 6;
 361                                                     let NumMicroOps = 4; }
 362 def M4WriteVLDD    : SchedWriteRes<[M4UnitL,
 363                                     M4UnitNSHF]>  { let Latency = 6;
 364                                                     let NumMicroOps = 2;
 365                                                     let ResourceCycles = [2, 1]; }
 366 def M4WriteVLDF    : SchedWriteRes<[M4UnitL,
 367                                     M4UnitL]>     { let Latency = 10;
 368                                                     let NumMicroOps = 2;
 369                                                     let ResourceCycles = [3, 3]; }
 370 def M4WriteVLDG    : SchedWriteRes<[M4UnitL,
 371                                     M4UnitNSHF,
 372                                     M4UnitNSHF]>  { let Latency = 6;
 373                                                     let NumMicroOps = 3;
 374                                                     let ResourceCycles = [2, 1, 1]; }
 375 def M4WriteVLDI    : SchedWriteRes<[M4UnitL,
 376                                     M4UnitL,
 377                                     M4UnitL]>     { let Latency = 12;
 378                                                     let NumMicroOps = 3;
 379                                                     let ResourceCycles = [3, 3, 3]; }
 380 def M4WriteVLDJ    : SchedWriteRes<[M4UnitL,
 381                                     M4UnitNSHF,
 382                                     M4UnitNSHF,
 383                                     M4UnitNSHF]>  { let Latency = 7;
 384                                                     let NumMicroOps = 4;
 385                                                     let ResourceCycles = [3, 1, 1, 1]; }
 386 def M4WriteVLDK    : SchedWriteRes<[M4UnitL,
 387                                     M4UnitNSHF,
 388                                     M4UnitNSHF,
 389                                     M4UnitNSHF,
 390                                     M4UnitNSHF]>  { let Latency = 7;
 391                                                     let NumMicroOps = 5;
 392                                                     let ResourceCycles = [3, 1, 1, 1, 1]; }
 393 def M4WriteVLDL    : SchedWriteRes<[M4UnitL,
 394                                     M4UnitNSHF,
 395                                     M4UnitNSHF,
 396                                     M4UnitL,
 397                                     M4UnitNSHF]>  { let Latency = 7;
 398                                                     let NumMicroOps = 5;
 399                                                     let ResourceCycles = [3, 1, 1, 6, 1]; }
 400 def M4WriteVLDM    : SchedWriteRes<[M4UnitL,
 401                                     M4UnitNSHF,
 402                                     M4UnitNSHF,
 403                                     M4UnitL,
 404                                     M4UnitNSHF,
 405                                     M4UnitNSHF]>  { let Latency = 7;
 406                                                     let NumMicroOps = 6;
 407                                                     let ResourceCycles = [3, 1, 1, 3, 1, 1]; }
 408 def M4WriteVLDN    : SchedWriteRes<[M4UnitL,
 409                                     M4UnitL,
 410                                     M4UnitL,
 411                                     M4UnitL]>     { let Latency = 14;
 412                                                     let NumMicroOps = 4;
 413                                                     let ResourceCycles = [3, 3, 3, 3]; }
 414
 415 def M4WriteVST1    : SchedWriteRes<[M4UnitS,
 416                                     M4UnitFST]>  { let Latency = 1;
 417                                                    let NumMicroOps = 1; }
 418 def M4WriteVSTA    : WriteSequence<[WriteVST], 2>;
 419 def M4WriteVSTB    : WriteSequence<[WriteVST], 3>;
 420 def M4WriteVSTC    : WriteSequence<[WriteVST], 4>;
 421 def M4WriteVSTD    : SchedWriteRes<[M4UnitS,
 422                                     M4UnitFST]>   { let Latency = 2; }
 423 def M4WriteVSTE    : SchedWriteRes<[M4UnitS,
 424                                     M4UnitFST,
 425                                     M4UnitS,
 426                                     M4UnitFST]>   { let Latency = 2;
 427                                                     let NumMicroOps = 2; }
 428 def M4WriteVSTF    : SchedWriteRes<[M4UnitNSHF,
 429                                     M4UnitS,
 430                                     M4UnitFST,
 431                                     M4UnitS,
 432                                     M4UnitFST]>   { let Latency = 4;
 433                                                     let NumMicroOps = 4;
 434                                                     let ResourceCycles = [1, 2, 1, 2, 1]; }
 435 def M4WriteVSTG    : SchedWriteRes<[M4UnitNSHF,
 436                                     M4UnitNSHF,
 437                                     M4UnitNSHF,
 438                                     M4UnitS,
 439                                     M4UnitFST,
 440                                     M4UnitS,
 441                                     M4UnitFST,
 442                                     M4UnitS,
 443                                     M4UnitFST]>   { let Latency = 5;
 444                                                     let NumMicroOps = 6;
 445                                                     let ResourceCycles = [1, 1, 1, 2, 1, 2, 1, 2, 1]; }
 446 def M4WriteVSTI    : SchedWriteRes<[M4UnitNSHF,
 447                                     M4UnitNSHF,
 448                                     M4UnitNSHF,
 449                                     M4UnitNSHF,
 450                                     M4UnitS,
 451                                     M4UnitFST,
 452                                     M4UnitS,
 453                                     M4UnitFST,
 454                                     M4UnitS,
 455                                     M4UnitFST,
 456                                     M4UnitS,
 457                                     M4UnitFST]>   { let Latency = 8;
 458                                                     let NumMicroOps = 5;
 459                                                     let ResourceCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; }
 460 def M4WriteVSTJ    : SchedWriteRes<[M4UnitA,
 461                                     M4UnitS,
 462                                     M4UnitFST]>   { let Latency = 1;
 463                                                     let NumMicroOps = 2; }
 464 def M4WriteVSTK    : SchedWriteRes<[M4UnitA,
 465                                     M4UnitS,
 466                                     M4UnitFST]>   { let Latency = 3;
 467                                                     let NumMicroOps = 2; }
 468 def M4WriteVSTL    : SchedWriteRes<[M4UnitNSHF,
 469                                     M4UnitNSHF,
 470                                     M4UnitS,
 471                                     M4UnitFST,
 472                                     M4UnitS,
 473                                     M4UnitFST]>   { let Latency = 4;
 474                                                     let NumMicroOps = 4;
 475                                                     let ResourceCycles = [1, 1, 2, 1, 2, 1]; }
 476
 477 // Special cases.
 478 def M4WriteCOPY    : SchedWriteVariant<[SchedVar<ExynosFPPred, [M4WriteNALU1]>,
 479                                         SchedVar<NoSchedPred,  [M4WriteZ0]>]>;
 480 def M4WriteMOVI    : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M4WriteZ0]>,
 481                                         SchedVar<NoSchedPred,       [M4WriteNALU1]>]>;
 482 def M4WriteMULL    : SchedWriteVariant<[SchedVar<ExynosLongVectorUpperPred, [M4WriteNEONM]>,
 483                                         SchedVar<NoSchedPred,               [M4WriteNMUL3]>]>;
 484
 485 // Fast forwarding.
 486 def M4ReadAESM1    : SchedReadAdvance<+1, [M4WriteNCRY1]>;
 487 def M4ReadFMACM1   : SchedReadAdvance<+1, [M4WriteFMAC4,
 488                                            M4WriteFMAC4H,
 489                                            M4WriteFMAC5]>;
 490 def M4ReadNMULM1   : SchedReadAdvance<+1, [M4WriteNMUL3]>;
 491 def M4ReadMULLP2   : SchedReadAdvance<-2, [M4WriteNEONM]>;
 492
 493 //===----------------------------------------------------------------------===//
 494 // Coarse scheduling model.
 495
 496 // Branch instructions.
 497 def : SchedAlias<WriteBr,    M4WriteZ0>;
 498 def : SchedAlias<WriteBrReg, M4WriteC1>;
 499
 500 // Arithmetic and logical integer instructions.
 501 def : SchedAlias<WriteI,     M4WriteA1>;
 502 def : SchedAlias<WriteIEReg, M4WriteAA>; // FIXME: M4WriteAX crashes TableGen.
 503 def : SchedAlias<WriteISReg, M4WriteAA>; // FIXME: M4WriteAX crashes TableGen.
 504 def : SchedAlias<WriteIS,    M4WriteA1>;
 505
 506 // Move instructions.
 507 def : SchedAlias<WriteImm, M4WriteA1>;
 508
 509 // Divide and multiply instructions.
 510 def : SchedAlias<WriteID32, M4WriteD12>;
 511 def : SchedAlias<WriteID64, M4WriteD21>;
 512 def : SchedAlias<WriteIM32, M4WriteC3>;
 513 def : SchedAlias<WriteIM64, M4WriteCA>;
 514
 515 // Miscellaneous instructions.
 516 def : SchedAlias<WriteExtr, M4WriteAY>;
 517
 518 // Addressing modes.
 519 def : SchedAlias<WriteAdr,    M4WriteZ1>;
 520 def : SchedAlias<ReadAdrBase, M4ReadAdrBase>;
 521
 522 // Load instructions.
 523 def : SchedAlias<WriteLD,    M4WriteL4>;
 524 def : SchedAlias<WriteLDHi,  M4WriteZ4>;
 525 def : SchedAlias<WriteLDIdx, M4WriteLX>;
 526
 527 // Store instructions.
 528 def : SchedAlias<WriteST,    M4WriteS1>;
 529 def : SchedAlias<WriteSTP,   M4WriteS1>;
 530 def : SchedAlias<WriteSTX,   M4WriteS1>;
 531 def : SchedAlias<WriteSTIdx, M4WriteSX>;
 532
 533 // FP data instructions.
 534 def : SchedAlias<WriteF,    M4WriteFADD2>;
 535 def : SchedAlias<WriteFCmp, M4WriteNMSC2>;
 536 def : SchedAlias<WriteFDiv, M4WriteFDIV12>;
 537 def : SchedAlias<WriteFMul, M4WriteFMAC3>;
 538
 539 // FP miscellaneous instructions.
 540 def : SchedAlias<WriteFCvt,  M4WriteFCVT2>;
 541 def : SchedAlias<WriteFImm,  M4WriteNALU1>;
 542 def : SchedAlias<WriteFCopy, M4WriteCOPY>;
 543
 544 // FP load instructions.
 545 def : SchedAlias<WriteVLD, M4WriteL5>;
 546
 547 // FP store instructions.
 548 def : SchedAlias<WriteVST, M4WriteVST1>;
 549
 550 // ASIMD FP instructions.
 551 def : SchedAlias<WriteV, M4WriteNALU1>;
 552
 553 // Other miscellaneous instructions.
 554 def : WriteRes<WriteAtomic,  []> { let Unsupported = 1; }
 555 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
 556 def : WriteRes<WriteHint,    []> { let Latency = 1; }
 557 def : WriteRes<WriteSys,     []> { let Latency = 1; }
 558
 559 //===----------------------------------------------------------------------===//
 560 // Generic fast forwarding.
 561
 562 // TODO: Add FP register forwarding rules.
 563
 564 def : ReadAdvance<ReadI,       0>;
 565 def : ReadAdvance<ReadISReg,   0>;
 566 def : ReadAdvance<ReadIEReg,   0>;
 567 def : ReadAdvance<ReadIM,      0>;
 568 // TODO: The forwarding for 32 bits actually saves 2 cycles.
 569 def : ReadAdvance<ReadIMA,     3, [WriteIM32, WriteIM64]>;
 570 def : ReadAdvance<ReadID,      0>;
 571 def : ReadAdvance<ReadExtrHi,  0>;
 572 def : ReadAdvance<ReadAdrBase, 0>;
 573 def : ReadAdvance<ReadVLD,     0>;
 574
 575 //===----------------------------------------------------------------------===//
 576 // Finer scheduling model.
 577
 578 // Branch instructions
 579 def : InstRW<[M4WriteB1], (instrs Bcc)>;
 580 def : InstRW<[M4WriteAF], (instrs BL)>;
 581 def : InstRW<[M4WriteBX], (instrs BLR)>;
 582 def : InstRW<[M4WriteC1], (instregex "^CBN?Z[WX]")>;
 583 def : InstRW<[M4WriteAD], (instregex "^TBN?Z[WX]")>;
 584
 585 // Arithmetic and logical integer instructions.
 586 def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>;
 587 def : InstRW<[M4WriteAU], (instrs ORRWrs, ORRXrs)>;
 588 def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>;
 589 def : InstRW<[M4WriteAX], (instregex "^(ADD|SUB)S?[WX]rx(64)?$")>;
 590 def : InstRW<[M4WriteAV], (instrs ADDWri, ADDXri, ORRWri, ORRXri)>;
 591
 592 // Move instructions.
 593 def : InstRW<[M4WriteCOPY], (instrs COPY)>;
 594 def : InstRW<[M4WriteZ0],   (instrs ADR, ADRP)>;
 595 def : InstRW<[M4WriteZ0],   (instregex "^MOV[NZ][WX]i")>;
 596
 597 // Divide and multiply instructions.
 598
 599 // Miscellaneous instructions.
 600
 601 // Load instructions.
 602 def : InstRW<[M4WriteLD,
 603               WriteLDHi,
 604               WriteAdr],    (instregex "^LDP(SW|W|X)(post|pre)")>;
 605 def : InstRW<[M4WriteL5,
 606               ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
 607 def : InstRW<[WriteLDIdx,
 608               ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
 609 def : InstRW<[M4WriteL5,
 610               ReadAdrBase], (instrs PRFMroW)>;
 611 def : InstRW<[WriteLDIdx,
 612               ReadAdrBase], (instrs PRFMroX)>;
 613
 614 // Store instructions.
 615 def : InstRW<[M4WriteSB,
 616               ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>;
 617 def : InstRW<[WriteST,
 618               ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>;
 619
 620 // FP data instructions.
 621 def : InstRW<[M4WriteNSHF1H], (instrs FABSHr)>;
 622 def : InstRW<[M4WriteNSHF1],  (instregex "^FABS[SD]r")>;
 623 def : InstRW<[M4WriteFADD2H], (instregex "^F(ADD|SUB)Hrr")>;
 624 def : InstRW<[M4WriteFADD2],  (instregex "^F(ADD|SUB)[SD]rr")>;
 625 def : InstRW<[M4WriteFADD2H], (instregex "^FADDPv.i16")>;
 626 def : InstRW<[M4WriteFADD2],  (instregex "^FADDPv.i(32|64)")>;
 627 def : InstRW<[M4WriteNEONQ],  (instregex "^FCCMPE?[HSD]rr")>;
 628 def : InstRW<[M4WriteNMSC2],  (instregex "^FCMPE?[HSD]r[ir]")>;
 629 def : InstRW<[M4WriteNMSC1],  (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)(16|32|64|v1)")>;
 630 def : InstRW<[M4WriteFDIV7H], (instrs FDIVHrr)>;
 631 def : InstRW<[M4WriteFDIV7],  (instrs FDIVSrr)>;
 632 def : InstRW<[M4WriteFDIV12], (instrs FDIVDrr)>;
 633 def : InstRW<[M4WriteNMSC1],  (instregex "^F(MAX|MIN)(NM)?[HSD]rr")>;
 634 def : InstRW<[M4WriteFMAC3H], (instregex "^FN?MULHrr")>;
 635 def : InstRW<[M4WriteFMAC3],  (instregex "^FN?MUL[SD]rr")>;
 636 def : InstRW<[M4WriteFMAC3H], (instrs FMULX16)>;
 637 def : InstRW<[M4WriteFMAC3],  (instregex "^FMULX(32|64)")>;
 638 def : InstRW<[M4WriteFMAC4H,
 639               M4ReadFMACM1],  (instregex "^FN?M(ADD|SUB)Hrrr")>;
 640 def : InstRW<[M4WriteFMAC4,
 641               M4ReadFMACM1],  (instregex "^FN?M(ADD|SUB)[SD]rrr")>;
 642 def : InstRW<[M4WriteNALU1H], (instrs FNEGHr)>;
 643 def : InstRW<[M4WriteNALU1],  (instregex "^FNEG[SD]r")>;
 644 def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT.+r")>;
 645 def : InstRW<[M4WriteNEONH],  (instregex "^FCSEL[HSD]rrr")>;
 646 def : InstRW<[M4WriteFSQR7H], (instrs FSQRTHr)>;
 647 def : InstRW<[M4WriteFSQR8],  (instrs FSQRTSr)>;
 648 def : InstRW<[M4WriteFSQR12], (instrs FSQRTDr)>;
 649
 650 // FP miscellaneous instructions.
 651 def : InstRW<[M4WriteFCVT2H], (instregex "^FCVTH[SD]r")>;
 652 def : InstRW<[M4WriteFCVT2H], (instregex "^FCVT[SD]Hr")>;
 653 def : InstRW<[M4WriteFCVT2],  (instregex "^FCVT[SD][SD]r")>;
 654 def : InstRW<[M4WriteFCVT6A], (instregex "^[SU]CVTF[SU][XW][HSD]ri")>;
 655 def : InstRW<[M4WriteNEONR],  (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>;
 656 def : InstRW<[M4WriteNALU1],  (instregex "^FMOV[HSD][ir]")>;
 657 def : InstRW<[M4WriteSA],     (instregex "^FMOV[WX][HSD]r")>;
 658 def : InstRW<[M4WriteNEONJ],  (instregex "^FMOV[HSD][WX]r")>;
 659 def : InstRW<[M4WriteNEONI],  (instregex "^FMOVXDHighr")>;
 660 def : InstRW<[M4WriteNEONK],  (instregex "^FMOVDXHighr")>;
 661 def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev1f16")>;
 662 def : InstRW<[M4WriteFCVT3],  (instregex "^F(RECP|RSQRT)Ev1i(32|64)")>;
 663 def : InstRW<[M4WriteNMSC1],  (instregex "^FRECPXv1")>;
 664 def : InstRW<[M4WriteFMAC4H,
 665               M4ReadFMACM1],  (instregex "^F(RECP|RSQRT)S16")>;
 666 def : InstRW<[M4WriteFMAC4,
 667               M4ReadFMACM1],  (instregex "^F(RECP|RSQRT)S(32|64)")>;
 668
 669 // FP load instructions.
 670 def : InstRW<[WriteVLD],    (instregex "^LDR[SDQ]l")>;
 671 def : InstRW<[WriteVLD],    (instregex "^LDUR[BHSDQ]i")>;
 672 def : InstRW<[WriteVLD,
 673               WriteAdr],    (instregex "^LDR[BHSDQ](post|pre)")>;
 674 def : InstRW<[WriteVLD],    (instregex "^LDR[BHSDQ]ui")>;
 675 def : InstRW<[M4WriteLE,
 676               ReadAdrBase], (instregex "^LDR[BHSDQ]roW")>;
 677 def : InstRW<[WriteVLD,
 678               ReadAdrBase], (instregex "^LDR[BHSD]roX")>;
 679 def : InstRW<[M4WriteLE,
 680               ReadAdrBase], (instrs LDRQroX)>;
 681 def : InstRW<[WriteVLD,
 682               M4WriteLH],   (instregex "^LDN?P[SD]i")>;
 683 def : InstRW<[M4WriteLA,
 684               M4WriteLH],   (instregex "^LDN?PQi")>;
 685 def : InstRW<[M4WriteL5,
 686               M4WriteLH,
 687               WriteAdr],    (instregex "^LDP[SD]post")>;
 688 def : InstRW<[M4WriteLB,
 689               M4WriteLH,
 690               WriteAdr],    (instrs LDPQpost)>;
 691 def : InstRW<[M4WriteLB,
 692               M4WriteLH,
 693               WriteAdr],    (instregex "^LDP[SD]pre")>;
 694 def : InstRW<[M4WriteLC,
 695               M4WriteLH,
 696               WriteAdr],    (instrs LDPQpre)>;
 697
 698 // FP store instructions.
 699 def : InstRW<[WriteVST],    (instregex "^STUR[BHSDQ]i")>;
 700 def : InstRW<[WriteVST,
 701               WriteAdr],    (instregex "^STR[BHSDQ](post|pre)")>;
 702 def : InstRW<[WriteVST],    (instregex "^STR[BHSDQ]ui")>;
 703 def : InstRW<[M4WriteVSTJ,
 704               ReadAdrBase], (instregex "^STR[BHSD]roW")>;
 705 def : InstRW<[M4WriteVSTK,
 706               ReadAdrBase], (instrs STRQroW)>;
 707 def : InstRW<[WriteVST,
 708               ReadAdrBase], (instregex "^STR[BHSD]roX")>;
 709 def : InstRW<[M4WriteVSTK,
 710               ReadAdrBase], (instrs STRQroX)>;
 711 def : InstRW<[WriteVST],    (instregex "^STN?P[SD]i")>;
 712 def : InstRW<[M4WriteVSTA], (instregex "^STN?PQi")>;
 713 def : InstRW<[WriteVST,
 714               WriteAdr],    (instregex "^STP[SD](post|pre)")>;
 715 def : InstRW<[M4WriteVSTJ,
 716               WriteAdr],    (instregex "^STPQ(post|pre)")>;
 717
 718 // ASIMD instructions.
 719 def : InstRW<[M4WriteNHAD1],  (instregex "^[SU]ABDL?v")>;
 720 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU]ABAL?v")>;
 721 def : InstRW<[M4WriteNMSC1],  (instregex "^ABSv")>;
 722 def : InstRW<[M4WriteNALU1],  (instregex "^(ADD|NEG|SUB)v")>;
 723 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU]?ADDL?Pv")>;
 724 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU]H(ADD|SUB)v")>;
 725 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU](ADD|SUB)[LW]v")>;
 726 def : InstRW<[M4WriteNHAD3],  (instregex "^R?(ADD|SUB)HN2?v")>;
 727 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU]Q(ADD|SUB)v")>;
 728 def : InstRW<[M4WriteNHAD3],  (instregex "^(SU|US)QADDv")>;
 729 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU]RHADDv")>;
 730 def : InstRW<[M4WriteNMSC1],  (instregex "^SQ(ABS|NEG)v")>;
 731 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU]?ADDL?Vv")>;
 732 def : InstRW<[M4WriteNMSC1],  (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>;
 733 def : InstRW<[M4WriteNALU1],  (instregex "^CMTSTv")>;
 734 def : InstRW<[M4WriteNALU1],  (instregex "^(AND|BIC|EOR|NOT|ORN|ORR)v")>;
 735 def : InstRW<[M4WriteNMSC1],  (instregex "^[SU](MIN|MAX)v")>;
 736 def : InstRW<[M4WriteNMSC2],  (instregex "^[SU](MIN|MAX)Pv")>;
 737 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU](MIN|MAX)Vv")>;
 738 def : InstRW<[M4WriteNMUL3],  (instregex "^(SQR?D)?MULH?v")>;
 739 def : InstRW<[M4WriteNMUL3,
 740               M4ReadNMULM1],  (instregex "^ML[AS]v")>;
 741 def : InstRW<[M4WriteNMUL3],  (instregex "^SQRDML[AS]H")>;
 742 def : InstRW<[M4WriteMULL,
 743               M4ReadMULLP2],  (instregex "^(S|U|SQD)ML[AS]Lv")>;
 744 def : InstRW<[M4WriteMULL,
 745               M4ReadMULLP2],  (instregex "^(S|U|SQD)MULLv")>;
 746 def : InstRW<[M4WriteNMUL3],  (instregex "^[SU]DOT(lane)?v")>;
 747 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU]ADALPv")>;
 748 def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]R?SRA[dv]")>;
 749 def : InstRW<[M4WriteNSHT1],  (instregex "^SHL[dv]")>;
 750 def : InstRW<[M4WriteNSHT1],  (instregex "^S[LR]I[dv]")>;
 751 def : InstRW<[M4WriteNSHT1],  (instregex "^[SU]SH[LR][dv]")>;
 752 def : InstRW<[M4WriteNSHT2],  (instregex "^[SU]?SHLLv")>;
 753 def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]?Q?R?SHRU?N[bhsv]")>;
 754 def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]RSH[LR][dv]")>;
 755 def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]QR?SHLU?[bhsdv]")>;
 756
 757 // ASIMD FP instructions.
 758 def : InstRW<[M4WriteNSHF1H], (instregex "^FABSv.f16")>;
 759 def : InstRW<[M4WriteNSHF1],  (instregex "^FABSv.f(32|64)")>;
 760 def : InstRW<[M4WriteFADD2H], (instregex "^F(ABD|ADD|SUB)v.f16")>;
 761 def : InstRW<[M4WriteFADD2],  (instregex "^F(ABD|ADD|SUB)v.f(32|64)")>;
 762 def : InstRW<[M4WriteFADD2H], (instregex "^FADDPv.f16")>;
 763 def : InstRW<[M4WriteFADD2],  (instregex "^FADDPv.f(32|64)")>;
 764 def : InstRW<[M4WriteNMSC1],  (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>;
 765 def : InstRW<[M4WriteFCVT2],  (instregex "^FCVT(L|N|XN)v")>;
 766 def : InstRW<[M4WriteFCVT2A], (instregex "^FCVT[AMNPZ][SU]v")>;
 767 def : InstRW<[M4WriteFCVT2H], (instregex "^[SU]CVTFv.[fi]16")>;
 768 def : InstRW<[M4WriteFCVT2],  (instregex "^[SU]CVTFv.[fi](32|64)")>;
 769 def : InstRW<[M4WriteFDIV7H], (instrs FDIVv4f16)>;
 770 def : InstRW<[M4WriteNEONVH], (instrs FDIVv8f16)>;
 771 def : InstRW<[M4WriteFDIV7],  (instrs FDIVv2f32)>;
 772 def : InstRW<[M4WriteNEONV],  (instrs FDIVv4f32)>;
 773 def : InstRW<[M4WriteNEONW],  (instrs FDIVv2f64)>;
 774 def : InstRW<[M4WriteNMSC1],  (instregex "^F(MAX|MIN)(NM)?v")>;
 775 def : InstRW<[M4WriteNMSC2],  (instregex "^F(MAX|MIN)(NM)?Pv")>;
 776 def : InstRW<[M4WriteNEONZ],  (instregex "^F(MAX|MIN)(NM)?Vv")>;
 777 def : InstRW<[M4WriteFMAC2H], (instregex "^FMULX?v.[fi]16")>;
 778 def : InstRW<[M4WriteFMAC3],  (instregex "^FMULX?v.[fi](32|64)")>;
 779 def : InstRW<[M4WriteFMAC4H,
 780               M4ReadFMACM1],  (instregex "^FML[AS]v.[fi]16")>;
 781 def : InstRW<[M4WriteFMAC4,
 782               M4ReadFMACM1],  (instregex "^FML[AS]v.[fi](32|64)")>;
 783 def : InstRW<[M4WriteNALU1H], (instregex "^FNEGv.f16")>;
 784 def : InstRW<[M4WriteNALU1],  (instregex "^FNEGv.f(32|64)")>;
 785 def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
 786 def : InstRW<[M4WriteFSQR7H], (instrs FSQRTv4f16)>;
 787 def : InstRW<[M4WriteNEONXH], (instrs FSQRTv8f16)>;
 788 def : InstRW<[M4WriteFSQR8],  (instrs FSQRTv2f32)>;
 789 def : InstRW<[M4WriteNEONX],  (instrs FSQRTv4f32)>;
 790 def : InstRW<[M4WriteNEONY],  (instrs FSQRTv2f64)>;
 791
 792 // ASIMD miscellaneous instructions.
 793 def : InstRW<[M4WriteNALU1],  (instregex "^RBITv")>;
 794 def : InstRW<[M4WriteNALU1],  (instregex "^(BIF|BIT|BSL)v")>;
 795 def : InstRW<[M4WriteNALU1],  (instregex "^CL[STZ]v")>;
 796 def : InstRW<[M4WriteNEONB],  (instregex "^DUPv.+gpr")>;
 797 def : InstRW<[M4WriteNSHF1],  (instregex "^CPY")>;
 798 def : InstRW<[M4WriteNSHF1],  (instregex "^DUPv.+lane")>;
 799 def : InstRW<[M4WriteNSHF1],  (instregex "^EXTv")>;
 800 def : InstRW<[M4WriteNSHT4A], (instregex "^XTNv")>;
 801 def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]?QXTU?Nv")>;
 802 def : InstRW<[M4WriteNEONB],  (instregex "^INSv.+gpr")>;
 803 def : InstRW<[M4WriteNSHF1],  (instregex "^INSv.+lane")>;
 804 def : InstRW<[M4WriteMOVI],   (instregex "^(MOV|MVN)I")>;
 805 def : InstRW<[M4WriteNALU1H], (instregex "^FMOVv.f16")>;
 806 def : InstRW<[M4WriteNALU1],  (instregex "^FMOVv.f(32|64)")>;
 807 def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev[248]f16")>;
 808 def : InstRW<[M4WriteFCVT3],  (instregex "^F(RECP|RSQRT)Ev[248]f(32|64)")>;
 809 def : InstRW<[M4WriteFCVT3],  (instregex "^U(RECP|RSQRT)Ev[24]i32")>;
 810 def : InstRW<[M4WriteFMAC4H,
 811               M4ReadFMACM1],  (instregex "^F(RECP|RSQRT)Sv.f16")>;
 812 def : InstRW<[M4WriteFMAC4,
 813               M4ReadFMACM1],  (instregex "^F(RECP|RSQRT)Sv.f(32|64)")>;
 814 def : InstRW<[M4WriteNSHF1],  (instregex "^REV(16|32|64)v")>;
 815 def : InstRW<[M4WriteNSHFA],  (instregex "^TB[LX]v(8|16)i8One")>;
 816 def : InstRW<[M4WriteNSHFB],  (instregex "^TB[LX]v(8|16)i8Two")>;
 817 def : InstRW<[M4WriteNSHFC],  (instregex "^TB[LX]v(8|16)i8Three")>;
 818 def : InstRW<[M4WriteNSHFD],  (instregex "^TB[LX]v(8|16)i8Four")>;
 819 def : InstRW<[M4WriteNEONP],  (instregex "^[SU]MOVv")>;
 820 def : InstRW<[M4WriteNSHF1],  (instregex "^(TRN|UZP|ZIP)[12]v")>;
 821
 822 // ASIMD load instructions.
 823 def : InstRW<[WriteVLD],    (instregex "LD1Onev(8b|4h|2s|1d)$")>;
 824 def : InstRW<[WriteVLD,
 825               M4WriteA1],   (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>;
 826 def : InstRW<[WriteVLD],    (instregex "LD1Onev(16b|8h|4s|2d)$")>;
 827 def : InstRW<[WriteVLD,
 828               M4WriteA1],   (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>;
 829
 830 def : InstRW<[M4WriteVLDA], (instregex "LD1Twov(8b|4h|2s|1d)$")>;
 831 def : InstRW<[M4WriteVLDA,
 832               M4WriteA1],   (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>;
 833 def : InstRW<[M4WriteVLDA], (instregex "LD1Twov(16b|8h|4s|2d)$")>;
 834 def : InstRW<[M4WriteVLDA,
 835               M4WriteA1],   (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>;
 836
 837 def : InstRW<[M4WriteVLDB], (instregex "LD1Threev(8b|4h|2s|1d)$")>;
 838 def : InstRW<[M4WriteVLDB,
 839               M4WriteA1],   (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>;
 840 def : InstRW<[M4WriteVLDB], (instregex "LD1Threev(16b|8h|4s|2d)$")>;
 841 def : InstRW<[M4WriteVLDB,
 842               M4WriteA1],   (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>;
 843
 844 def : InstRW<[M4WriteVLDC], (instregex "LD1Fourv(8b|4h|2s|1d)$")>;
 845 def : InstRW<[M4WriteVLDC,
 846               M4WriteA1],   (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>;
 847 def : InstRW<[M4WriteVLDC], (instregex "LD1Fourv(16b|8h|4s|2d)$")>;
 848 def : InstRW<[M4WriteVLDC,
 849               M4WriteA1],   (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>;
 850
 851 def : InstRW<[M4WriteVLDD], (instregex "LD1i(8|16|32|64)$")>;
 852 def : InstRW<[M4WriteVLDD,
 853               M4WriteA1],   (instregex "LD1i(8|16|32|64)_POST$")>;
 854
 855 def : InstRW<[WriteVLD],    (instregex "LD1Rv(8b|4h|2s|1d)$")>;
 856 def : InstRW<[WriteVLD,
 857               M4WriteA1],   (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>;
 858 def : InstRW<[WriteVLD],    (instregex "LD1Rv(16b|8h|4s|2d)$")>;
 859 def : InstRW<[WriteVLD,
 860               M4WriteA1],   (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
 861
 862 def : InstRW<[M4WriteVLDF], (instregex "LD2Twov(8b|4h|2s)$")>;
 863 def : InstRW<[M4WriteVLDF,
 864               M4WriteA1],   (instregex "LD2Twov(8b|4h|2s)_POST$")>;
 865 def : InstRW<[M4WriteVLDF], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
 866 def : InstRW<[M4WriteVLDF,
 867               M4WriteA1],   (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>;
 868
 869 def : InstRW<[M4WriteVLDG], (instregex "LD2i(8|16|32|64)$")>;
 870 def : InstRW<[M4WriteVLDG,
 871               M4WriteA1],   (instregex "LD2i(8|16|32|64)_POST$")>;
 872
 873 def : InstRW<[M4WriteVLDA], (instregex "LD2Rv(8b|4h|2s|1d)$")>;
 874 def : InstRW<[M4WriteVLDA,
 875               M4WriteA1],   (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>;
 876 def : InstRW<[M4WriteVLDA], (instregex "LD2Rv(16b|8h|4s|2d)$")>;
 877 def : InstRW<[M4WriteVLDA,
 878               M4WriteA1],   (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
 879
 880 def : InstRW<[M4WriteVLDI], (instregex "LD3Threev(8b|4h|2s)$")>;
 881 def : InstRW<[M4WriteVLDI,
 882               M4WriteA1],   (instregex "LD3Threev(8b|4h|2s)_POST$")>;
 883 def : InstRW<[M4WriteVLDI], (instregex "LD3Threev(16b|8h|4s|2d)$")>;
 884 def : InstRW<[M4WriteVLDI,
 885               M4WriteA1],   (instregex "LD3Threev(16b|8h|4s|2d)_POST$")>;
 886
 887 def : InstRW<[M4WriteVLDJ], (instregex "LD3i(8|16|32)$")>;
 888 def : InstRW<[M4WriteVLDJ,
 889               M4WriteA1],   (instregex "LD3i(8|16|32)_POST$")>;
 890 def : InstRW<[M4WriteVLDL], (instregex "LD3i64$")>;
 891 def : InstRW<[M4WriteVLDL,
 892               M4WriteA1],   (instregex "LD3i64_POST$")>;
 893
 894 def : InstRW<[M4WriteVLDB], (instregex "LD3Rv(8b|4h|2s|1d)$")>;
 895 def : InstRW<[M4WriteVLDB,
 896               M4WriteA1],   (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>;
 897 def : InstRW<[M4WriteVLDB], (instregex "LD3Rv(16b|8h|4s|2d)$")>;
 898 def : InstRW<[M4WriteVLDB,
 899               M4WriteA1],   (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>;
 900
 901 def : InstRW<[M4WriteVLDN], (instregex "LD4Fourv(8b|4h|2s)$")>;
 902 def : InstRW<[M4WriteVLDN,
 903               M4WriteA1],   (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
 904 def : InstRW<[M4WriteVLDN], (instregex "LD4Fourv(16b|8h|4s|2d)$")>;
 905 def : InstRW<[M4WriteVLDN,
 906               M4WriteA1],   (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>;
 907
 908 def : InstRW<[M4WriteVLDK], (instregex "LD4i(8|16|32)$")>;
 909 def : InstRW<[M4WriteVLDK,
 910               M4WriteA1],   (instregex "LD4i(8|16|32)_POST$")>;
 911 def : InstRW<[M4WriteVLDM], (instregex "LD4i64$")>;
 912 def : InstRW<[M4WriteVLDM,
 913               M4WriteA1],   (instregex "LD4i64_POST$")>;
 914
 915 def : InstRW<[M4WriteVLDC], (instregex "LD4Rv(8b|4h|2s|1d)$")>;
 916 def : InstRW<[M4WriteVLDC,
 917               M4WriteA1],   (instregex "LD4Rv(8b|4h|2s|1d)_POST$")>;
 918 def : InstRW<[M4WriteVLDC], (instregex "LD4Rv(16b|8h|4s|2d)$")>;
 919 def : InstRW<[M4WriteVLDC,
 920               M4WriteA1],   (instregex "LD4Rv(16b|8h|4s|2d)_POST$")>;
 921
 922 // ASIMD store instructions.
 923 def : InstRW<[WriteVST],    (instregex "ST1Onev(8b|4h|2s|1d)$")>;
 924 def : InstRW<[WriteVST,
 925               M4WriteA1],   (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
 926 def : InstRW<[WriteVST],    (instregex "ST1Onev(16b|8h|4s|2d)$")>;
 927 def : InstRW<[WriteVST,
 928               M4WriteA1],   (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
 929
 930 def : InstRW<[M4WriteVSTA], (instregex "ST1Twov(8b|4h|2s|1d)$")>;
 931 def : InstRW<[M4WriteVSTA,
 932               M4WriteA1],   (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
 933 def : InstRW<[M4WriteVSTA], (instregex "ST1Twov(16b|8h|4s|2d)$")>;
 934 def : InstRW<[M4WriteVSTA,
 935               M4WriteA1],   (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
 936
 937 def : InstRW<[M4WriteVSTB], (instregex "ST1Threev(8b|4h|2s|1d)$")>;
 938 def : InstRW<[M4WriteVSTB,
 939               M4WriteA1],   (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
 940 def : InstRW<[M4WriteVSTB], (instregex "ST1Threev(16b|8h|4s|2d)$")>;
 941 def : InstRW<[M4WriteVSTB,
 942               M4WriteA1],   (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
 943
 944 def : InstRW<[M4WriteVSTC], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
 945 def : InstRW<[M4WriteVSTC,
 946               M4WriteA1],   (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
 947 def : InstRW<[M4WriteVSTC], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
 948 def : InstRW<[M4WriteVSTC,
 949               M4WriteA1],   (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
 950
 951 def : InstRW<[WriteVST],    (instregex "ST1i(8|16|32|64)$")>;
 952 def : InstRW<[WriteVST,
 953               M4WriteA1],   (instregex "ST1i(8|16|32|64)_POST$")>;
 954
 955 def : InstRW<[M4WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>;
 956 def : InstRW<[M4WriteVSTD,
 957               M4WriteA1],   (instregex "ST2Twov(8b|4h|2s)_POST$")>;
 958 def : InstRW<[M4WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
 959 def : InstRW<[M4WriteVSTE,
 960               M4WriteA1],   (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
 961
 962 def : InstRW<[M4WriteVSTD], (instregex "ST2i(8|16|32|64)$")>;
 963 def : InstRW<[M4WriteVSTD,
 964               M4WriteA1],   (instregex "ST2i(8|16|32|64)_POST$")>;
 965
 966 def : InstRW<[M4WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>;
 967 def : InstRW<[M4WriteVSTF,
 968               M4WriteA1],   (instregex "ST3Threev(8b|4h|2s)_POST$")>;
 969 def : InstRW<[M4WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>;
 970 def : InstRW<[M4WriteVSTG,
 971               M4WriteA1],   (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>;
 972
 973 def : InstRW<[M4WriteVSTE], (instregex "ST3i(8|16|32|64)$")>;
 974 def : InstRW<[M4WriteVSTE,
 975               M4WriteA1],   (instregex "ST3i(8|16|32|64)_POST$")>;
 976
 977 def : InstRW<[M4WriteVSTL], (instregex "ST4Fourv(8b|4h|2s)$")>;
 978 def : InstRW<[M4WriteVSTL,
 979               M4WriteA1],   (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
 980 def : InstRW<[M4WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>;
 981 def : InstRW<[M4WriteVSTI,
 982               M4WriteA1],   (instregex "ST4Fourv(16b|8h|4s|2d)_POST$")>;
 983
 984 def : InstRW<[M4WriteVSTE], (instregex "ST4i(8|16|32|64)$")>;
 985 def : InstRW<[M4WriteVSTE,
 986               M4WriteA1],   (instregex "ST4i(8|16|32|64)_POST$")>;
 987
 988 // Cryptography instructions.
 989 def : InstRW<[M4WriteNCRY1],  (instregex "^AES[DE]")>;
 990 def : InstRW<[M4WriteNCRY1,
 991               M4ReadAESM1],   (instregex "^AESI?MC")>;
 992 def : InstRW<[M4WriteNCRY1A], (instregex "^PMULv")>;
 993 def : InstRW<[M4WriteNCRY1A], (instregex "^PMULLv(1|8)i")>;
 994 def : InstRW<[M4WriteNCRY3A], (instregex "^PMULLv(2|16)i")>;
 995 def : InstRW<[M4WriteNCRY1A], (instregex "^SHA1([CHMP]|SU[01])")>;
 996 def : InstRW<[M4WriteNCRY1A], (instrs SHA256SU0rr)>;
 997 def : InstRW<[M4WriteNCRY5A], (instrs SHA256SU1rrr)>;
 998 def : InstRW<[M4WriteNCRY5A], (instrs SHA256H2rrr)>;
 999
1000 // CRC instructions.
1001 def : InstRW<[M4WriteE2], (instregex "^CRC32C?[BHWX]rr$")>;
1002
1003 } // SchedModel = ExynosM4Model