lib/Target/AMDGPU/AMDGPU.td

   1 //===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===------------------------------------------------------------===//
   8
   9 include "llvm/TableGen/SearchableTable.td"
  10 include "llvm/Target/Target.td"
  11 include "AMDGPUFeatures.td"
  12
  13 class BoolToList<bit Value> {
  14   list<int> ret = !if(Value, [1]<int>, []<int>);
  15 }
  16
  17 //===------------------------------------------------------------===//
  18 // Subtarget Features (device properties)
  19 //===------------------------------------------------------------===//
  20
  21 def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
  22   "FastFMAF32",
  23   "true",
  24   "Assuming f32 fma is at least as fast as mul + add"
  25 >;
  26
  27 def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
  28   "MIMG_R128",
  29   "true",
  30   "Support 128-bit texture resources"
  31 >;
  32
  33 def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
  34   "HalfRate64Ops",
  35   "true",
  36   "Most fp64 instructions are half rate instead of quarter"
  37 >;
  38
  39 def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
  40   "FlatAddressSpace",
  41   "true",
  42   "Support flat address space"
  43 >;
  44
  45 def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
  46   "FlatInstOffsets",
  47   "true",
  48   "Flat instructions have immediate offset addressing mode"
  49 >;
  50
  51 def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
  52   "FlatGlobalInsts",
  53   "true",
  54   "Have global_* flat memory instructions"
  55 >;
  56
  57 def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
  58   "FlatScratchInsts",
  59   "true",
  60   "Have scratch_* flat memory instructions"
  61 >;
  62
  63 def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
  64   "AddNoCarryInsts",
  65   "true",
  66   "Have VALU add/sub instructions without carry out"
  67 >;
  68
  69 def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
  70   "UnalignedBufferAccess",
  71   "true",
  72   "Support unaligned global loads and stores"
  73 >;
  74
  75 def FeatureTrapHandler: SubtargetFeature<"trap-handler",
  76   "TrapHandler",
  77   "true",
  78   "Trap handler support"
  79 >;
  80
  81 def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
  82   "UnalignedScratchAccess",
  83   "true",
  84   "Support unaligned scratch loads and stores"
  85 >;
  86
  87 def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
  88   "HasApertureRegs",
  89   "true",
  90   "Has Memory Aperture Base and Size Registers"
  91 >;
  92
  93 def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
  94   "HasMadMixInsts",
  95   "true",
  96   "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
  97 >;
  98
  99 def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
 100   "HasFmaMixInsts",
 101   "true",
 102   "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
 103 >;
 104
 105 // XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
 106 // XNACK. The current default kernel driver setting is:
 107 // - graphics ring: XNACK disabled
 108 // - compute ring: XNACK enabled
 109 //
 110 // If XNACK is enabled, the VMEM latency can be worse.
 111 // If XNACK is disabled, the 2 SGPRs can be used for general purposes.
 112 def FeatureXNACK : SubtargetFeature<"xnack",
 113   "EnableXNACK",
 114   "true",
 115   "Enable XNACK support"
 116 >;
 117
 118 def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
 119   "SGPRInitBug",
 120   "true",
 121   "VI SGPR initialization bug requiring a fixed SGPR allocation size"
 122 >;
 123
 124 class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
 125   "ldsbankcount"#Value,
 126   "LDSBankCount",
 127   !cast<string>(Value),
 128   "The number of LDS banks per compute unit."
 129 >;
 130
 131 def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
 132 def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
 133
 134 def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
 135   "GCN3Encoding",
 136   "true",
 137   "Encoding format for VI"
 138 >;
 139
 140 def FeatureCIInsts : SubtargetFeature<"ci-insts",
 141   "CIInsts",
 142   "true",
 143   "Additional instructions for CI+"
 144 >;
 145
 146 def FeatureVIInsts : SubtargetFeature<"vi-insts",
 147   "VIInsts",
 148   "true",
 149   "Additional instructions for VI+"
 150 >;
 151
 152 def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
 153   "GFX9Insts",
 154   "true",
 155   "Additional instructions for GFX9+"
 156 >;
 157
 158 def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
 159   "HasSMemRealTime",
 160   "true",
 161   "Has s_memrealtime instruction"
 162 >;
 163
 164 def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
 165   "HasInv2PiInlineImm",
 166   "true",
 167   "Has 1 / (2 * pi) as inline immediate"
 168 >;
 169
 170 def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
 171   "Has16BitInsts",
 172   "true",
 173   "Has i16/f16 instructions"
 174 >;
 175
 176 def FeatureVOP3P : SubtargetFeature<"vop3p",
 177   "HasVOP3PInsts",
 178   "true",
 179   "Has VOP3P packed instructions"
 180 >;
 181
 182 def FeatureMovrel : SubtargetFeature<"movrel",
 183   "HasMovrel",
 184   "true",
 185   "Has v_movrel*_b32 instructions"
 186 >;
 187
 188 def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
 189   "HasVGPRIndexMode",
 190   "true",
 191   "Has VGPR mode register indexing"
 192 >;
 193
 194 def FeatureScalarStores : SubtargetFeature<"scalar-stores",
 195   "HasScalarStores",
 196   "true",
 197   "Has store scalar memory instructions"
 198 >;
 199
 200 def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
 201   "HasScalarAtomics",
 202   "true",
 203   "Has atomic scalar memory instructions"
 204 >;
 205
 206 def FeatureSDWA : SubtargetFeature<"sdwa",
 207   "HasSDWA",
 208   "true",
 209   "Support SDWA (Sub-DWORD Addressing) extension"
 210 >;
 211
 212 def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
 213   "HasSDWAOmod",
 214   "true",
 215   "Support OMod with SDWA (Sub-DWORD Addressing) extension"
 216 >;
 217
 218 def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
 219   "HasSDWAScalar",
 220   "true",
 221   "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
 222 >;
 223
 224 def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
 225   "HasSDWASdst",
 226   "true",
 227   "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
 228 >;
 229
 230 def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
 231   "HasSDWAMac",
 232   "true",
 233   "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
 234 >;
 235
 236 def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
 237   "HasSDWAOutModsVOPC",
 238   "true",
 239   "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
 240 >;
 241
 242 def FeatureDPP : SubtargetFeature<"dpp",
 243   "HasDPP",
 244   "true",
 245   "Support DPP (Data Parallel Primitives) extension"
 246 >;
 247
 248 def FeatureR128A16 : SubtargetFeature<"r128-a16",
 249   "HasR128A16",
 250   "true",
 251   "Support 16 bit coordindates/gradients/lod/clamp/mip types on gfx9"
 252 >;
 253
 254 def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
 255   "HasIntClamp",
 256   "true",
 257   "Support clamp for integer destination"
 258 >;
 259
 260 def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
 261   "HasUnpackedD16VMem",
 262   "true",
 263   "Has unpacked d16 vmem instructions"
 264 >;
 265
 266 def FeatureDLInsts : SubtargetFeature<"dl-insts",
 267   "HasDLInsts",
 268   "true",
 269   "Has v_fmac_f32 and v_xnor_b32 instructions"
 270 >;
 271
 272 def FeatureDot1Insts : SubtargetFeature<"dot1-insts",
 273   "HasDot1Insts",
 274   "true",
 275   "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions"
 276 >;
 277
 278 def FeatureDot2Insts : SubtargetFeature<"dot2-insts",
 279   "HasDot2Insts",
 280   "true",
 281   "Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions"
 282 >;
 283
 284 def FeatureSRAMECC : SubtargetFeature<"sram-ecc",
 285   "EnableSRAMECC",
 286   "true",
 287   "Enable SRAM ECC"
 288 >;
 289
 290 //===------------------------------------------------------------===//
 291 // Subtarget Features (options and debugging)
 292 //===------------------------------------------------------------===//
 293
 294 // Denormal handling for fp64 and fp16 is controlled by the same
 295 // config register when fp16 supported.
 296 // TODO: Do we need a separate f16 setting when not legal?
 297 def FeatureFP64FP16Denormals : SubtargetFeature<"fp64-fp16-denormals",
 298   "FP64FP16Denormals",
 299   "true",
 300   "Enable double and half precision denormal handling",
 301   [FeatureFP64]
 302 >;
 303
 304 def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
 305   "FP64FP16Denormals",
 306   "true",
 307   "Enable double and half precision denormal handling",
 308   [FeatureFP64, FeatureFP64FP16Denormals]
 309 >;
 310
 311 def FeatureFP16Denormals : SubtargetFeature<"fp16-denormals",
 312   "FP64FP16Denormals",
 313   "true",
 314   "Enable half precision denormal handling",
 315   [FeatureFP64FP16Denormals]
 316 >;
 317
 318 def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
 319   "FPExceptions",
 320   "true",
 321   "Enable floating point exceptions"
 322 >;
 323
 324 class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
 325   "max-private-element-size-"#size,
 326   "MaxPrivateElementSize",
 327   !cast<string>(size),
 328   "Maximum private access size may be "#size
 329 >;
 330
 331 def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
 332 def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
 333 def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
 334
 335 def FeatureEnableHugePrivateBuffer : SubtargetFeature<
 336   "huge-private-buffer",
 337   "EnableHugePrivateBuffer",
 338   "true",
 339   "Enable private/scratch buffer sizes greater than 128 GB"
 340 >;
 341
 342 def FeatureDumpCode : SubtargetFeature <"DumpCode",
 343   "DumpCode",
 344   "true",
 345   "Dump MachineInstrs in the CodeEmitter"
 346 >;
 347
 348 def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
 349   "DumpCode",
 350   "true",
 351   "Dump MachineInstrs in the CodeEmitter"
 352 >;
 353
 354 // XXX - This should probably be removed once enabled by default
 355 def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
 356   "EnableLoadStoreOpt",
 357   "true",
 358   "Enable SI load/store optimizer pass"
 359 >;
 360
 361 // Performance debugging feature. Allow using DS instruction immediate
 362 // offsets even if the base pointer can't be proven to be base. On SI,
 363 // base pointer values that won't give the same result as a 16-bit add
 364 // are not safe to fold, but this will override the conservative test
 365 // for the base pointer.
 366 def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
 367   "unsafe-ds-offset-folding",
 368   "EnableUnsafeDSOffsetFolding",
 369   "true",
 370   "Force using DS instruction immediate offsets on SI"
 371 >;
 372
 373 def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
 374   "EnableSIScheduler",
 375   "true",
 376   "Enable SI Machine Scheduler"
 377 >;
 378
 379 def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
 380   "EnableDS128",
 381   "true",
 382   "Use ds_{read|write}_b128"
 383 >;
 384
 385 // Sparse texture support requires that all result registers are zeroed when
 386 // PRTStrictNull is set to true. This feature is turned on for all architectures
 387 // but is enabled as a feature in case there are situations where PRTStrictNull
 388 // is disabled by the driver.
 389 def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
 390   "EnablePRTStrictNull",
 391   "true",
 392   "Enable zeroing of result registers for sparse texture fetches"
 393 >;
 394
 395 // Unless +-flat-for-global is specified, turn on FlatForGlobal for
 396 // all OS-es on VI and newer hardware to avoid assertion failures due
 397 // to missing ADDR64 variants of MUBUF instructions.
 398 // FIXME: moveToVALU should be able to handle converting addr64 MUBUF
 399 // instructions.
 400
 401 def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
 402   "FlatForGlobal",
 403   "true",
 404   "Force to generate flat instruction for global"
 405 >;
 406
 407 def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
 408   "auto-waitcnt-before-barrier",
 409   "AutoWaitcntBeforeBarrier",
 410   "true",
 411   "Hardware automatically inserts waitcnt before barrier"
 412 >;
 413
 414 def FeatureCodeObjectV3 : SubtargetFeature <
 415   "code-object-v3",
 416   "CodeObjectV3",
 417   "true",
 418   "Generate code object version 3"
 419 >;
 420
 421 def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
 422   "HasTrigReducedRange",
 423   "true",
 424   "Requires use of fract on arguments to trig instructions"
 425 >;
 426
 427 // Dummy feature used to disable assembler instructions.
 428 def FeatureDisable : SubtargetFeature<"",
 429   "FeatureDisable","true",
 430   "Dummy feature to disable assembler instructions"
 431 >;
 432
 433 class GCNSubtargetFeatureGeneration <string Value,
 434                                   list<SubtargetFeature> Implies> :
 435         SubtargetFeatureGeneration <Value, "GCNSubtarget", Implies>;
 436
 437 def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
 438   [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
 439   FeatureWavefrontSize64,
 440   FeatureLDSBankCount32, FeatureMovrel, FeatureTrigReducedRange]
 441 >;
 442
 443 def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
 444   [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
 445   FeatureWavefrontSize64, FeatureFlatAddressSpace,
 446   FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange]
 447 >;
 448
 449 def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
 450   [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
 451    FeatureWavefrontSize64, FeatureFlatAddressSpace,
 452    FeatureGCN3Encoding, FeatureCIInsts, FeatureVIInsts, Feature16BitInsts,
 453    FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
 454    FeatureScalarStores, FeatureInv2PiInlineImm,
 455    FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
 456    FeatureIntClamp, FeatureTrigReducedRange
 457   ]
 458 >;
 459
 460 def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
 461   [FeatureFP64, FeatureLocalMemorySize65536,
 462    FeatureWavefrontSize64, FeatureFlatAddressSpace,
 463    FeatureGCN3Encoding, FeatureCIInsts, FeatureVIInsts, Feature16BitInsts,
 464    FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
 465    FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
 466    FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
 467    FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
 468    FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
 469    FeatureAddNoCarryInsts, FeatureScalarAtomics, FeatureR128A16
 470   ]
 471 >;
 472
 473 class FeatureSet<list<SubtargetFeature> Features_> {
 474   list<SubtargetFeature> Features = Features_;
 475 }
 476
 477 def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
 478    FeatureFastFMAF32,
 479    HalfRate64Ops,
 480    FeatureLDSBankCount32,
 481    FeatureCodeObjectV3]>;
 482
 483 def FeatureISAVersion6_0_1 : FeatureSet<
 484   [FeatureSouthernIslands,
 485    FeatureLDSBankCount32,
 486    FeatureCodeObjectV3]>;
 487
 488 def FeatureISAVersion7_0_0 : FeatureSet<
 489   [FeatureSeaIslands,
 490    FeatureLDSBankCount32,
 491    FeatureCodeObjectV3]>;
 492
 493 def FeatureISAVersion7_0_1 : FeatureSet<
 494   [FeatureSeaIslands,
 495    HalfRate64Ops,
 496    FeatureLDSBankCount32,
 497    FeatureFastFMAF32,
 498    FeatureCodeObjectV3]>;
 499
 500 def FeatureISAVersion7_0_2 : FeatureSet<
 501   [FeatureSeaIslands,
 502    FeatureLDSBankCount16,
 503    FeatureFastFMAF32,
 504    FeatureCodeObjectV3]>;
 505
 506 def FeatureISAVersion7_0_3 : FeatureSet<
 507   [FeatureSeaIslands,
 508    FeatureLDSBankCount16,
 509    FeatureCodeObjectV3]>;
 510
 511 def FeatureISAVersion7_0_4 : FeatureSet<
 512   [FeatureSeaIslands,
 513    FeatureLDSBankCount32,
 514    FeatureCodeObjectV3]>;
 515
 516 def FeatureISAVersion8_0_1 : FeatureSet<
 517   [FeatureVolcanicIslands,
 518    FeatureFastFMAF32,
 519    HalfRate64Ops,
 520    FeatureLDSBankCount32,
 521    FeatureXNACK,
 522    FeatureUnpackedD16VMem,
 523    FeatureCodeObjectV3]>;
 524
 525 def FeatureISAVersion8_0_2 : FeatureSet<
 526   [FeatureVolcanicIslands,
 527    FeatureLDSBankCount32,
 528    FeatureSGPRInitBug,
 529    FeatureUnpackedD16VMem,
 530    FeatureCodeObjectV3]>;
 531
 532 def FeatureISAVersion8_0_3 : FeatureSet<
 533   [FeatureVolcanicIslands,
 534    FeatureLDSBankCount32,
 535    FeatureUnpackedD16VMem,
 536    FeatureCodeObjectV3]>;
 537
 538 def FeatureISAVersion8_1_0 : FeatureSet<
 539   [FeatureVolcanicIslands,
 540    FeatureLDSBankCount16,
 541    FeatureXNACK,
 542    FeatureCodeObjectV3]>;
 543
 544 def FeatureISAVersion9_0_0 : FeatureSet<
 545   [FeatureGFX9,
 546    FeatureMadMixInsts,
 547    FeatureLDSBankCount32,
 548    FeatureCodeObjectV3]>;
 549
 550 def FeatureISAVersion9_0_2 : FeatureSet<
 551   [FeatureGFX9,
 552    FeatureMadMixInsts,
 553    FeatureLDSBankCount32,
 554    FeatureXNACK,
 555    FeatureCodeObjectV3]>;
 556
 557 def FeatureISAVersion9_0_4 : FeatureSet<
 558   [FeatureGFX9,
 559    FeatureLDSBankCount32,
 560    FeatureFmaMixInsts,
 561    FeatureCodeObjectV3]>;
 562
 563 def FeatureISAVersion9_0_6 : FeatureSet<
 564   [FeatureGFX9,
 565    HalfRate64Ops,
 566    FeatureFmaMixInsts,
 567    FeatureLDSBankCount32,
 568    FeatureDLInsts,
 569    FeatureDot1Insts,
 570    FeatureDot2Insts,
 571    FeatureSRAMECC,
 572    FeatureCodeObjectV3]>;
 573
 574 def FeatureISAVersion9_0_9 : FeatureSet<
 575   [FeatureGFX9,
 576    FeatureMadMixInsts,
 577    FeatureLDSBankCount32,
 578    FeatureXNACK,
 579    FeatureCodeObjectV3]>;
 580
 581 //===----------------------------------------------------------------------===//
 582 // Debugger related subtarget features.
 583 //===----------------------------------------------------------------------===//
 584
 585 def FeatureDebuggerInsertNops : SubtargetFeature<
 586   "amdgpu-debugger-insert-nops",
 587   "DebuggerInsertNops",
 588   "true",
 589   "Insert one nop instruction for each high level source statement"
 590 >;
 591
 592 def FeatureDebuggerEmitPrologue : SubtargetFeature<
 593   "amdgpu-debugger-emit-prologue",
 594   "DebuggerEmitPrologue",
 595   "true",
 596   "Emit debugger prologue"
 597 >;
 598
 599 //===----------------------------------------------------------------------===//
 600
 601 def AMDGPUInstrInfo : InstrInfo {
 602   let guessInstructionProperties = 1;
 603   let noNamedPositionallyEncodedOperands = 1;
 604 }
 605
 606 def AMDGPUAsmParser : AsmParser {
 607   // Some of the R600 registers have the same name, so this crashes.
 608   // For example T0_XYZW and T0_XY both have the asm name T0.
 609   let ShouldEmitMatchRegisterName = 0;
 610 }
 611
 612 def AMDGPUAsmWriter : AsmWriter {
 613   int PassSubtarget = 1;
 614 }
 615
 616 def AMDGPUAsmVariants {
 617   string Default = "Default";
 618   int Default_ID = 0;
 619   string VOP3 = "VOP3";
 620   int VOP3_ID = 1;
 621   string SDWA = "SDWA";
 622   int SDWA_ID = 2;
 623   string SDWA9 = "SDWA9";
 624   int SDWA9_ID = 3;
 625   string DPP = "DPP";
 626   int DPP_ID = 4;
 627   string Disable = "Disable";
 628   int Disable_ID = 5;
 629 }
 630
 631 def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
 632   let Variant = AMDGPUAsmVariants.Default_ID;
 633   let Name = AMDGPUAsmVariants.Default;
 634 }
 635
 636 def VOP3AsmParserVariant : AsmParserVariant {
 637   let Variant = AMDGPUAsmVariants.VOP3_ID;
 638   let Name = AMDGPUAsmVariants.VOP3;
 639 }
 640
 641 def SDWAAsmParserVariant : AsmParserVariant {
 642   let Variant = AMDGPUAsmVariants.SDWA_ID;
 643   let Name = AMDGPUAsmVariants.SDWA;
 644 }
 645
 646 def SDWA9AsmParserVariant : AsmParserVariant {
 647   let Variant = AMDGPUAsmVariants.SDWA9_ID;
 648   let Name = AMDGPUAsmVariants.SDWA9;
 649 }
 650
 651
 652 def DPPAsmParserVariant : AsmParserVariant {
 653   let Variant = AMDGPUAsmVariants.DPP_ID;
 654   let Name = AMDGPUAsmVariants.DPP;
 655 }
 656
 657 def AMDGPU : Target {
 658   // Pull in Instruction Info:
 659   let InstructionSet = AMDGPUInstrInfo;
 660   let AssemblyParsers = [AMDGPUAsmParser];
 661   let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
 662                                 VOP3AsmParserVariant,
 663                                 SDWAAsmParserVariant,
 664                                 SDWA9AsmParserVariant,
 665                                 DPPAsmParserVariant];
 666   let AssemblyWriters = [AMDGPUAsmWriter];
 667   let AllowRegisterRenaming = 1;
 668 }
 669
 670 // Dummy Instruction itineraries for pseudo instructions
 671 def ALU_NULL : FuncUnit;
 672 def NullALU : InstrItinClass;
 673
 674 //===----------------------------------------------------------------------===//
 675 // Predicate helper class
 676 //===----------------------------------------------------------------------===//
 677
 678 def isSICI : Predicate<
 679   "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
 680   "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
 681 >, AssemblerPredicate<"!FeatureGCN3Encoding">;
 682
 683 def isVI : Predicate <
 684   "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
 685   AssemblerPredicate<"FeatureGCN3Encoding">;
 686
 687 def isGFX9 : Predicate <
 688   "Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
 689   AssemblerPredicate<"FeatureGFX9Insts">;
 690
 691 // TODO: Either the name to be changed or we simply use IsCI!
 692 def isCIVI : Predicate <
 693   "Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
 694   AssemblerPredicate<"FeatureCIInsts">;
 695
 696 def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
 697   AssemblerPredicate<"FeatureFlatAddressSpace">;
 698
 699 def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
 700   AssemblerPredicate<"FeatureFlatGlobalInsts">;
 701 def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
 702   AssemblerPredicate<"FeatureFlatScratchInsts">;
 703 def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
 704   AssemblerPredicate<"FeatureGFX9Insts">;
 705
 706 def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
 707   AssemblerPredicate<"FeatureUnpackedD16VMem">;
 708 def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
 709   AssemblerPredicate<"!FeatureUnpackedD16VMem">;
 710
 711 def D16PreservesUnusedBits :
 712   Predicate<"Subtarget->hasD16LoadStore() && !Subtarget->isSRAMECCEnabled()">,
 713   AssemblerPredicate<"FeatureGFX9Insts,!FeatureSRAMECC">;
 714
 715 def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
 716 def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
 717
 718 def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
 719   AssemblerPredicate<"FeatureGFX9Insts">;
 720
 721 def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
 722   AssemblerPredicate<"FeatureAddNoCarryInsts">;
 723
 724 def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">,
 725   AssemblerPredicate<"!FeatureAddNoCarryInsts">;
 726
 727 def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
 728   AssemblerPredicate<"Feature16BitInsts">;
 729 def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
 730   AssemblerPredicate<"FeatureVOP3P">;
 731
 732 def NotHasVOP3PInsts : Predicate<"!Subtarget->hasVOP3PInsts()">,
 733   AssemblerPredicate<"!FeatureVOP3P">;
 734
 735 def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
 736   AssemblerPredicate<"FeatureSDWA,FeatureVolcanicIslands">;
 737
 738 def HasSDWA9 : Predicate<"Subtarget->hasSDWA()">,
 739   AssemblerPredicate<"FeatureSDWA,FeatureGFX9">;
 740
 741 def HasDPP : Predicate<"Subtarget->hasDPP()">,
 742   AssemblerPredicate<"FeatureDPP">;
 743
 744 def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
 745   AssemblerPredicate<"FeatureR128A16">;
 746
 747 def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
 748   AssemblerPredicate<"FeatureIntClamp">;
 749
 750 def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
 751   AssemblerPredicate<"FeatureMadMixInsts">;
 752
 753 def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
 754   AssemblerPredicate<"FeatureScalarAtomics">;
 755
 756 def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
 757 def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
 758 def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
 759                       AssemblerPredicate<"FeatureVGPRIndexMode">;
 760 def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
 761                 AssemblerPredicate<"FeatureMovrel">;
 762
 763 def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
 764   AssemblerPredicate<"FeatureFmaMixInsts">;
 765
 766 def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
 767   AssemblerPredicate<"FeatureDLInsts">;
 768
 769 def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">,
 770   AssemblerPredicate<"FeatureDot1Insts">;
 771
 772 def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">,
 773   AssemblerPredicate<"FeatureDot2Insts">;
 774
 775
 776 def EnableLateCFGStructurize : Predicate<
 777   "EnableLateStructurizeCFG">;
 778
 779 // Include AMDGPU TD files
 780 include "SISchedule.td"
 781 include "GCNProcessors.td"
 782 include "AMDGPUInstrInfo.td"
 783 include "AMDGPURegisterInfo.td"
 784 include "AMDGPURegisterBanks.td"
 785 include "AMDGPUInstructions.td"
 786 include "SIInstrInfo.td"
 787 include "AMDGPUCallingConv.td"
 788 include "AMDGPUSearchableTables.td"