lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

   1 //===- AMDGPURegisterBankInfo.cpp -------------------------------*- C++ -*-==//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 /// \file
   9 /// This file implements the targeting of the RegisterBankInfo class for
  10 /// AMDGPU.
  11 /// \todo This should be generated by TableGen.
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "AMDGPURegisterBankInfo.h"
  15 #include "AMDGPUInstrInfo.h"
  16 #include "SIMachineFunctionInfo.h"
  17 #include "SIRegisterInfo.h"
  18 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
  19 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
  20 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
  21 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
  22 #include "llvm/CodeGen/TargetRegisterInfo.h"
  23 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  24 #include "llvm/IR/Constants.h"
  25
  26 #define GET_TARGET_REGBANK_IMPL
  27 #include "AMDGPUGenRegisterBank.inc"
  28
  29 // This file will be TableGen'ed at some point.
  30 #include "AMDGPUGenRegisterBankInfo.def"
  31
  32 using namespace llvm;
  33
  34 AMDGPURegisterBankInfo::AMDGPURegisterBankInfo(const TargetRegisterInfo &TRI)
  35     : AMDGPUGenRegisterBankInfo(),
  36       TRI(static_cast<const SIRegisterInfo*>(&TRI)) {
  37
  38   // HACK: Until this is fully tablegen'd.
  39   static bool AlreadyInit = false;
  40   if (AlreadyInit)
  41     return;
  42
  43   AlreadyInit = true;
  44
  45   const RegisterBank &RBSGPR = getRegBank(AMDGPU::SGPRRegBankID);
  46   (void)RBSGPR;
  47   assert(&RBSGPR == &AMDGPU::SGPRRegBank);
  48
  49   const RegisterBank &RBVGPR = getRegBank(AMDGPU::VGPRRegBankID);
  50   (void)RBVGPR;
  51   assert(&RBVGPR == &AMDGPU::VGPRRegBank);
  52
  53 }
  54
  55 static bool isConstant(const MachineOperand &MO, int64_t &C) {
  56   const MachineFunction *MF = MO.getParent()->getParent()->getParent();
  57   const MachineRegisterInfo &MRI = MF->getRegInfo();
  58   const MachineInstr *Def = MRI.getVRegDef(MO.getReg());
  59   if (!Def)
  60     return false;
  61
  62   if (Def->getOpcode() == AMDGPU::G_CONSTANT) {
  63     C = Def->getOperand(1).getCImm()->getSExtValue();
  64     return true;
  65   }
  66
  67   if (Def->getOpcode() == AMDGPU::COPY)
  68     return isConstant(Def->getOperand(1), C);
  69
  70   return false;
  71 }
  72
  73 unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst,
  74                                           const RegisterBank &Src,
  75                                           unsigned Size) const {
  76   if (Dst.getID() == AMDGPU::SGPRRegBankID &&
  77       Src.getID() == AMDGPU::VGPRRegBankID) {
  78     return std::numeric_limits<unsigned>::max();
  79   }
  80
  81   // SGPRRegBank with size 1 is actually vcc or another 64-bit sgpr written by
  82   // the valu.
  83   if (Size == 1 && Dst.getID() == AMDGPU::SCCRegBankID &&
  84       (Src.getID() == AMDGPU::SGPRRegBankID ||
  85        Src.getID() == AMDGPU::VGPRRegBankID ||
  86        Src.getID() == AMDGPU::VCCRegBankID))
  87     return std::numeric_limits<unsigned>::max();
  88
  89   if (Dst.getID() == AMDGPU::SCCRegBankID &&
  90       Src.getID() == AMDGPU::VCCRegBankID)
  91     return std::numeric_limits<unsigned>::max();
  92
  93   return RegisterBankInfo::copyCost(Dst, Src, Size);
  94 }
  95
  96 unsigned AMDGPURegisterBankInfo::getBreakDownCost(
  97   const ValueMapping &ValMapping,
  98   const RegisterBank *CurBank) const {
  99   assert(ValMapping.NumBreakDowns == 2 &&
 100          ValMapping.BreakDown[0].Length == 32 &&
 101          ValMapping.BreakDown[0].StartIdx == 0 &&
 102          ValMapping.BreakDown[1].Length == 32 &&
 103          ValMapping.BreakDown[1].StartIdx == 32 &&
 104          ValMapping.BreakDown[0].RegBank == ValMapping.BreakDown[1].RegBank);
 105
 106   // 32-bit extract of a 64-bit value is just access of a subregister, so free.
 107   // TODO: Cost of 0 hits assert, though it's not clear it's what we really
 108   // want.
 109
 110   // TODO: 32-bit insert to a 64-bit SGPR may incur a non-free copy due to SGPR
 111   // alignment restrictions, but this probably isn't important.
 112   return 1;
 113 }
 114
 115 const RegisterBank &AMDGPURegisterBankInfo::getRegBankFromRegClass(
 116     const TargetRegisterClass &RC) const {
 117
 118   if (TRI->isSGPRClass(&RC))
 119     return getRegBank(AMDGPU::SGPRRegBankID);
 120
 121   return getRegBank(AMDGPU::VGPRRegBankID);
 122 }
 123
 124 RegisterBankInfo::InstructionMappings
 125 AMDGPURegisterBankInfo::getInstrAlternativeMappings(
 126     const MachineInstr &MI) const {
 127
 128   const MachineFunction &MF = *MI.getParent()->getParent();
 129   const MachineRegisterInfo &MRI = MF.getRegInfo();
 130
 131
 132   InstructionMappings AltMappings;
 133   switch (MI.getOpcode()) {
 134   case TargetOpcode::G_AND:
 135   case TargetOpcode::G_OR:
 136   case TargetOpcode::G_XOR: {
 137     unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
 138     if (Size != 64)
 139       break;
 140
 141     const InstructionMapping &SSMapping = getInstructionMapping(
 142       1, 1, getOperandsMapping(
 143         {AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
 144          AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
 145          AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
 146       3); // Num Operands
 147     AltMappings.push_back(&SSMapping);
 148
 149     const InstructionMapping &VVMapping = getInstructionMapping(
 150       2, 2, getOperandsMapping(
 151         {AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size),
 152          AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size),
 153          AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size)}),
 154       3); // Num Operands
 155     AltMappings.push_back(&VVMapping);
 156
 157     const InstructionMapping &SVMapping = getInstructionMapping(
 158       3, 3, getOperandsMapping(
 159         {AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size),
 160          AMDGPU::getValueMappingSGPR64Only(AMDGPU::SGPRRegBankID, Size),
 161          AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size)}),
 162       3); // Num Operands
 163     AltMappings.push_back(&SVMapping);
 164
 165     // SGPR in LHS is slightly preferrable, so make it VS more expnesive than
 166     // SV.
 167     const InstructionMapping &VSMapping = getInstructionMapping(
 168       3, 4, getOperandsMapping(
 169         {AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size),
 170          AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size),
 171          AMDGPU::getValueMappingSGPR64Only(AMDGPU::SGPRRegBankID, Size)}),
 172       3); // Num Operands
 173     AltMappings.push_back(&VSMapping);
 174     break;
 175   }
 176   case TargetOpcode::G_LOAD: {
 177     unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
 178     // FIXME: Should we be hard coding the size for these mappings?
 179     const InstructionMapping &SSMapping = getInstructionMapping(
 180         1, 1, getOperandsMapping(
 181                   {AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
 182                    AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 64)}),
 183         2); // Num Operands
 184     AltMappings.push_back(&SSMapping);
 185
 186     const InstructionMapping &VVMapping = getInstructionMapping(
 187         2, 1, getOperandsMapping(
 188                   {AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
 189                    AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 64)}),
 190         2); // Num Operands
 191     AltMappings.push_back(&VVMapping);
 192
 193     // FIXME: Should this be the pointer-size (64-bits) or the size of the
 194     // register that will hold the bufffer resourc (128-bits).
 195     const InstructionMapping &VSMapping = getInstructionMapping(
 196         3, 1, getOperandsMapping(
 197                   {AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
 198                    AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 64)}),
 199         2); // Num Operands
 200     AltMappings.push_back(&VSMapping);
 201
 202     return AltMappings;
 203
 204   }
 205   case TargetOpcode::G_ICMP: {
 206     unsigned Size = getSizeInBits(MI.getOperand(2).getReg(), MRI, *TRI);
 207     const InstructionMapping &SSMapping = getInstructionMapping(1, 1,
 208       getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1),
 209                           nullptr, // Predicate operand.
 210                           AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
 211                           AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
 212       4); // Num Operands
 213     AltMappings.push_back(&SSMapping);
 214
 215     const InstructionMapping &SVMapping = getInstructionMapping(2, 1,
 216       getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1),
 217                           nullptr, // Predicate operand.
 218                           AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
 219                           AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}),
 220       4); // Num Operands
 221     AltMappings.push_back(&SVMapping);
 222
 223     const InstructionMapping &VSMapping = getInstructionMapping(3, 1,
 224       getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1),
 225                           nullptr, // Predicate operand.
 226                           AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
 227                           AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
 228       4); // Num Operands
 229     AltMappings.push_back(&VSMapping);
 230
 231     const InstructionMapping &VVMapping = getInstructionMapping(4, 1,
 232       getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1),
 233                           nullptr, // Predicate operand.
 234                           AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
 235                           AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}),
 236       4); // Num Operands
 237     AltMappings.push_back(&VVMapping);
 238
 239     return AltMappings;
 240   }
 241   case TargetOpcode::G_SELECT: {
 242     unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
 243     const InstructionMapping &SSMapping = getInstructionMapping(1, 1,
 244       getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
 245                           AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1),
 246                           AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
 247                           AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
 248       4); // Num Operands
 249     AltMappings.push_back(&SSMapping);
 250
 251     const InstructionMapping &VVMapping = getInstructionMapping(2, 1,
 252       getOperandsMapping({AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size),
 253                           AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1),
 254                           AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size),
 255                           AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size)}),
 256       4); // Num Operands
 257     AltMappings.push_back(&VVMapping);
 258
 259     return AltMappings;
 260   }
 261   case TargetOpcode::G_UADDE:
 262   case TargetOpcode::G_USUBE:
 263   case TargetOpcode::G_SADDE:
 264   case TargetOpcode::G_SSUBE: {
 265     unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
 266     const InstructionMapping &SSMapping = getInstructionMapping(1, 1,
 267       getOperandsMapping(
 268         {AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
 269          AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1),
 270          AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
 271          AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
 272          AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1)}),
 273       5); // Num Operands
 274     AltMappings.push_back(&SSMapping);
 275
 276     const InstructionMapping &VVMapping = getInstructionMapping(2, 1,
 277       getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
 278                           AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1),
 279                           AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
 280                           AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
 281                           AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1)}),
 282       5); // Num Operands
 283     AltMappings.push_back(&VVMapping);
 284     return AltMappings;
 285   }
 286   case AMDGPU::G_BRCOND: {
 287     assert(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() == 1);
 288
 289     const InstructionMapping &SMapping = getInstructionMapping(
 290       1, 1, getOperandsMapping(
 291         {AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1), nullptr}),
 292       2); // Num Operands
 293     AltMappings.push_back(&SMapping);
 294
 295     const InstructionMapping &VMapping = getInstructionMapping(
 296       1, 1, getOperandsMapping(
 297         {AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1), nullptr }),
 298       2); // Num Operands
 299     AltMappings.push_back(&VMapping);
 300     return AltMappings;
 301   }
 302   default:
 303     break;
 304   }
 305   return RegisterBankInfo::getInstrAlternativeMappings(MI);
 306 }
 307
 308 void AMDGPURegisterBankInfo::split64BitValueForMapping(
 309   MachineIRBuilder &B,
 310   SmallVector<unsigned, 2> &Regs,
 311   unsigned Reg) const {
 312   LLT S32 = LLT::scalar(32);
 313   MachineRegisterInfo *MRI = B.getMRI();
 314   unsigned LoLHS = MRI->createGenericVirtualRegister(S32);
 315   unsigned HiLHS = MRI->createGenericVirtualRegister(S32);
 316   const RegisterBank *Bank = getRegBank(Reg, *MRI, *TRI);
 317   MRI->setRegBank(LoLHS, *Bank);
 318   MRI->setRegBank(HiLHS, *Bank);
 319
 320   Regs.push_back(LoLHS);
 321   Regs.push_back(HiLHS);
 322
 323   B.buildInstr(AMDGPU::G_UNMERGE_VALUES)
 324     .addDef(LoLHS)
 325     .addDef(HiLHS)
 326     .addUse(Reg);
 327 }
 328
 329 void AMDGPURegisterBankInfo::applyMappingImpl(
 330     const OperandsMapper &OpdMapper) const {
 331   MachineInstr &MI = OpdMapper.getMI();
 332   unsigned Opc = MI.getOpcode();
 333   MachineRegisterInfo &MRI = OpdMapper.getMRI();
 334   switch (Opc) {
 335   case AMDGPU::G_SELECT: {
 336     unsigned DstReg = MI.getOperand(0).getReg();
 337     LLT DstTy = MRI.getType(DstReg);
 338     if (DstTy.getSizeInBits() != 64)
 339       break;
 340
 341     SmallVector<unsigned, 2> DefRegs(OpdMapper.getVRegs(0));
 342     SmallVector<unsigned, 1> Src0Regs(OpdMapper.getVRegs(1));
 343     SmallVector<unsigned, 2> Src1Regs(OpdMapper.getVRegs(2));
 344     SmallVector<unsigned, 2> Src2Regs(OpdMapper.getVRegs(3));
 345
 346     // All inputs are SGPRs, nothing special to do.
 347     if (DefRegs.empty()) {
 348       assert(Src1Regs.empty() && Src2Regs.empty());
 349       break;
 350     }
 351
 352     MachineIRBuilder B(MI);
 353     if (Src0Regs.empty())
 354       Src0Regs.push_back(MI.getOperand(1).getReg());
 355     else {
 356       assert(Src0Regs.size() == 1);
 357     }
 358
 359     if (Src1Regs.empty())
 360       split64BitValueForMapping(B, Src1Regs, MI.getOperand(2).getReg());
 361
 362     if (Src2Regs.empty())
 363       split64BitValueForMapping(B, Src2Regs, MI.getOperand(3).getReg());
 364
 365     B.buildSelect(DefRegs[0], Src0Regs[0], Src1Regs[0], Src2Regs[0]);
 366     B.buildSelect(DefRegs[1], Src0Regs[0], Src1Regs[1], Src2Regs[1]);
 367
 368     MRI.setRegBank(DstReg, getRegBank(AMDGPU::VGPRRegBankID));
 369     MI.eraseFromParent();
 370     return;
 371   }
 372   case AMDGPU::G_AND:
 373   case AMDGPU::G_OR:
 374   case AMDGPU::G_XOR: {
 375     // 64-bit and is only available on the SALU, so split into 2 32-bit ops if
 376     // there is a VGPR input.
 377     unsigned DstReg = MI.getOperand(0).getReg();
 378     if (MRI.getType(DstReg).getSizeInBits() != 64)
 379       break;
 380
 381     SmallVector<unsigned, 2> DefRegs(OpdMapper.getVRegs(0));
 382     SmallVector<unsigned, 2> Src0Regs(OpdMapper.getVRegs(1));
 383     SmallVector<unsigned, 2> Src1Regs(OpdMapper.getVRegs(2));
 384
 385     // All inputs are SGPRs, nothing special to do.
 386     if (DefRegs.empty()) {
 387       assert(Src0Regs.empty() && Src1Regs.empty());
 388       break;
 389     }
 390
 391     assert(DefRegs.size() == 2);
 392     assert(Src0Regs.size() == Src1Regs.size() &&
 393            (Src0Regs.empty() || Src0Regs.size() == 2));
 394
 395     // Depending on where the source registers came from, the generic code may
 396     // have decided to split the inputs already or not. If not, we still need to
 397     // extract the values.
 398     MachineIRBuilder B(MI);
 399
 400     if (Src0Regs.empty())
 401       split64BitValueForMapping(B, Src0Regs, MI.getOperand(1).getReg());
 402
 403     if (Src1Regs.empty())
 404       split64BitValueForMapping(B, Src1Regs, MI.getOperand(2).getReg());
 405
 406     B.buildInstr(Opc)
 407       .addDef(DefRegs[0])
 408       .addUse(Src0Regs[0])
 409       .addUse(Src1Regs[0]);
 410
 411     B.buildInstr(Opc)
 412       .addDef(DefRegs[1])
 413       .addUse(Src0Regs[1])
 414       .addUse(Src1Regs[1]);
 415
 416     MRI.setRegBank(DstReg, getRegBank(AMDGPU::VGPRRegBankID));
 417     MI.eraseFromParent();
 418     return;
 419   }
 420   default:
 421     break;
 422   }
 423
 424   return applyDefaultMapping(OpdMapper);
 425 }
 426
 427 static bool isInstrUniform(const MachineInstr &MI) {
 428   if (!MI.hasOneMemOperand())
 429     return false;
 430
 431   const MachineMemOperand *MMO = *MI.memoperands_begin();
 432   return AMDGPUInstrInfo::isUniformMMO(MMO);
 433 }
 434
 435 bool AMDGPURegisterBankInfo::isSALUMapping(const MachineInstr &MI) const {
 436   const MachineFunction &MF = *MI.getParent()->getParent();
 437   const MachineRegisterInfo &MRI = MF.getRegInfo();
 438   for (unsigned i = 0, e = MI.getNumOperands();i != e; ++i) {
 439     if (!MI.getOperand(i).isReg())
 440       continue;
 441     unsigned Reg = MI.getOperand(i).getReg();
 442     if (const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI)) {
 443       if (Bank->getID() == AMDGPU::VGPRRegBankID)
 444         return false;
 445
 446       assert(Bank->getID() == AMDGPU::SGPRRegBankID ||
 447              Bank->getID() == AMDGPU::SCCRegBankID);
 448     }
 449   }
 450   return true;
 451 }
 452
 453 const RegisterBankInfo::InstructionMapping &
 454 AMDGPURegisterBankInfo::getDefaultMappingSOP(const MachineInstr &MI) const {
 455   const MachineFunction &MF = *MI.getParent()->getParent();
 456   const MachineRegisterInfo &MRI = MF.getRegInfo();
 457   SmallVector<const ValueMapping*, 8> OpdsMapping(MI.getNumOperands());
 458
 459   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
 460     unsigned Size = getSizeInBits(MI.getOperand(i).getReg(), MRI, *TRI);
 461     unsigned BankID = Size == 1 ? AMDGPU::SCCRegBankID : AMDGPU::SGPRRegBankID;
 462     OpdsMapping[i] = AMDGPU::getValueMapping(BankID, Size);
 463   }
 464   return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),
 465                                MI.getNumOperands());
 466 }
 467
 468 const RegisterBankInfo::InstructionMapping &
 469 AMDGPURegisterBankInfo::getDefaultMappingVOP(const MachineInstr &MI) const {
 470   const MachineFunction &MF = *MI.getParent()->getParent();
 471   const MachineRegisterInfo &MRI = MF.getRegInfo();
 472   SmallVector<const ValueMapping*, 8> OpdsMapping(MI.getNumOperands());
 473   unsigned OpdIdx = 0;
 474
 475   unsigned Size0 = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
 476   OpdsMapping[OpdIdx++] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size0);
 477
 478   if (MI.getOperand(OpdIdx).isIntrinsicID())
 479     OpdsMapping[OpdIdx++] = nullptr;
 480
 481   unsigned Reg1 = MI.getOperand(OpdIdx).getReg();
 482   unsigned Size1 = getSizeInBits(Reg1, MRI, *TRI);
 483
 484   unsigned DefaultBankID = Size1 == 1 ?
 485     AMDGPU::VCCRegBankID : AMDGPU::VGPRRegBankID;
 486   unsigned Bank1 = getRegBankID(Reg1, MRI, *TRI, DefaultBankID);
 487
 488   OpdsMapping[OpdIdx++] = AMDGPU::getValueMapping(Bank1, Size1);
 489
 490   for (unsigned e = MI.getNumOperands(); OpdIdx != e; ++OpdIdx) {
 491     unsigned Size = getSizeInBits(MI.getOperand(OpdIdx).getReg(), MRI, *TRI);
 492     unsigned BankID = Size == 1 ? AMDGPU::VCCRegBankID : AMDGPU::VGPRRegBankID;
 493     OpdsMapping[OpdIdx] = AMDGPU::getValueMapping(BankID, Size);
 494   }
 495
 496   return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),
 497                                MI.getNumOperands());
 498 }
 499
 500 const RegisterBankInfo::InstructionMapping &
 501 AMDGPURegisterBankInfo::getDefaultMappingAllVGPR(const MachineInstr &MI) const {
 502   const MachineFunction &MF = *MI.getParent()->getParent();
 503   const MachineRegisterInfo &MRI = MF.getRegInfo();
 504   SmallVector<const ValueMapping*, 8> OpdsMapping(MI.getNumOperands());
 505
 506   for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
 507     unsigned Size = getSizeInBits(MI.getOperand(I).getReg(), MRI, *TRI);
 508     OpdsMapping[I] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
 509   }
 510
 511   return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),
 512                                MI.getNumOperands());
 513 }
 514
 515 const RegisterBankInfo::InstructionMapping &
 516 AMDGPURegisterBankInfo::getInstrMappingForLoad(const MachineInstr &MI) const {
 517
 518   const MachineFunction &MF = *MI.getParent()->getParent();
 519   const MachineRegisterInfo &MRI = MF.getRegInfo();
 520   SmallVector<const ValueMapping*, 8> OpdsMapping(MI.getNumOperands());
 521   unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
 522   unsigned PtrSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI);
 523
 524   const ValueMapping *ValMapping;
 525   const ValueMapping *PtrMapping;
 526
 527   if (isInstrUniform(MI)) {
 528     // We have a uniform instruction so we want to use an SMRD load
 529     ValMapping = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
 530     PtrMapping = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, PtrSize);
 531   } else {
 532     ValMapping = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
 533     // FIXME: What would happen if we used SGPRRegBankID here?
 534     PtrMapping = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, PtrSize);
 535   }
 536
 537   OpdsMapping[0] = ValMapping;
 538   OpdsMapping[1] = PtrMapping;
 539   const RegisterBankInfo::InstructionMapping &Mapping = getInstructionMapping(
 540       1, 1, getOperandsMapping(OpdsMapping), MI.getNumOperands());
 541   return Mapping;
 542
 543   // FIXME: Do we want to add a mapping for FLAT load, or should we just
 544   // handle that during instruction selection?
 545 }
 546
 547 unsigned
 548 AMDGPURegisterBankInfo::getRegBankID(unsigned Reg,
 549                                      const MachineRegisterInfo &MRI,
 550                                      const TargetRegisterInfo &TRI,
 551                                      unsigned Default) const {
 552
 553   const RegisterBank *Bank = getRegBank(Reg, MRI, TRI);
 554   return Bank ? Bank->getID() : Default;
 555 }
 556
 557 ///
 558 /// This function must return a legal mapping, because
 559 /// AMDGPURegisterBankInfo::getInstrAlternativeMappings() is not called
 560 /// in RegBankSelect::Mode::Fast.  Any mapping that would cause a
 561 /// VGPR to SGPR generated is illegal.
 562 ///
 563 const RegisterBankInfo::InstructionMapping &
 564 AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
 565   const RegisterBankInfo::InstructionMapping &Mapping = getInstrMappingImpl(MI);
 566
 567   if (Mapping.isValid())
 568     return Mapping;
 569
 570   const MachineFunction &MF = *MI.getParent()->getParent();
 571   const MachineRegisterInfo &MRI = MF.getRegInfo();
 572   SmallVector<const ValueMapping*, 8> OpdsMapping(MI.getNumOperands());
 573
 574   switch (MI.getOpcode()) {
 575   default:
 576     return getInvalidInstructionMapping();
 577
 578   case AMDGPU::G_AND:
 579   case AMDGPU::G_OR:
 580   case AMDGPU::G_XOR: {
 581     unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
 582     if (Size == 1) {
 583       OpdsMapping[0] = OpdsMapping[1] =
 584         OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
 585       break;
 586     }
 587
 588     if (Size == 64) {
 589
 590       if (isSALUMapping(MI)) {
 591         OpdsMapping[0] = getValueMappingSGPR64Only(AMDGPU::SGPRRegBankID, Size);
 592         OpdsMapping[1] = OpdsMapping[2] = OpdsMapping[0];
 593       } else {
 594         OpdsMapping[0] = getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size);
 595         unsigned Bank1 = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI/*, DefaultBankID*/);
 596         OpdsMapping[1] = AMDGPU::getValueMapping(Bank1, Size);
 597
 598         unsigned Bank2 = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI/*, DefaultBankID*/);
 599         OpdsMapping[2] = AMDGPU::getValueMapping(Bank2, Size);
 600       }
 601
 602       break;
 603     }
 604
 605     LLVM_FALLTHROUGH;
 606   }
 607
 608   case AMDGPU::G_GEP:
 609   case AMDGPU::G_ADD:
 610   case AMDGPU::G_SUB:
 611   case AMDGPU::G_MUL:
 612   case AMDGPU::G_SHL:
 613   case AMDGPU::G_LSHR:
 614   case AMDGPU::G_ASHR:
 615   case AMDGPU::G_UADDO:
 616   case AMDGPU::G_SADDO:
 617   case AMDGPU::G_USUBO:
 618   case AMDGPU::G_SSUBO:
 619   case AMDGPU::G_UADDE:
 620   case AMDGPU::G_SADDE:
 621   case AMDGPU::G_USUBE:
 622   case AMDGPU::G_SSUBE:
 623   case AMDGPU::G_UMULH:
 624   case AMDGPU::G_SMULH:
 625     if (isSALUMapping(MI))
 626       return getDefaultMappingSOP(MI);
 627     LLVM_FALLTHROUGH;
 628
 629   case AMDGPU::G_FADD:
 630   case AMDGPU::G_FSUB:
 631   case AMDGPU::G_FPTOSI:
 632   case AMDGPU::G_FPTOUI:
 633   case AMDGPU::G_FMUL:
 634   case AMDGPU::G_FMA:
 635   case AMDGPU::G_FSQRT:
 636   case AMDGPU::G_SITOFP:
 637   case AMDGPU::G_UITOFP:
 638   case AMDGPU::G_FPTRUNC:
 639   case AMDGPU::G_FPEXT:
 640   case AMDGPU::G_FEXP2:
 641   case AMDGPU::G_FLOG2:
 642   case AMDGPU::G_INTRINSIC_TRUNC:
 643   case AMDGPU::G_INTRINSIC_ROUND:
 644     return getDefaultMappingVOP(MI);
 645   case AMDGPU::G_IMPLICIT_DEF: {
 646     unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
 647     OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
 648     break;
 649   }
 650   case AMDGPU::G_FCONSTANT:
 651   case AMDGPU::G_CONSTANT:
 652   case AMDGPU::G_FRAME_INDEX:
 653   case AMDGPU::G_BLOCK_ADDR: {
 654     unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
 655     OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
 656     break;
 657   }
 658   case AMDGPU::G_INSERT: {
 659     unsigned BankID = isSALUMapping(MI) ? AMDGPU::SGPRRegBankID :
 660                                           AMDGPU::VGPRRegBankID;
 661     unsigned DstSize = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
 662     unsigned SrcSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI);
 663     unsigned EltSize = getSizeInBits(MI.getOperand(2).getReg(), MRI, *TRI);
 664     OpdsMapping[0] = AMDGPU::getValueMapping(BankID, DstSize);
 665     OpdsMapping[1] = AMDGPU::getValueMapping(BankID, SrcSize);
 666     OpdsMapping[2] = AMDGPU::getValueMapping(BankID, EltSize);
 667     OpdsMapping[3] = nullptr;
 668     break;
 669   }
 670   case AMDGPU::G_EXTRACT: {
 671     unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
 672     unsigned DstSize = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
 673     unsigned SrcSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI);
 674     OpdsMapping[0] = AMDGPU::getValueMapping(BankID, DstSize);
 675     OpdsMapping[1] = AMDGPU::getValueMapping(BankID, SrcSize);
 676     OpdsMapping[2] = nullptr;
 677     break;
 678   }
 679   case AMDGPU::G_MERGE_VALUES: {
 680     unsigned Bank = isSALUMapping(MI) ?
 681       AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
 682     unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
 683     unsigned SrcSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
 684
 685     OpdsMapping[0] = AMDGPU::getValueMapping(Bank, DstSize);
 686     // Op1 and Dst should use the same register bank.
 687     for (unsigned i = 1, e = MI.getNumOperands(); i != e; ++i)
 688       OpdsMapping[i] = AMDGPU::getValueMapping(Bank, SrcSize);
 689     break;
 690   }
 691   case AMDGPU::G_BITCAST:
 692   case AMDGPU::G_INTTOPTR:
 693   case AMDGPU::G_PTRTOINT:
 694   case AMDGPU::G_CTLZ:
 695   case AMDGPU::G_CTLZ_ZERO_UNDEF:
 696   case AMDGPU::G_CTTZ:
 697   case AMDGPU::G_CTTZ_ZERO_UNDEF:
 698   case AMDGPU::G_CTPOP:
 699   case AMDGPU::G_BSWAP:
 700   case AMDGPU::G_FABS:
 701   case AMDGPU::G_FNEG: {
 702     unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
 703     unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
 704     OpdsMapping[0] = OpdsMapping[1] = AMDGPU::getValueMapping(BankID, Size);
 705     break;
 706   }
 707   case AMDGPU::G_TRUNC: {
 708     unsigned Dst = MI.getOperand(0).getReg();
 709     unsigned Src = MI.getOperand(1).getReg();
 710     unsigned Bank = getRegBankID(Src, MRI, *TRI);
 711     unsigned DstSize = getSizeInBits(Dst, MRI, *TRI);
 712     unsigned SrcSize = getSizeInBits(Src, MRI, *TRI);
 713     OpdsMapping[0] = AMDGPU::getValueMapping(Bank, DstSize);
 714     OpdsMapping[1] = AMDGPU::getValueMapping(Bank, SrcSize);
 715     break;
 716   }
 717   case AMDGPU::G_ZEXT:
 718   case AMDGPU::G_SEXT:
 719   case AMDGPU::G_ANYEXT: {
 720     unsigned Dst = MI.getOperand(0).getReg();
 721     unsigned Src = MI.getOperand(1).getReg();
 722     unsigned DstSize = getSizeInBits(Dst, MRI, *TRI);
 723     unsigned SrcSize = getSizeInBits(Src, MRI, *TRI);
 724     unsigned SrcBank = getRegBankID(Src, MRI, *TRI,
 725                                     SrcSize == 1 ? AMDGPU::SGPRRegBankID :
 726                                     AMDGPU::VGPRRegBankID);
 727     unsigned DstBank = SrcBank;
 728     if (SrcSize == 1) {
 729       if (SrcBank == AMDGPU::SGPRRegBankID)
 730         DstBank = AMDGPU::VGPRRegBankID;
 731       else
 732         DstBank = AMDGPU::SGPRRegBankID;
 733     }
 734
 735     OpdsMapping[0] = AMDGPU::getValueMapping(DstBank, DstSize);
 736     OpdsMapping[1] = AMDGPU::getValueMapping(SrcBank, SrcSize);
 737     break;
 738   }
 739   case AMDGPU::G_FCMP: {
 740     unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
 741     unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
 742     OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1);
 743     OpdsMapping[1] = nullptr; // Predicate Operand.
 744     OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size);
 745     OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
 746     break;
 747   }
 748   case AMDGPU::G_STORE: {
 749     assert(MI.getOperand(0).isReg());
 750     unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
 751     // FIXME: We need to specify a different reg bank once scalar stores
 752     // are supported.
 753     const ValueMapping *ValMapping =
 754         AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
 755     // FIXME: Depending on the type of store, the pointer could be in
 756     // the SGPR Reg bank.
 757     // FIXME: Pointer size should be based on the address space.
 758     const ValueMapping *PtrMapping =
 759         AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 64);
 760
 761     OpdsMapping[0] = ValMapping;
 762     OpdsMapping[1] = PtrMapping;
 763     break;
 764   }
 765
 766   case AMDGPU::G_ICMP: {
 767     unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
 768     unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
 769     unsigned Op3Bank = getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI);
 770     unsigned Op0Bank = Op2Bank == AMDGPU::SGPRRegBankID &&
 771                        Op3Bank == AMDGPU::SGPRRegBankID ?
 772                        AMDGPU::SCCRegBankID : AMDGPU::VCCRegBankID;
 773     OpdsMapping[0] = AMDGPU::getValueMapping(Op0Bank, 1);
 774     OpdsMapping[1] = nullptr; // Predicate Operand.
 775     OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size);
 776     OpdsMapping[3] = AMDGPU::getValueMapping(Op3Bank, Size);
 777     break;
 778   }
 779
 780
 781   case AMDGPU::G_EXTRACT_VECTOR_ELT: {
 782     unsigned IdxOp = 2;
 783     int64_t Imm;
 784     // XXX - Do we really need to fully handle these? The constant case should
 785     // be legalized away before RegBankSelect?
 786
 787     unsigned OutputBankID = isSALUMapping(MI) && isConstant(MI.getOperand(IdxOp), Imm) ?
 788                             AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
 789
 790     unsigned IdxBank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
 791     OpdsMapping[0] = AMDGPU::getValueMapping(OutputBankID, MRI.getType(MI.getOperand(0).getReg()).getSizeInBits());
 792     OpdsMapping[1] = AMDGPU::getValueMapping(OutputBankID, MRI.getType(MI.getOperand(1).getReg()).getSizeInBits());
 793
 794     // The index can be either if the source vector is VGPR.
 795     OpdsMapping[2] = AMDGPU::getValueMapping(IdxBank, MRI.getType(MI.getOperand(2).getReg()).getSizeInBits());
 796     break;
 797   }
 798   case AMDGPU::G_INSERT_VECTOR_ELT: {
 799     // XXX - Do we really need to fully handle these? The constant case should
 800     // be legalized away before RegBankSelect?
 801
 802     int64_t Imm;
 803
 804     unsigned IdxOp = MI.getOpcode() == AMDGPU::G_EXTRACT_VECTOR_ELT ? 2 : 3;
 805     unsigned BankID = isSALUMapping(MI) && isConstant(MI.getOperand(IdxOp), Imm) ?
 806                       AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
 807
 808
 809
 810     // TODO: Can do SGPR indexing, which would obviate the need for the
 811     // isConstant check.
 812     for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
 813       unsigned Size = getSizeInBits(MI.getOperand(i).getReg(), MRI, *TRI);
 814       OpdsMapping[i] = AMDGPU::getValueMapping(BankID, Size);
 815     }
 816
 817
 818     break;
 819   }
 820   case AMDGPU::G_UNMERGE_VALUES: {
 821     unsigned Bank = isSALUMapping(MI) ? AMDGPU::SGPRRegBankID :
 822       AMDGPU::VGPRRegBankID;
 823
 824     // Op1 and Dst should use the same register bank.
 825     // FIXME: Shouldn't this be the default? Why do we need to handle this?
 826     for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
 827       unsigned Size = getSizeInBits(MI.getOperand(i).getReg(), MRI, *TRI);
 828       OpdsMapping[i] = AMDGPU::getValueMapping(Bank, Size);
 829     }
 830     break;
 831   }
 832   case AMDGPU::G_INTRINSIC: {
 833     switch (MI.getOperand(1).getIntrinsicID()) {
 834     default:
 835       return getInvalidInstructionMapping();
 836     case Intrinsic::maxnum:
 837     case Intrinsic::minnum:
 838     case Intrinsic::amdgcn_cvt_pkrtz:
 839       return getDefaultMappingVOP(MI);
 840     case Intrinsic::amdgcn_kernarg_segment_ptr: {
 841       unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
 842       OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
 843       break;
 844     }
 845     case Intrinsic::amdgcn_wqm_vote: {
 846       unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
 847       OpdsMapping[0] = OpdsMapping[2]
 848         = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
 849       break;
 850     }
 851     }
 852     break;
 853   }
 854   case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: {
 855     switch (MI.getOperand(0).getIntrinsicID()) {
 856     default:
 857       return getInvalidInstructionMapping();
 858     case Intrinsic::amdgcn_exp_compr:
 859       OpdsMapping[0] = nullptr; // IntrinsicID
 860       // FIXME: These are immediate values which can't be read from registers.
 861       OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
 862       OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
 863       // FIXME: Could we support packed types here?
 864       OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
 865       OpdsMapping[4] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
 866       // FIXME: These are immediate values which can't be read from registers.
 867       OpdsMapping[5] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
 868       OpdsMapping[6] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
 869       break;
 870     case Intrinsic::amdgcn_exp:
 871       OpdsMapping[0] = nullptr; // IntrinsicID
 872       // FIXME: These are immediate values which can't be read from registers.
 873       OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
 874       OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
 875       // FIXME: Could we support packed types here?
 876       OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
 877       OpdsMapping[4] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
 878       OpdsMapping[5] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
 879       OpdsMapping[6] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
 880       // FIXME: These are immediate values which can't be read from registers.
 881       OpdsMapping[7] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
 882       OpdsMapping[8] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
 883       break;
 884     }
 885     break;
 886   }
 887   case AMDGPU::G_SELECT: {
 888     unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
 889     unsigned Op1Bank = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI,
 890                                     AMDGPU::SGPRRegBankID);
 891     unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
 892     unsigned Op3Bank = getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI);
 893     bool SGPRSrcs = Op1Bank == AMDGPU::SCCRegBankID &&
 894                     Op2Bank == AMDGPU::SGPRRegBankID &&
 895                     Op3Bank == AMDGPU::SGPRRegBankID;
 896     unsigned Bank = SGPRSrcs ? AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
 897     Op1Bank = SGPRSrcs ? AMDGPU::SCCRegBankID : AMDGPU::VCCRegBankID;
 898
 899     if (Size == 64) {
 900       OpdsMapping[0] = AMDGPU::getValueMappingSGPR64Only(Bank, Size);
 901       OpdsMapping[1] = AMDGPU::getValueMapping(Op1Bank, 1);
 902       OpdsMapping[2] = AMDGPU::getValueMappingSGPR64Only(Bank, Size);
 903       OpdsMapping[3] = AMDGPU::getValueMappingSGPR64Only(Bank, Size);
 904     } else {
 905       OpdsMapping[0] = AMDGPU::getValueMapping(Bank, Size);
 906       OpdsMapping[1] = AMDGPU::getValueMapping(Op1Bank, 1);
 907       OpdsMapping[2] = AMDGPU::getValueMapping(Bank, Size);
 908       OpdsMapping[3] = AMDGPU::getValueMapping(Bank, Size);
 909     }
 910
 911     break;
 912   }
 913
 914   case AMDGPU::G_LOAD:
 915     return getInstrMappingForLoad(MI);
 916
 917   case AMDGPU::G_ATOMICRMW_XCHG:
 918   case AMDGPU::G_ATOMICRMW_ADD:
 919   case AMDGPU::G_ATOMICRMW_SUB:
 920   case AMDGPU::G_ATOMICRMW_AND:
 921   case AMDGPU::G_ATOMICRMW_OR:
 922   case AMDGPU::G_ATOMICRMW_XOR:
 923   case AMDGPU::G_ATOMICRMW_MAX:
 924   case AMDGPU::G_ATOMICRMW_MIN:
 925   case AMDGPU::G_ATOMICRMW_UMAX:
 926   case AMDGPU::G_ATOMICRMW_UMIN:
 927   case AMDGPU::G_ATOMIC_CMPXCHG: {
 928     return getDefaultMappingAllVGPR(MI);
 929   }
 930   case AMDGPU::G_BRCOND: {
 931     unsigned Bank = getRegBankID(MI.getOperand(0).getReg(), MRI, *TRI,
 932                                  AMDGPU::SGPRRegBankID);
 933     assert(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() == 1);
 934     if (Bank != AMDGPU::SCCRegBankID)
 935       Bank = AMDGPU::VCCRegBankID;
 936
 937     OpdsMapping[0] = AMDGPU::getValueMapping(Bank, 1);
 938     break;
 939   }
 940   }
 941
 942   return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),
 943                                MI.getNumOperands());
 944 }
 945