lib/Target/AMDGPU/AMDGPURegisterBankInfo.h

   1 //===- AMDGPURegisterBankInfo -----------------------------------*- C++ -*-==//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 /// \file
   9 /// This file declares the targeting of the RegisterBankInfo class for AMDGPU.
  10 /// \todo This should be generated by TableGen.
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
  14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
  15
  16 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
  17
  18 #define GET_REGBANK_DECLARATIONS
  19 #include "AMDGPUGenRegisterBank.inc"
  20 #undef GET_REGBANK_DECLARATIONS
  21
  22 namespace llvm {
  23
  24 class MachineIRBuilder;
  25 class SIRegisterInfo;
  26 class TargetRegisterInfo;
  27
  28 /// This class provides the information for the target register banks.
  29 class AMDGPUGenRegisterBankInfo : public RegisterBankInfo {
  30
  31 protected:
  32
  33 #define GET_TARGET_REGBANK_CLASS
  34 #include "AMDGPUGenRegisterBank.inc"
  35 };
  36 class AMDGPURegisterBankInfo : public AMDGPUGenRegisterBankInfo {
  37   const SIRegisterInfo *TRI;
  38
  39   /// See RegisterBankInfo::applyMapping.
  40   void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
  41
  42   const RegisterBankInfo::InstructionMapping &
  43   getInstrMappingForLoad(const MachineInstr &MI) const;
  44
  45   unsigned getRegBankID(unsigned Reg, const MachineRegisterInfo &MRI,
  46                         const TargetRegisterInfo &TRI,
  47                         unsigned Default = AMDGPU::VGPRRegBankID) const;
  48
  49   /// Split 64-bit value \p Reg into two 32-bit halves and populate them into \p
  50   /// Regs. This appropriately sets the regbank of the new registers.
  51   void split64BitValueForMapping(MachineIRBuilder &B,
  52                                  SmallVector<unsigned, 2> &Regs,
  53                                  unsigned Reg) const;
  54
  55   bool isSALUMapping(const MachineInstr &MI) const;
  56   const InstructionMapping &getDefaultMappingSOP(const MachineInstr &MI) const;
  57   const InstructionMapping &getDefaultMappingVOP(const MachineInstr &MI) const;
  58   const InstructionMapping &getDefaultMappingAllVGPR(
  59     const MachineInstr &MI) const;
  60 public:
  61   AMDGPURegisterBankInfo(const TargetRegisterInfo &TRI);
  62
  63   unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
  64                     unsigned Size) const override;
  65
  66   unsigned getBreakDownCost(const ValueMapping &ValMapping,
  67                             const RegisterBank *CurBank = nullptr) const override;
  68
  69   const RegisterBank &
  70   getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
  71
  72   InstructionMappings
  73   getInstrAlternativeMappings(const MachineInstr &MI) const override;
  74
  75   const InstructionMapping &
  76   getInstrMapping(const MachineInstr &MI) const override;
  77 };
  78 } // End llvm namespace.
  79 #endif