lib/Target/AMDGPU/GCNHazardRecognizer.h

   1 //===-- GCNHazardRecognizers.h - GCN Hazard Recognizers ---------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines hazard recognizers for scheduling on GCN processors.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
  14 #define LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
  15
  16 #include "llvm/ADT/BitVector.h"
  17 #include "llvm/ADT/STLExtras.h"
  18 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
  19 #include <list>
  20
  21 namespace llvm {
  22
  23 class MachineFunction;
  24 class MachineInstr;
  25 class MachineOperand;
  26 class MachineRegisterInfo;
  27 class ScheduleDAG;
  28 class SIInstrInfo;
  29 class SIRegisterInfo;
  30 class GCNSubtarget;
  31
  32 class GCNHazardRecognizer final : public ScheduleHazardRecognizer {
  33 public:
  34   typedef function_ref<bool(MachineInstr *)> IsHazardFn;
  35
  36 private:
  37   // Distinguish if we are called from scheduler or hazard recognizer
  38   bool IsHazardRecognizerMode;
  39
  40   // This variable stores the instruction that has been emitted this cycle. It
  41   // will be added to EmittedInstrs, when AdvanceCycle() or RecedeCycle() is
  42   // called.
  43   MachineInstr *CurrCycleInstr;
  44   std::list<MachineInstr*> EmittedInstrs;
  45   const MachineFunction &MF;
  46   const GCNSubtarget &ST;
  47   const SIInstrInfo &TII;
  48   const SIRegisterInfo &TRI;
  49
  50   /// RegUnits of uses in the current soft memory clause.
  51   BitVector ClauseUses;
  52
  53   /// RegUnits of defs in the current soft memory clause.
  54   BitVector ClauseDefs;
  55
  56   void resetClause() {
  57     ClauseUses.reset();
  58     ClauseDefs.reset();
  59   }
  60
  61   void addClauseInst(const MachineInstr &MI);
  62
  63   int getWaitStatesSince(IsHazardFn IsHazard, int Limit);
  64   int getWaitStatesSinceDef(unsigned Reg, IsHazardFn IsHazardDef, int Limit);
  65   int getWaitStatesSinceSetReg(IsHazardFn IsHazard, int Limit);
  66
  67   int checkSoftClauseHazards(MachineInstr *SMEM);
  68   int checkSMRDHazards(MachineInstr *SMRD);
  69   int checkVMEMHazards(MachineInstr* VMEM);
  70   int checkDPPHazards(MachineInstr *DPP);
  71   int checkDivFMasHazards(MachineInstr *DivFMas);
  72   int checkGetRegHazards(MachineInstr *GetRegInstr);
  73   int checkSetRegHazards(MachineInstr *SetRegInstr);
  74   int createsVALUHazard(const MachineInstr &MI);
  75   int checkVALUHazards(MachineInstr *VALU);
  76   int checkVALUHazardsHelper(const MachineOperand &Def, const MachineRegisterInfo &MRI);
  77   int checkRWLaneHazards(MachineInstr *RWLane);
  78   int checkRFEHazards(MachineInstr *RFE);
  79   int checkInlineAsmHazards(MachineInstr *IA);
  80   int checkAnyInstHazards(MachineInstr *MI);
  81   int checkReadM0Hazards(MachineInstr *SMovRel);
  82 public:
  83   GCNHazardRecognizer(const MachineFunction &MF);
  84   // We can only issue one instruction per cycle.
  85   bool atIssueLimit() const override { return true; }
  86   void EmitInstruction(SUnit *SU) override;
  87   void EmitInstruction(MachineInstr *MI) override;
  88   HazardType getHazardType(SUnit *SU, int Stalls) override;
  89   void EmitNoop() override;
  90   unsigned PreEmitNoops(SUnit *SU) override;
  91   unsigned PreEmitNoops(MachineInstr *) override;
  92   unsigned PreEmitNoopsCommon(MachineInstr *);
  93   void AdvanceCycle() override;
  94   void RecedeCycle() override;
  95 };
  96
  97 } // end namespace llvm
  98
  99 #endif //LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H