lib/Target/AMDGPU/R600ISelLowering.h

   1 //===-- R600ISelLowering.h - R600 DAG Lowering Interface -*- C++ -*--------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 /// \file
  10 /// R600 DAG Lowering interface definition
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_AMDGPU_R600ISELLOWERING_H
  15 #define LLVM_LIB_TARGET_AMDGPU_R600ISELLOWERING_H
  16
  17 #include "AMDGPUISelLowering.h"
  18
  19 namespace llvm {
  20
  21 class R600InstrInfo;
  22 class R600Subtarget;
  23
  24 class R600TargetLowering final : public AMDGPUTargetLowering {
  25
  26   const R600Subtarget *Subtarget;
  27 public:
  28   R600TargetLowering(const TargetMachine &TM, const R600Subtarget &STI);
  29
  30   const R600Subtarget *getSubtarget() const;
  31
  32   MachineBasicBlock *
  33   EmitInstrWithCustomInserter(MachineInstr &MI,
  34                               MachineBasicBlock *BB) const override;
  35   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
  36   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
  37   void ReplaceNodeResults(SDNode * N,
  38                           SmallVectorImpl<SDValue> &Results,
  39                           SelectionDAG &DAG) const override;
  40   CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
  41   SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
  42                                bool isVarArg,
  43                                const SmallVectorImpl<ISD::InputArg> &Ins,
  44                                const SDLoc &DL, SelectionDAG &DAG,
  45                                SmallVectorImpl<SDValue> &InVals) const override;
  46   EVT getSetCCResultType(const DataLayout &DL, LLVMContext &,
  47                          EVT VT) const override;
  48
  49   bool canMergeStoresTo(unsigned AS, EVT MemVT,
  50                         const SelectionDAG &DAG) const override;
  51
  52   bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
  53                                       unsigned Align,
  54                                       bool *IsFast) const override;
  55
  56 private:
  57   unsigned Gen;
  58   /// Each OpenCL kernel has nine implicit parameters that are stored in the
  59   /// first nine dwords of a Vertex Buffer.  These implicit parameters are
  60   /// lowered to load instructions which retrieve the values from the Vertex
  61   /// Buffer.
  62   SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT, const SDLoc &DL,
  63                                  unsigned DwordOffset) const;
  64
  65   void lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
  66       MachineRegisterInfo & MRI, unsigned dword_offset) const;
  67   SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG,
  68                           const SDLoc &DL) const;
  69   SDValue vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const;
  70
  71   SDValue lowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
  72   SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
  73   SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
  74   SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
  75                              SelectionDAG &DAG) const override;
  76   SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
  77
  78   SDValue lowerPrivateTruncStore(StoreSDNode *Store, SelectionDAG &DAG) const;
  79   SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
  80   SDValue lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
  81   SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
  82
  83   SDValue lowerPrivateExtLoad(SDValue Op, SelectionDAG &DAG) const;
  84   SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
  85   SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
  86   SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
  87   SDValue LowerSHLParts(SDValue Op, SelectionDAG &DAG) const;
  88   SDValue LowerSRXParts(SDValue Op, SelectionDAG &DAG) const;
  89   SDValue LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
  90                         unsigned mainop, unsigned ovf) const;
  91
  92   SDValue stackPtrToRegIndex(SDValue Ptr, unsigned StackWidth,
  93                                           SelectionDAG &DAG) const;
  94   void getStackAddress(unsigned StackWidth, unsigned ElemIdx,
  95                        unsigned &Channel, unsigned &PtrIncr) const;
  96   bool isZero(SDValue Op) const;
  97   bool isHWTrueValue(SDValue Op) const;
  98   bool isHWFalseValue(SDValue Op) const;
  99
 100   bool FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src,
 101                    SDValue &Neg, SDValue &Abs, SDValue &Sel, SDValue &Imm,
 102                    SelectionDAG &DAG) const;
 103   SDValue constBufferLoad(LoadSDNode *LoadNode, int Block,
 104                           SelectionDAG &DAG) const;
 105
 106   SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
 107 };
 108
 109 } // End namespace llvm;
 110
 111 #endif