lib/Target/ARM/ARM.td

   1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 //
  10 //===----------------------------------------------------------------------===//
  11
  12 //===----------------------------------------------------------------------===//
  13 // Target-independent interfaces which we are implementing
  14 //===----------------------------------------------------------------------===//
  15
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // ARM Subtarget state.
  20 //
  21
  22 def ModeThumb             : SubtargetFeature<"thumb-mode", "InThumbMode",
  23                                              "true", "Thumb mode">;
  24
  25 def ModeSoftFloat         : SubtargetFeature<"soft-float","UseSoftFloat",
  26                                              "true", "Use software floating "
  27                                              "point features.">;
  28
  29
  30 //===----------------------------------------------------------------------===//
  31 // ARM Subtarget features.
  32 //
  33
  34 // Floating Point, HW Division and Neon Support
  35 def FeatureVFP2           : SubtargetFeature<"vfp2", "HasVFPv2", "true",
  36                                              "Enable VFP2 instructions">;
  37
  38 def FeatureVFP3           : SubtargetFeature<"vfp3", "HasVFPv3", "true",
  39                                              "Enable VFP3 instructions",
  40                                              [FeatureVFP2]>;
  41
  42 def FeatureNEON           : SubtargetFeature<"neon", "HasNEON", "true",
  43                                              "Enable NEON instructions",
  44                                              [FeatureVFP3]>;
  45
  46 def FeatureFP16           : SubtargetFeature<"fp16", "HasFP16", "true",
  47                                              "Enable half-precision "
  48                                              "floating point">;
  49
  50 def FeatureVFP4           : SubtargetFeature<"vfp4", "HasVFPv4", "true",
  51                                              "Enable VFP4 instructions",
  52                                              [FeatureVFP3, FeatureFP16]>;
  53
  54 def FeatureFPARMv8        : SubtargetFeature<"fp-armv8", "HasFPARMv8",
  55                                              "true", "Enable ARMv8 FP",
  56                                              [FeatureVFP4]>;
  57
  58 def FeatureFullFP16       : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
  59                                              "Enable full half-precision "
  60                                              "floating point",
  61                                              [FeatureFPARMv8]>;
  62
  63 def FeatureFP16FML        : SubtargetFeature<"fp16fml", "HasFP16FML", "true",
  64                                              "Enable full half-precision "
  65                                              "floating point fml instructions",
  66                                              [FeatureFullFP16]>;
  67
  68 def FeatureVFPOnlySP      : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
  69                                              "Floating point unit supports "
  70                                              "single precision only">;
  71
  72 def FeatureD16            : SubtargetFeature<"d16", "HasD16", "true",
  73                                              "Restrict FP to 16 double registers">;
  74
  75 def FeatureHWDivThumb     : SubtargetFeature<"hwdiv",
  76                                              "HasHardwareDivideInThumb", "true",
  77                                              "Enable divide instructions in Thumb">;
  78
  79 def FeatureHWDivARM       : SubtargetFeature<"hwdiv-arm",
  80                                              "HasHardwareDivideInARM", "true",
  81                                              "Enable divide instructions in ARM mode">;
  82
  83 // Atomic Support
  84 def FeatureDB             : SubtargetFeature<"db", "HasDataBarrier", "true",
  85                                              "Has data barrier (dmb/dsb) instructions">;
  86
  87 def FeatureV7Clrex        : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
  88                                              "Has v7 clrex instruction">;
  89
  90 def FeatureDFB  : SubtargetFeature<"dfb", "HasFullDataBarrier", "true",
  91                                    "Has full data barrier (dfb) instruction">;
  92
  93 def FeatureAcquireRelease : SubtargetFeature<"acquire-release",
  94                                              "HasAcquireRelease", "true",
  95                                              "Has v8 acquire/release (lda/ldaex "
  96                                              " etc) instructions">;
  97
  98
  99 def FeatureSlowFPBrcc     : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
 100                                              "FP compare + branch is slow">;
 101
 102 def FeaturePerfMon        : SubtargetFeature<"perfmon", "HasPerfMon", "true",
 103                                              "Enable support for Performance "
 104                                              "Monitor extensions">;
 105
 106
 107 // TrustZone Security Extensions
 108 def FeatureTrustZone      : SubtargetFeature<"trustzone", "HasTrustZone", "true",
 109                                              "Enable support for TrustZone "
 110                                              "security extensions">;
 111
 112 def Feature8MSecExt       : SubtargetFeature<"8msecext", "Has8MSecExt", "true",
 113                                              "Enable support for ARMv8-M "
 114                                              "Security Extensions">;
 115
 116 def FeatureSHA2           : SubtargetFeature<"sha2", "HasSHA2", "true",
 117                                              "Enable SHA1 and SHA256 support", [FeatureNEON]>;
 118
 119 def FeatureAES            : SubtargetFeature<"aes", "HasAES", "true",
 120                                              "Enable AES support", [FeatureNEON]>;
 121
 122 def FeatureCrypto         : SubtargetFeature<"crypto", "HasCrypto", "true",
 123                                              "Enable support for "
 124                                              "Cryptography extensions",
 125                                              [FeatureNEON, FeatureSHA2, FeatureAES]>;
 126
 127 def FeatureCRC            : SubtargetFeature<"crc", "HasCRC", "true",
 128                                              "Enable support for CRC instructions">;
 129
 130 def FeatureDotProd        : SubtargetFeature<"dotprod", "HasDotProd", "true",
 131                                              "Enable support for dot product instructions",
 132                                              [FeatureNEON]>;
 133
 134 // Not to be confused with FeatureHasRetAddrStack (return address stack)
 135 def FeatureRAS            : SubtargetFeature<"ras", "HasRAS", "true",
 136                                              "Enable Reliability, Availability "
 137                                              "and Serviceability extensions">;
 138
 139 // Fast computation of non-negative address offsets
 140 def FeatureFPAO           : SubtargetFeature<"fpao", "HasFPAO", "true",
 141                                              "Enable fast computation of "
 142                                              "positive address offsets">;
 143
 144 // Fast execution of AES crypto operations
 145 def FeatureFuseAES        : SubtargetFeature<"fuse-aes", "HasFuseAES", "true",
 146                                              "CPU fuses AES crypto operations">;
 147
 148 // Fast execution of bottom and top halves of literal generation
 149 def FeatureFuseLiterals   : SubtargetFeature<"fuse-literals", "HasFuseLiterals", "true",
 150                                              "CPU fuses literal generation operations">;
 151
 152 // The way of reading thread pointer
 153 def FeatureReadTp :  SubtargetFeature<"read-tp-hard", "ReadTPHard", "true",
 154                                       "Reading thread pointer from register">;
 155
 156 // Cyclone can zero VFP registers in 0 cycles.
 157 def FeatureZCZeroing      : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
 158                                              "Has zero-cycle zeroing instructions">;
 159
 160 // Whether it is profitable to unpredicate certain instructions during if-conversion
 161 def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr",
 162                                               "IsProfitableToUnpredicate", "true",
 163                                               "Is profitable to unpredicate">;
 164
 165 // Some targets (e.g. Swift) have microcoded VGETLNi32.
 166 def FeatureSlowVGETLNi32  : SubtargetFeature<"slow-vgetlni32",
 167                                              "HasSlowVGETLNi32", "true",
 168                                              "Has slow VGETLNi32 - prefer VMOV">;
 169
 170 // Some targets (e.g. Swift) have microcoded VDUP32.
 171 def FeatureSlowVDUP32     : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32",
 172                                              "true",
 173                                              "Has slow VDUP32 - prefer VMOV">;
 174
 175 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
 176 // for scalar FP, as this allows more effective execution domain optimization.
 177 def FeaturePreferVMOVSR   : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR",
 178                                              "true", "Prefer VMOVSR">;
 179
 180 // Swift has ISHST barriers compatible with Atomic Release semantics but weaker
 181 // than ISH
 182 def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST",
 183                                                "true", "Prefer ISHST barriers">;
 184
 185 // Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU.
 186 def FeatureMuxedUnits     : SubtargetFeature<"muxed-units", "HasMuxedUnits",
 187                                              "true",
 188                                              "Has muxed AGU and NEON/FPU">;
 189
 190 // Whether VLDM/VSTM starting with odd register number need more microops
 191 // than single VLDRS
 192 def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister",
 193                                               "true", "VLDM/VSTM starting "
 194                                               "with an odd register is slow">;
 195
 196 // Some targets have a renaming dependency when loading into D subregisters.
 197 def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg",
 198                                               "SlowLoadDSubregister", "true",
 199                                               "Loading into D subregs is slow">;
 200
 201 def FeatureUseWideStrideVFP : SubtargetFeature<"wide-stride-vfp",
 202                                                "UseWideStrideVFP", "true",
 203                                                "Use a wide stride when allocating VFP registers">;
 204
 205 // Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD.
 206 def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs",
 207                                              "DontWidenVMOVS", "true",
 208                                              "Don't widen VMOVS to VMOVD">;
 209
 210 // Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different
 211 // VFP register widths.
 212 def FeatureSplatVFPToNeon : SubtargetFeature<"splat-vfp-neon",
 213                                              "SplatVFPToNeon", "true",
 214                                              "Splat register from VFP to NEON",
 215                                              [FeatureDontWidenVMOVS]>;
 216
 217 // Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions.
 218 def FeatureExpandMLx      : SubtargetFeature<"expand-fp-mlx",
 219                                              "ExpandMLx", "true",
 220                                              "Expand VFP/NEON MLA/MLS instructions">;
 221
 222 // Some targets have special RAW hazards for VFP/NEON VMLA/VMLS.
 223 def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards",
 224                                              "true", "Has VMLx hazards">;
 225
 226 // Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
 227 // VFP to NEON, as an execution domain optimization.
 228 def FeatureNEONForFPMovs  : SubtargetFeature<"neon-fpmovs",
 229                                              "UseNEONForFPMovs", "true",
 230                                              "Convert VMOVSR, VMOVRS, "
 231                                              "VMOVS to NEON">;
 232
 233 // Some processors benefit from using NEON instructions for scalar
 234 // single-precision FP operations. This affects instruction selection and should
 235 // only be enabled if the handling of denormals is not important.
 236 def FeatureNEONForFP      : SubtargetFeature<"neonfp",
 237                                              "UseNEONForSinglePrecisionFP",
 238                                              "true",
 239                                              "Use NEON for single precision FP">;
 240
 241 // On some processors, VLDn instructions that access unaligned data take one
 242 // extra cycle. Take that into account when computing operand latencies.
 243 def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign",
 244                                              "true",
 245                                              "Check for VLDn unaligned access">;
 246
 247 // Some processors have a nonpipelined VFP coprocessor.
 248 def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp",
 249                                               "NonpipelinedVFP", "true",
 250                                               "VFP instructions are not pipelined">;
 251
 252 // Some processors have FP multiply-accumulate instructions that don't
 253 // play nicely with other VFP / NEON instructions, and it's generally better
 254 // to just not use them.
 255 def FeatureHasSlowFPVMLx  : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
 256                                              "Disable VFP / NEON MAC instructions">;
 257
 258 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
 259 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
 260                                              "HasVMLxForwarding", "true",
 261                                              "Has multiplier accumulator forwarding">;
 262
 263 // Disable 32-bit to 16-bit narrowing for experimentation.
 264 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
 265                                              "Prefer 32-bit Thumb instrs">;
 266
 267 def FeaturePrefLoopAlign32 : SubtargetFeature<"loop-align", "PrefLoopAlignment","2",
 268                                               "Prefer 32-bit alignment for loops">;
 269
 270 /// Some instructions update CPSR partially, which can add false dependency for
 271 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
 272 /// mapped to a separate physical register. Avoid partial CPSR update for these
 273 /// processors.
 274 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
 275                                                "AvoidCPSRPartialUpdate", "true",
 276                                  "Avoid CPSR partial update for OOO execution">;
 277
 278 /// Disable +1 predication cost for instructions updating CPSR.
 279 /// Enabled for Cortex-A57.
 280 def FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr",
 281                                                   "CheapPredicableCPSRDef",
 282                                                   "true",
 283                   "Disable +1 predication cost for instructions updating CPSR">;
 284
 285 def FeatureAvoidMOVsShOp  : SubtargetFeature<"avoid-movs-shop",
 286                                              "AvoidMOVsShifterOperand", "true",
 287                                              "Avoid movs instructions with "
 288                                              "shifter operand">;
 289
 290 // Some processors perform return stack prediction. CodeGen should avoid issue
 291 // "normal" call instructions to callees which do not return.
 292 def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack",
 293                                               "HasRetAddrStack", "true",
 294                                               "Has return address stack">;
 295
 296 // Some processors have no branch predictor, which changes the expected cost of
 297 // taking a branch which affects the choice of whether to use predicated
 298 // instructions.
 299 def FeatureHasNoBranchPredictor : SubtargetFeature<"no-branch-predictor",
 300                                                    "HasBranchPredictor", "false",
 301                                                    "Has no branch predictor">;
 302
 303 /// DSP extension.
 304 def FeatureDSP            : SubtargetFeature<"dsp", "HasDSP", "true",
 305                                              "Supports DSP instructions in "
 306                                              "ARM and/or Thumb2">;
 307
 308 // Multiprocessing extension.
 309 def FeatureMP             : SubtargetFeature<"mp", "HasMPExtension", "true",
 310                                         "Supports Multiprocessing extension">;
 311
 312 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
 313 def FeatureVirtualization : SubtargetFeature<"virtualization",
 314                                              "HasVirtualization", "true",
 315                                              "Supports Virtualization extension",
 316                                              [FeatureHWDivThumb, FeatureHWDivARM]>;
 317
 318 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
 319 // See ARMInstrInfo.td for details.
 320 def FeatureNaClTrap       : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
 321                                              "NaCl trap">;
 322
 323 def FeatureStrictAlign    : SubtargetFeature<"strict-align",
 324                                              "StrictAlign", "true",
 325                                              "Disallow all unaligned memory "
 326                                              "access">;
 327
 328 def FeatureLongCalls      : SubtargetFeature<"long-calls", "GenLongCalls", "true",
 329                                              "Generate calls via indirect call "
 330                                              "instructions">;
 331
 332 def FeatureExecuteOnly    : SubtargetFeature<"execute-only",
 333                                              "GenExecuteOnly", "true",
 334                                              "Enable the generation of "
 335                                              "execute only code.">;
 336
 337 def FeatureReserveR9      : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
 338                                              "Reserve R9, making it unavailable"
 339                                              " as GPR">;
 340
 341 def FeatureNoMovt         : SubtargetFeature<"no-movt", "NoMovt", "true",
 342                                              "Don't use movt/movw pairs for "
 343                                              "32-bit imms">;
 344
 345 def FeatureNoNegativeImmediates
 346                           : SubtargetFeature<"no-neg-immediates",
 347                                              "NegativeImmediates", "false",
 348                                              "Convert immediates and instructions "
 349                                              "to their negated or complemented "
 350                                              "equivalent when the immediate does "
 351                                              "not fit in the encoding.">;
 352
 353 // Use the MachineScheduler for instruction scheduling for the subtarget.
 354 def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true",
 355                                         "Use the MachineScheduler">;
 356
 357 def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler",
 358     "DisablePostRAScheduler", "true",
 359     "Don't schedule again after register allocation">;
 360
 361 // Enable use of alias analysis during code generation
 362 def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
 363                                     "Use alias analysis during codegen">;
 364
 365 // Armv8.5-A extensions
 366
 367 def FeatureSB       : SubtargetFeature<"sb", "HasSB", "true",
 368   "Enable v8.5a Speculation Barrier" >;
 369
 370 //===----------------------------------------------------------------------===//
 371 // ARM architecture class
 372 //
 373
 374 // A-series ISA
 375 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
 376                                      "Is application profile ('A' series)">;
 377
 378 // R-series ISA
 379 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
 380                                      "Is realtime profile ('R' series)">;
 381
 382 // M-series ISA
 383 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
 384                                      "Is microcontroller profile ('M' series)">;
 385
 386
 387 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
 388                                      "Enable Thumb2 instructions">;
 389
 390 def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
 391                                      "Does not support ARM mode execution">;
 392
 393 //===----------------------------------------------------------------------===//
 394 // ARM ISAa.
 395 //
 396
 397 def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
 398                                    "Support ARM v4T instructions">;
 399
 400 def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
 401                                    "Support ARM v5T instructions",
 402                                    [HasV4TOps]>;
 403
 404 def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
 405                                    "Support ARM v5TE, v5TEj, and "
 406                                    "v5TExp instructions",
 407                                    [HasV5TOps]>;
 408
 409 def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
 410                                    "Support ARM v6 instructions",
 411                                    [HasV5TEOps]>;
 412
 413 def HasV6MOps   : SubtargetFeature<"v6m", "HasV6MOps", "true",
 414                                    "Support ARM v6M instructions",
 415                                    [HasV6Ops]>;
 416
 417 def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true",
 418                                          "Support ARM v8M Baseline instructions",
 419                                          [HasV6MOps]>;
 420
 421 def HasV6KOps   : SubtargetFeature<"v6k", "HasV6KOps", "true",
 422                                    "Support ARM v6k instructions",
 423                                    [HasV6Ops]>;
 424
 425 def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
 426                                    "Support ARM v6t2 instructions",
 427                                    [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>;
 428
 429 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
 430                                    "Support ARM v7 instructions",
 431                                    [HasV6T2Ops, FeaturePerfMon,
 432                                     FeatureV7Clrex]>;
 433
 434 def HasV8MMainlineOps :
 435                   SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true",
 436                                    "Support ARM v8M Mainline instructions",
 437                                    [HasV7Ops]>;
 438
 439 def HasV8Ops    : SubtargetFeature<"v8", "HasV8Ops", "true",
 440                                    "Support ARM v8 instructions",
 441                                    [HasV7Ops, FeatureAcquireRelease]>;
 442
 443 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
 444                                    "Support ARM v8.1a instructions",
 445                                    [HasV8Ops]>;
 446
 447 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
 448                                    "Support ARM v8.2a instructions",
 449                                    [HasV8_1aOps]>;
 450
 451 def HasV8_3aOps   : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
 452                                    "Support ARM v8.3a instructions",
 453                                    [HasV8_2aOps]>;
 454
 455 def HasV8_4aOps   : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
 456                                    "Support ARM v8.4a instructions",
 457                                    [HasV8_3aOps, FeatureDotProd]>;
 458
 459 def HasV8_5aOps   : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true",
 460                                    "Support ARM v8.5a instructions",
 461                                    [HasV8_4aOps, FeatureSB]>;
 462
 463 //===----------------------------------------------------------------------===//
 464 // ARM Processor subtarget features.
 465 //
 466
 467 def ProcA5      : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
 468                                    "Cortex-A5 ARM processors", []>;
 469 def ProcA7      : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
 470                                    "Cortex-A7 ARM processors", []>;
 471 def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
 472                                    "Cortex-A8 ARM processors", []>;
 473 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
 474                                    "Cortex-A9 ARM processors", []>;
 475 def ProcA12     : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
 476                                    "Cortex-A12 ARM processors", []>;
 477 def ProcA15     : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
 478                                    "Cortex-A15 ARM processors", []>;
 479 def ProcA17     : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
 480                                    "Cortex-A17 ARM processors", []>;
 481 def ProcA32     : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32",
 482                                    "Cortex-A32 ARM processors", []>;
 483 def ProcA35     : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
 484                                    "Cortex-A35 ARM processors", []>;
 485 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
 486                                    "Cortex-A53 ARM processors", []>;
 487 def ProcA55     : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
 488                                    "Cortex-A55 ARM processors", []>;
 489 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
 490                                    "Cortex-A57 ARM processors", []>;
 491 def ProcA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
 492                                    "Cortex-A72 ARM processors", []>;
 493 def ProcA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
 494                                    "Cortex-A73 ARM processors", []>;
 495 def ProcA75     : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
 496                                    "Cortex-A75 ARM processors", []>;
 497
 498 def ProcKrait   : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
 499                                    "Qualcomm Krait processors", []>;
 500 def ProcKryo    : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
 501                                    "Qualcomm Kryo processors", []>;
 502 def ProcSwift   : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
 503                                    "Swift ARM processors", []>;
 504
 505 def ProcExynos  : SubtargetFeature<"exynos", "ARMProcFamily", "Exynos",
 506                                    "Samsung Exynos processors",
 507                                    [FeatureZCZeroing,
 508                                     FeatureUseWideStrideVFP,
 509                                     FeatureUseAA,
 510                                     FeatureSplatVFPToNeon,
 511                                     FeatureSlowVGETLNi32,
 512                                     FeatureSlowVDUP32,
 513                                     FeatureSlowFPBrcc,
 514                                     FeatureProfUnpredicate,
 515                                     FeatureHWDivThumb,
 516                                     FeatureHWDivARM,
 517                                     FeatureHasSlowFPVMLx,
 518                                     FeatureHasRetAddrStack,
 519                                     FeatureFuseLiterals,
 520                                     FeatureFuseAES,
 521                                     FeatureExpandMLx,
 522                                     FeatureCrypto,
 523                                     FeatureCRC]>;
 524
 525 def ProcR4      : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
 526                                    "Cortex-R4 ARM processors", []>;
 527 def ProcR5      : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
 528                                    "Cortex-R5 ARM processors", []>;
 529 def ProcR7      : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
 530                                    "Cortex-R7 ARM processors", []>;
 531 def ProcR52     : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52",
 532                                    "Cortex-R52 ARM processors", []>;
 533
 534 def ProcM3      : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3",
 535                                    "Cortex-M3 ARM processors", []>;
 536
 537
 538 //===----------------------------------------------------------------------===//
 539 // ARM Helper classes.
 540 //
 541
 542 class Architecture<string fname, string aname, list<SubtargetFeature> features>
 543   : SubtargetFeature<fname, "ARMArch", aname,
 544                      !strconcat(aname, " architecture"), features>;
 545
 546 class ProcNoItin<string Name, list<SubtargetFeature> Features>
 547   : Processor<Name, NoItineraries, Features>;
 548
 549
 550 //===----------------------------------------------------------------------===//
 551 // ARM architectures
 552 //
 553
 554 def ARMv2     : Architecture<"armv2",     "ARMv2",    []>;
 555
 556 def ARMv2a    : Architecture<"armv2a",    "ARMv2a",   []>;
 557
 558 def ARMv3     : Architecture<"armv3",     "ARMv3",    []>;
 559
 560 def ARMv3m    : Architecture<"armv3m",    "ARMv3m",   []>;
 561
 562 def ARMv4     : Architecture<"armv4",     "ARMv4",    []>;
 563
 564 def ARMv4t    : Architecture<"armv4t",    "ARMv4t",   [HasV4TOps]>;
 565
 566 def ARMv5t    : Architecture<"armv5t",    "ARMv5t",   [HasV5TOps]>;
 567
 568 def ARMv5te   : Architecture<"armv5te",   "ARMv5te",  [HasV5TEOps]>;
 569
 570 def ARMv5tej  : Architecture<"armv5tej",  "ARMv5tej", [HasV5TEOps]>;
 571
 572 def ARMv6     : Architecture<"armv6",     "ARMv6",    [HasV6Ops,
 573                                                        FeatureDSP]>;
 574
 575 def ARMv6t2   : Architecture<"armv6t2",   "ARMv6t2",  [HasV6T2Ops,
 576                                                        FeatureDSP]>;
 577
 578 def ARMv6k    : Architecture<"armv6k",    "ARMv6k",   [HasV6KOps]>;
 579
 580 def ARMv6kz   : Architecture<"armv6kz",   "ARMv6kz",  [HasV6KOps,
 581                                                        FeatureTrustZone]>;
 582
 583 def ARMv6m    : Architecture<"armv6-m",   "ARMv6m",   [HasV6MOps,
 584                                                        FeatureNoARM,
 585                                                        ModeThumb,
 586                                                        FeatureDB,
 587                                                        FeatureMClass,
 588                                                        FeatureStrictAlign]>;
 589
 590 def ARMv6sm   : Architecture<"armv6s-m",  "ARMv6sm",  [HasV6MOps,
 591                                                        FeatureNoARM,
 592                                                        ModeThumb,
 593                                                        FeatureDB,
 594                                                        FeatureMClass,
 595                                                        FeatureStrictAlign]>;
 596
 597 def ARMv7a    : Architecture<"armv7-a",   "ARMv7a",   [HasV7Ops,
 598                                                        FeatureNEON,
 599                                                        FeatureDB,
 600                                                        FeatureDSP,
 601                                                        FeatureAClass]>;
 602
 603 def ARMv7ve   : Architecture<"armv7ve",   "ARMv7ve",  [HasV7Ops,
 604                                                        FeatureNEON,
 605                                                        FeatureDB,
 606                                                        FeatureDSP,
 607                                                        FeatureTrustZone,
 608                                                        FeatureMP,
 609                                                        FeatureVirtualization,
 610                                                        FeatureAClass]>;
 611
 612 def ARMv7r    : Architecture<"armv7-r",   "ARMv7r",   [HasV7Ops,
 613                                                        FeatureDB,
 614                                                        FeatureDSP,
 615                                                        FeatureHWDivThumb,
 616                                                        FeatureRClass]>;
 617
 618 def ARMv7m    : Architecture<"armv7-m",   "ARMv7m",   [HasV7Ops,
 619                                                        FeatureThumb2,
 620                                                        FeatureNoARM,
 621                                                        ModeThumb,
 622                                                        FeatureDB,
 623                                                        FeatureHWDivThumb,
 624                                                        FeatureMClass]>;
 625
 626 def ARMv7em   : Architecture<"armv7e-m",  "ARMv7em",  [HasV7Ops,
 627                                                        FeatureThumb2,
 628                                                        FeatureNoARM,
 629                                                        ModeThumb,
 630                                                        FeatureDB,
 631                                                        FeatureHWDivThumb,
 632                                                        FeatureMClass,
 633                                                        FeatureDSP]>;
 634
 635 def ARMv8a    : Architecture<"armv8-a",   "ARMv8a",   [HasV8Ops,
 636                                                        FeatureAClass,
 637                                                        FeatureDB,
 638                                                        FeatureFPARMv8,
 639                                                        FeatureNEON,
 640                                                        FeatureDSP,
 641                                                        FeatureTrustZone,
 642                                                        FeatureMP,
 643                                                        FeatureVirtualization,
 644                                                        FeatureCrypto,
 645                                                        FeatureCRC]>;
 646
 647 def ARMv81a   : Architecture<"armv8.1-a", "ARMv81a",  [HasV8_1aOps,
 648                                                        FeatureAClass,
 649                                                        FeatureDB,
 650                                                        FeatureFPARMv8,
 651                                                        FeatureNEON,
 652                                                        FeatureDSP,
 653                                                        FeatureTrustZone,
 654                                                        FeatureMP,
 655                                                        FeatureVirtualization,
 656                                                        FeatureCrypto,
 657                                                        FeatureCRC]>;
 658
 659 def ARMv82a   : Architecture<"armv8.2-a", "ARMv82a",  [HasV8_2aOps,
 660                                                        FeatureAClass,
 661                                                        FeatureDB,
 662                                                        FeatureFPARMv8,
 663                                                        FeatureNEON,
 664                                                        FeatureDSP,
 665                                                        FeatureTrustZone,
 666                                                        FeatureMP,
 667                                                        FeatureVirtualization,
 668                                                        FeatureCrypto,
 669                                                        FeatureCRC,
 670                                                        FeatureRAS]>;
 671
 672 def ARMv83a   : Architecture<"armv8.3-a", "ARMv83a",  [HasV8_3aOps,
 673                                                        FeatureAClass,
 674                                                        FeatureDB,
 675                                                        FeatureFPARMv8,
 676                                                        FeatureNEON,
 677                                                        FeatureDSP,
 678                                                        FeatureTrustZone,
 679                                                        FeatureMP,
 680                                                        FeatureVirtualization,
 681                                                        FeatureCrypto,
 682                                                        FeatureCRC,
 683                                                        FeatureRAS]>;
 684
 685 def ARMv84a   : Architecture<"armv8.4-a", "ARMv84a",  [HasV8_4aOps,
 686                                                        FeatureAClass,
 687                                                        FeatureDB,
 688                                                        FeatureFPARMv8,
 689                                                        FeatureNEON,
 690                                                        FeatureDSP,
 691                                                        FeatureTrustZone,
 692                                                        FeatureMP,
 693                                                        FeatureVirtualization,
 694                                                        FeatureCrypto,
 695                                                        FeatureCRC,
 696                                                        FeatureRAS,
 697                                                        FeatureDotProd]>;
 698
 699 def ARMv85a   : Architecture<"armv8.5-a", "ARMv85a",  [HasV8_5aOps,
 700                                                        FeatureAClass,
 701                                                        FeatureDB,
 702                                                        FeatureFPARMv8,
 703                                                        FeatureNEON,
 704                                                        FeatureDSP,
 705                                                        FeatureTrustZone,
 706                                                        FeatureMP,
 707                                                        FeatureVirtualization,
 708                                                        FeatureCrypto,
 709                                                        FeatureCRC,
 710                                                        FeatureRAS,
 711                                                        FeatureDotProd]>;
 712
 713 def ARMv8r    : Architecture<"armv8-r",   "ARMv8r",   [HasV8Ops,
 714                                                        FeatureRClass,
 715                                                        FeatureDB,
 716                                                        FeatureDFB,
 717                                                        FeatureDSP,
 718                                                        FeatureCRC,
 719                                                        FeatureMP,
 720                                                        FeatureVirtualization,
 721                                                        FeatureFPARMv8,
 722                                                        FeatureNEON]>;
 723
 724 def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
 725                                                       [HasV8MBaselineOps,
 726                                                        FeatureNoARM,
 727                                                        ModeThumb,
 728                                                        FeatureDB,
 729                                                        FeatureHWDivThumb,
 730                                                        FeatureV7Clrex,
 731                                                        Feature8MSecExt,
 732                                                        FeatureAcquireRelease,
 733                                                        FeatureMClass,
 734                                                        FeatureStrictAlign]>;
 735
 736 def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline",
 737                                                       [HasV8MMainlineOps,
 738                                                        FeatureNoARM,
 739                                                        ModeThumb,
 740                                                        FeatureDB,
 741                                                        FeatureHWDivThumb,
 742                                                        Feature8MSecExt,
 743                                                        FeatureAcquireRelease,
 744                                                        FeatureMClass]>;
 745
 746 // Aliases
 747 def IWMMXT   : Architecture<"iwmmxt",      "ARMv5te",  [ARMv5te]>;
 748 def IWMMXT2  : Architecture<"iwmmxt2",     "ARMv5te",  [ARMv5te]>;
 749 def XScale   : Architecture<"xscale",      "ARMv5te",  [ARMv5te]>;
 750 def ARMv6j   : Architecture<"armv6j",      "ARMv7a",   [ARMv6]>;
 751 def ARMv7k   : Architecture<"armv7k",      "ARMv7a",   [ARMv7a]>;
 752 def ARMv7s   : Architecture<"armv7s",      "ARMv7a",   [ARMv7a]>;
 753
 754
 755 //===----------------------------------------------------------------------===//
 756 // ARM schedules.
 757 //===----------------------------------------------------------------------===//
 758 //
 759 include "ARMSchedule.td"
 760
 761 //===----------------------------------------------------------------------===//
 762 // ARM processors
 763 //
 764
 765 // Dummy CPU, used to target architectures
 766 def : ProcessorModel<"generic",     CortexA8Model,      []>;
 767
 768 // FIXME: Several processors below are not using their own scheduler
 769 // model, but one of similar/previous processor. These should be fixed.
 770
 771 def : ProcNoItin<"arm8",                                [ARMv4]>;
 772 def : ProcNoItin<"arm810",                              [ARMv4]>;
 773 def : ProcNoItin<"strongarm",                           [ARMv4]>;
 774 def : ProcNoItin<"strongarm110",                        [ARMv4]>;
 775 def : ProcNoItin<"strongarm1100",                       [ARMv4]>;
 776 def : ProcNoItin<"strongarm1110",                       [ARMv4]>;
 777
 778 def : ProcNoItin<"arm7tdmi",                            [ARMv4t]>;
 779 def : ProcNoItin<"arm7tdmi-s",                          [ARMv4t]>;
 780 def : ProcNoItin<"arm710t",                             [ARMv4t]>;
 781 def : ProcNoItin<"arm720t",                             [ARMv4t]>;
 782 def : ProcNoItin<"arm9",                                [ARMv4t]>;
 783 def : ProcNoItin<"arm9tdmi",                            [ARMv4t]>;
 784 def : ProcNoItin<"arm920",                              [ARMv4t]>;
 785 def : ProcNoItin<"arm920t",                             [ARMv4t]>;
 786 def : ProcNoItin<"arm922t",                             [ARMv4t]>;
 787 def : ProcNoItin<"arm940t",                             [ARMv4t]>;
 788 def : ProcNoItin<"ep9312",                              [ARMv4t]>;
 789
 790 def : ProcNoItin<"arm10tdmi",                           [ARMv5t]>;
 791 def : ProcNoItin<"arm1020t",                            [ARMv5t]>;
 792
 793 def : ProcNoItin<"arm9e",                               [ARMv5te]>;
 794 def : ProcNoItin<"arm926ej-s",                          [ARMv5te]>;
 795 def : ProcNoItin<"arm946e-s",                           [ARMv5te]>;
 796 def : ProcNoItin<"arm966e-s",                           [ARMv5te]>;
 797 def : ProcNoItin<"arm968e-s",                           [ARMv5te]>;
 798 def : ProcNoItin<"arm10e",                              [ARMv5te]>;
 799 def : ProcNoItin<"arm1020e",                            [ARMv5te]>;
 800 def : ProcNoItin<"arm1022e",                            [ARMv5te]>;
 801 def : ProcNoItin<"xscale",                              [ARMv5te]>;
 802 def : ProcNoItin<"iwmmxt",                              [ARMv5te]>;
 803
 804 def : Processor<"arm1136j-s",       ARMV6Itineraries,   [ARMv6]>;
 805 def : Processor<"arm1136jf-s",      ARMV6Itineraries,   [ARMv6,
 806                                                          FeatureVFP2,
 807                                                          FeatureHasSlowFPVMLx]>;
 808
 809 def : Processor<"cortex-m0",        ARMV6Itineraries,   [ARMv6m]>;
 810 def : Processor<"cortex-m0plus",    ARMV6Itineraries,   [ARMv6m]>;
 811 def : Processor<"cortex-m1",        ARMV6Itineraries,   [ARMv6m]>;
 812 def : Processor<"sc000",            ARMV6Itineraries,   [ARMv6m]>;
 813
 814 def : Processor<"arm1176j-s",       ARMV6Itineraries,   [ARMv6kz]>;
 815 def : Processor<"arm1176jz-s",      ARMV6Itineraries,   [ARMv6kz]>;
 816 def : Processor<"arm1176jzf-s",     ARMV6Itineraries,   [ARMv6kz,
 817                                                          FeatureVFP2,
 818                                                          FeatureHasSlowFPVMLx]>;
 819
 820 def : Processor<"mpcorenovfp",      ARMV6Itineraries,   [ARMv6k]>;
 821 def : Processor<"mpcore",           ARMV6Itineraries,   [ARMv6k,
 822                                                          FeatureVFP2,
 823                                                          FeatureHasSlowFPVMLx]>;
 824
 825 def : Processor<"arm1156t2-s",      ARMV6Itineraries,   [ARMv6t2]>;
 826 def : Processor<"arm1156t2f-s",     ARMV6Itineraries,   [ARMv6t2,
 827                                                          FeatureVFP2,
 828                                                          FeatureHasSlowFPVMLx]>;
 829
 830 def : ProcessorModel<"cortex-a5",   CortexA8Model,      [ARMv7a, ProcA5,
 831                                                          FeatureHasRetAddrStack,
 832                                                          FeatureTrustZone,
 833                                                          FeatureSlowFPBrcc,
 834                                                          FeatureHasSlowFPVMLx,
 835                                                          FeatureVMLxForwarding,
 836                                                          FeatureMP,
 837                                                          FeatureVFP4]>;
 838
 839 def : ProcessorModel<"cortex-a7",   CortexA8Model,      [ARMv7a, ProcA7,
 840                                                          FeatureHasRetAddrStack,
 841                                                          FeatureTrustZone,
 842                                                          FeatureSlowFPBrcc,
 843                                                          FeatureHasVMLxHazards,
 844                                                          FeatureHasSlowFPVMLx,
 845                                                          FeatureVMLxForwarding,
 846                                                          FeatureMP,
 847                                                          FeatureVFP4,
 848                                                          FeatureVirtualization]>;
 849
 850 def : ProcessorModel<"cortex-a8",   CortexA8Model,      [ARMv7a, ProcA8,
 851                                                          FeatureHasRetAddrStack,
 852                                                          FeatureNonpipelinedVFP,
 853                                                          FeatureTrustZone,
 854                                                          FeatureSlowFPBrcc,
 855                                                          FeatureHasVMLxHazards,
 856                                                          FeatureHasSlowFPVMLx,
 857                                                          FeatureVMLxForwarding]>;
 858
 859 def : ProcessorModel<"cortex-a9",   CortexA9Model,      [ARMv7a, ProcA9,
 860                                                          FeatureHasRetAddrStack,
 861                                                          FeatureTrustZone,
 862                                                          FeatureHasVMLxHazards,
 863                                                          FeatureVMLxForwarding,
 864                                                          FeatureFP16,
 865                                                          FeatureAvoidPartialCPSR,
 866                                                          FeatureExpandMLx,
 867                                                          FeaturePreferVMOVSR,
 868                                                          FeatureMuxedUnits,
 869                                                          FeatureNEONForFPMovs,
 870                                                          FeatureCheckVLDnAlign,
 871                                                          FeatureMP]>;
 872
 873 def : ProcessorModel<"cortex-a12",  CortexA9Model,      [ARMv7a, ProcA12,
 874                                                          FeatureHasRetAddrStack,
 875                                                          FeatureTrustZone,
 876                                                          FeatureVMLxForwarding,
 877                                                          FeatureVFP4,
 878                                                          FeatureAvoidPartialCPSR,
 879                                                          FeatureVirtualization,
 880                                                          FeatureMP]>;
 881
 882 def : ProcessorModel<"cortex-a15",  CortexA9Model,      [ARMv7a, ProcA15,
 883                                                          FeatureDontWidenVMOVS,
 884                                                          FeatureSplatVFPToNeon,
 885                                                          FeatureHasRetAddrStack,
 886                                                          FeatureMuxedUnits,
 887                                                          FeatureTrustZone,
 888                                                          FeatureVFP4,
 889                                                          FeatureMP,
 890                                                          FeatureCheckVLDnAlign,
 891                                                          FeatureAvoidPartialCPSR,
 892                                                          FeatureVirtualization]>;
 893
 894 def : ProcessorModel<"cortex-a17",  CortexA9Model,      [ARMv7a, ProcA17,
 895                                                          FeatureHasRetAddrStack,
 896                                                          FeatureTrustZone,
 897                                                          FeatureMP,
 898                                                          FeatureVMLxForwarding,
 899                                                          FeatureVFP4,
 900                                                          FeatureAvoidPartialCPSR,
 901                                                          FeatureVirtualization]>;
 902
 903 // FIXME: krait has currently the same features as A9 plus VFP4 and  HWDiv
 904 def : ProcessorModel<"krait",       CortexA9Model,      [ARMv7a, ProcKrait,
 905                                                          FeatureHasRetAddrStack,
 906                                                          FeatureMuxedUnits,
 907                                                          FeatureCheckVLDnAlign,
 908                                                          FeatureVMLxForwarding,
 909                                                          FeatureFP16,
 910                                                          FeatureAvoidPartialCPSR,
 911                                                          FeatureVFP4,
 912                                                          FeatureHWDivThumb,
 913                                                          FeatureHWDivARM]>;
 914
 915 def : ProcessorModel<"swift",       SwiftModel,         [ARMv7a, ProcSwift,
 916                                                          FeatureHasRetAddrStack,
 917                                                          FeatureNEONForFP,
 918                                                          FeatureVFP4,
 919                                                          FeatureUseWideStrideVFP,
 920                                                          FeatureMP,
 921                                                          FeatureHWDivThumb,
 922                                                          FeatureHWDivARM,
 923                                                          FeatureAvoidPartialCPSR,
 924                                                          FeatureAvoidMOVsShOp,
 925                                                          FeatureHasSlowFPVMLx,
 926                                                          FeatureHasVMLxHazards,
 927                                                          FeatureProfUnpredicate,
 928                                                          FeaturePrefISHSTBarrier,
 929                                                          FeatureSlowOddRegister,
 930                                                          FeatureSlowLoadDSubreg,
 931                                                          FeatureSlowVGETLNi32,
 932                                                          FeatureSlowVDUP32,
 933                                                          FeatureUseMISched,
 934                                                          FeatureNoPostRASched]>;
 935
 936 def : ProcessorModel<"cortex-r4",   CortexA8Model,      [ARMv7r, ProcR4,
 937                                                          FeatureHasRetAddrStack,
 938                                                          FeatureAvoidPartialCPSR]>;
 939
 940 def : ProcessorModel<"cortex-r4f",  CortexA8Model,      [ARMv7r, ProcR4,
 941                                                          FeatureHasRetAddrStack,
 942                                                          FeatureSlowFPBrcc,
 943                                                          FeatureHasSlowFPVMLx,
 944                                                          FeatureVFP3,
 945                                                          FeatureD16,
 946                                                          FeatureAvoidPartialCPSR]>;
 947
 948 def : ProcessorModel<"cortex-r5",   CortexA8Model,      [ARMv7r, ProcR5,
 949                                                          FeatureHasRetAddrStack,
 950                                                          FeatureVFP3,
 951                                                          FeatureD16,
 952                                                          FeatureSlowFPBrcc,
 953                                                          FeatureHWDivARM,
 954                                                          FeatureHasSlowFPVMLx,
 955                                                          FeatureAvoidPartialCPSR]>;
 956
 957 def : ProcessorModel<"cortex-r7",   CortexA8Model,      [ARMv7r, ProcR7,
 958                                                          FeatureHasRetAddrStack,
 959                                                          FeatureVFP3,
 960                                                          FeatureD16,
 961                                                          FeatureFP16,
 962                                                          FeatureMP,
 963                                                          FeatureSlowFPBrcc,
 964                                                          FeatureHWDivARM,
 965                                                          FeatureHasSlowFPVMLx,
 966                                                          FeatureAvoidPartialCPSR]>;
 967
 968 def : ProcessorModel<"cortex-r8",   CortexA8Model,      [ARMv7r,
 969                                                          FeatureHasRetAddrStack,
 970                                                          FeatureVFP3,
 971                                                          FeatureD16,
 972                                                          FeatureFP16,
 973                                                          FeatureMP,
 974                                                          FeatureSlowFPBrcc,
 975                                                          FeatureHWDivARM,
 976                                                          FeatureHasSlowFPVMLx,
 977                                                          FeatureAvoidPartialCPSR]>;
 978
 979 def : ProcessorModel<"cortex-m3", CortexM3Model,        [ARMv7m,
 980                                                          ProcM3,
 981                                                          FeaturePrefLoopAlign32,
 982                                                          FeatureHasNoBranchPredictor]>;
 983
 984 def : ProcessorModel<"sc300",     CortexM3Model,        [ARMv7m,
 985                                                          ProcM3,
 986                                                          FeatureHasNoBranchPredictor]>;
 987
 988 def : ProcessorModel<"cortex-m4", CortexM3Model,        [ARMv7em,
 989                                                          FeatureVFP4,
 990                                                          FeatureVFPOnlySP,
 991                                                          FeatureD16,
 992                                                          FeaturePrefLoopAlign32,
 993                                                          FeatureHasSlowFPVMLx,
 994                                                          FeatureHasNoBranchPredictor]>;
 995
 996 def : ProcNoItin<"cortex-m7",                           [ARMv7em,
 997                                                          FeatureFPARMv8,
 998                                                          FeatureD16]>;
 999
1000 def : ProcNoItin<"cortex-m23",                          [ARMv8mBaseline,
1001                                                          FeatureNoMovt]>;
1002
1003 def : ProcessorModel<"cortex-m33", CortexM3Model,       [ARMv8mMainline,
1004                                                          FeatureDSP,
1005                                                          FeatureFPARMv8,
1006                                                          FeatureD16,
1007                                                          FeatureVFPOnlySP,
1008                                                          FeaturePrefLoopAlign32,
1009                                                          FeatureHasSlowFPVMLx,
1010                                                          FeatureHasNoBranchPredictor]>;
1011
1012 def : ProcNoItin<"cortex-a32",                           [ARMv8a,
1013                                                          FeatureHWDivThumb,
1014                                                          FeatureHWDivARM,
1015                                                          FeatureCrypto,
1016                                                          FeatureCRC]>;
1017
1018 def : ProcNoItin<"cortex-a35",                          [ARMv8a, ProcA35,
1019                                                          FeatureHWDivThumb,
1020                                                          FeatureHWDivARM,
1021                                                          FeatureCrypto,
1022                                                          FeatureCRC]>;
1023
1024 def : ProcNoItin<"cortex-a53",                          [ARMv8a, ProcA53,
1025                                                          FeatureHWDivThumb,
1026                                                          FeatureHWDivARM,
1027                                                          FeatureCrypto,
1028                                                          FeatureCRC,
1029                                                          FeatureFPAO]>;
1030
1031 def : ProcNoItin<"cortex-a55",                          [ARMv82a, ProcA55,
1032                                                          FeatureHWDivThumb,
1033                                                          FeatureHWDivARM,
1034                                                          FeatureDotProd]>;
1035
1036 def : ProcessorModel<"cortex-a57",  CortexA57Model,     [ARMv8a, ProcA57,
1037                                                          FeatureHWDivThumb,
1038                                                          FeatureHWDivARM,
1039                                                          FeatureCrypto,
1040                                                          FeatureCRC,
1041                                                          FeatureFPAO,
1042                                                          FeatureAvoidPartialCPSR,
1043                                                          FeatureCheapPredicableCPSR]>;
1044
1045 def : ProcessorModel<"cortex-a72",  CortexA57Model,     [ARMv8a, ProcA72,
1046                                                          FeatureHWDivThumb,
1047                                                          FeatureHWDivARM,
1048                                                          FeatureCrypto,
1049                                                          FeatureCRC]>;
1050
1051 def : ProcNoItin<"cortex-a73",                          [ARMv8a, ProcA73,
1052                                                          FeatureHWDivThumb,
1053                                                          FeatureHWDivARM,
1054                                                          FeatureCrypto,
1055                                                          FeatureCRC]>;
1056
1057 def : ProcNoItin<"cortex-a75",                          [ARMv82a, ProcA75,
1058                                                          FeatureHWDivThumb,
1059                                                          FeatureHWDivARM,
1060                                                          FeatureDotProd]>;
1061
1062 def : ProcessorModel<"cyclone",     SwiftModel,         [ARMv8a, ProcSwift,
1063                                                          FeatureHasRetAddrStack,
1064                                                          FeatureNEONForFP,
1065                                                          FeatureVFP4,
1066                                                          FeatureMP,
1067                                                          FeatureHWDivThumb,
1068                                                          FeatureHWDivARM,
1069                                                          FeatureAvoidPartialCPSR,
1070                                                          FeatureAvoidMOVsShOp,
1071                                                          FeatureHasSlowFPVMLx,
1072                                                          FeatureCrypto,
1073                                                          FeatureUseMISched,
1074                                                          FeatureZCZeroing,
1075                                                          FeatureNoPostRASched]>;
1076
1077 def : ProcNoItin<"exynos-m1",                           [ARMv8a, ProcExynos]>;
1078 def : ProcNoItin<"exynos-m2",                           [ARMv8a, ProcExynos]>;
1079 def : ProcNoItin<"exynos-m3",                           [ARMv8a, ProcExynos]>;
1080 def : ProcNoItin<"exynos-m4",                           [ARMv82a, ProcExynos,
1081                                                          FeatureFullFP16,
1082                                                          FeatureDotProd]>;
1083
1084 def : ProcNoItin<"kryo",                                [ARMv8a, ProcKryo,
1085                                                          FeatureHWDivThumb,
1086                                                          FeatureHWDivARM,
1087                                                          FeatureCrypto,
1088                                                          FeatureCRC]>;
1089
1090 def : ProcessorModel<"cortex-r52", CortexR52Model,      [ARMv8r, ProcR52,
1091                                                          FeatureUseMISched,
1092                                                          FeatureFPAO,
1093                                                          FeatureUseAA]>;
1094
1095 //===----------------------------------------------------------------------===//
1096 // Register File Description
1097 //===----------------------------------------------------------------------===//
1098
1099 include "ARMRegisterInfo.td"
1100 include "ARMRegisterBanks.td"
1101 include "ARMCallingConv.td"
1102
1103 //===----------------------------------------------------------------------===//
1104 // Instruction Descriptions
1105 //===----------------------------------------------------------------------===//
1106
1107 include "ARMInstrInfo.td"
1108 def ARMInstrInfo : InstrInfo;
1109
1110 //===----------------------------------------------------------------------===//
1111 // Declare the target which we are implementing
1112 //===----------------------------------------------------------------------===//
1113
1114 def ARMAsmWriter : AsmWriter {
1115   string AsmWriterClassName  = "InstPrinter";
1116   int PassSubtarget = 1;
1117   int Variant = 0;
1118   bit isMCAsmWriter = 1;
1119 }
1120
1121 def ARMAsmParser : AsmParser {
1122   bit ReportMultipleNearMisses = 1;
1123 }
1124
1125 def ARMAsmParserVariant : AsmParserVariant {
1126   int Variant = 0;
1127   string Name = "ARM";
1128   string BreakCharacters = ".";
1129 }
1130
1131 def ARM : Target {
1132   // Pull in Instruction Info.
1133   let InstructionSet = ARMInstrInfo;
1134   let AssemblyWriters = [ARMAsmWriter];
1135   let AssemblyParsers = [ARMAsmParser];
1136   let AssemblyParserVariants = [ARMAsmParserVariant];
1137   let AllowRegisterRenaming = 1;
1138 }