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Revert r354244 "[DAGCombiner] Eliminate dead stores to stack."
[llvm-complete.git] / lib / Target / ARM / ARMExpandPseudoInsts.cpp
blob680142c228899fa7d602677bd520bdfba9235558
1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a pass that expands pseudo instructions into target
10 // instructions to allow proper scheduling, if-conversion, and other late
11 // optimizations. This pass should be run after register allocation but before
12 // the post-regalloc scheduling pass.
13 //
14 //===----------------------------------------------------------------------===//
15
16 #include "ARM.h"
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMBaseRegisterInfo.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMSubtarget.h"
22 #include "MCTargetDesc/ARMAddressingModes.h"
23 #include "llvm/CodeGen/LivePhysRegs.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26
27 using namespace llvm;
28
29 #define DEBUG_TYPE "arm-pseudo"
30
31 static cl::opt<bool>
32 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
33 cl::desc("Verify machine code after expanding ARM pseudos"));
34
35 #define ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass"
36
37 namespace {
38 class ARMExpandPseudo : public MachineFunctionPass {
39 public:
40 static char ID;
41 ARMExpandPseudo() : MachineFunctionPass(ID) {}
42
43 const ARMBaseInstrInfo *TII;
44 const TargetRegisterInfo *TRI;
45 const ARMSubtarget *STI;
46 ARMFunctionInfo *AFI;
47
48 bool runOnMachineFunction(MachineFunction &Fn) override;
49
50 MachineFunctionProperties getRequiredProperties() const override {
51 return MachineFunctionProperties().set(
52 MachineFunctionProperties::Property::NoVRegs);
53 }
54
55 StringRef getPassName() const override {
56 return ARM_EXPAND_PSEUDO_NAME;
57 }
58
59 private:
60 void TransferImpOps(MachineInstr &OldMI,
61 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
62 bool ExpandMI(MachineBasicBlock &MBB,
63 MachineBasicBlock::iterator MBBI,
64 MachineBasicBlock::iterator &NextMBBI);
65 bool ExpandMBB(MachineBasicBlock &MBB);
66 void ExpandVLD(MachineBasicBlock::iterator &MBBI);
67 void ExpandVST(MachineBasicBlock::iterator &MBBI);
68 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
69 void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
70 unsigned Opc, bool IsExt);
71 void ExpandMOV32BitImm(MachineBasicBlock &MBB,
72 MachineBasicBlock::iterator &MBBI);
73 bool ExpandCMP_SWAP(MachineBasicBlock &MBB,
74 MachineBasicBlock::iterator MBBI, unsigned LdrexOp,
75 unsigned StrexOp, unsigned UxtOp,
76 MachineBasicBlock::iterator &NextMBBI);
77
78 bool ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
79 MachineBasicBlock::iterator MBBI,
80 MachineBasicBlock::iterator &NextMBBI);
81 };
82 char ARMExpandPseudo::ID = 0;
83 }
84
85 INITIALIZE_PASS(ARMExpandPseudo, DEBUG_TYPE, ARM_EXPAND_PSEUDO_NAME, false,
86 false)
87
88 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to
89 /// the instructions created from the expansion.
90 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
91 MachineInstrBuilder &UseMI,
92 MachineInstrBuilder &DefMI) {
93 const MCInstrDesc &Desc = OldMI.getDesc();
94 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
95 i != e; ++i) {
96 const MachineOperand &MO = OldMI.getOperand(i);
97 assert(MO.isReg() && MO.getReg());
98 if (MO.isUse())
99 UseMI.add(MO);
100 else
101 DefMI.add(MO);
102 }
103 }
104
105 namespace {
106 // Constants for register spacing in NEON load/store instructions.
107 // For quad-register load-lane and store-lane pseudo instructors, the
108 // spacing is initially assumed to be EvenDblSpc, and that is changed to
109 // OddDblSpc depending on the lane number operand.
110 enum NEONRegSpacing {
111 SingleSpc,
112 SingleLowSpc , // Single spacing, low registers, three and four vectors.
113 SingleHighQSpc, // Single spacing, high registers, four vectors.
114 SingleHighTSpc, // Single spacing, high registers, three vectors.
115 EvenDblSpc,
116 OddDblSpc
117 };
118
119 // Entries for NEON load/store information table. The table is sorted by
120 // PseudoOpc for fast binary-search lookups.
121 struct NEONLdStTableEntry {
122 uint16_t PseudoOpc;
123 uint16_t RealOpc;
124 bool IsLoad;
125 bool isUpdating;
126 bool hasWritebackOperand;
127 uint8_t RegSpacing; // One of type NEONRegSpacing
128 uint8_t NumRegs; // D registers loaded or stored
129 uint8_t RegElts; // elements per D register; used for lane ops
130 // FIXME: Temporary flag to denote whether the real instruction takes
131 // a single register (like the encoding) or all of the registers in
132 // the list (like the asm syntax and the isel DAG). When all definitions
133 // are converted to take only the single encoded register, this will
134 // go away.
135 bool copyAllListRegs;
136
137 // Comparison methods for binary search of the table.
138 bool operator<(const NEONLdStTableEntry &TE) const {
139 return PseudoOpc < TE.PseudoOpc;
140 }
141 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
142 return TE.PseudoOpc < PseudoOpc;
143 }
144 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
145 const NEONLdStTableEntry &TE) {
146 return PseudoOpc < TE.PseudoOpc;
147 }
148 };
149 }
150
151 static const NEONLdStTableEntry NEONLdStTable[] = {
152 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
153 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
154 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
155 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
156 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
157 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
158
159 { ARM::VLD1d16QPseudo, ARM::VLD1d16Q, true, false, false, SingleSpc, 4, 4 ,false},
160 { ARM::VLD1d16TPseudo, ARM::VLD1d16T, true, false, false, SingleSpc, 3, 4 ,false},
161 { ARM::VLD1d32QPseudo, ARM::VLD1d32Q, true, false, false, SingleSpc, 4, 2 ,false},
162 { ARM::VLD1d32TPseudo, ARM::VLD1d32T, true, false, false, SingleSpc, 3, 2 ,false},
163 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
164 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,false},
165 { ARM::VLD1d64QPseudoWB_register, ARM::VLD1d64Qwb_register, true, true, true, SingleSpc, 4, 1 ,false},
166 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
167 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,false},
168 { ARM::VLD1d64TPseudoWB_register, ARM::VLD1d64Twb_register, true, true, true, SingleSpc, 3, 1 ,false},
169 { ARM::VLD1d8QPseudo, ARM::VLD1d8Q, true, false, false, SingleSpc, 4, 8 ,false},
170 { ARM::VLD1d8TPseudo, ARM::VLD1d8T, true, false, false, SingleSpc, 3, 8 ,false},
171 { ARM::VLD1q16HighQPseudo, ARM::VLD1d16Q, true, false, false, SingleHighQSpc, 4, 4 ,false},
172 { ARM::VLD1q16HighTPseudo, ARM::VLD1d16T, true, false, false, SingleHighTSpc, 3, 4 ,false},
173 { ARM::VLD1q16LowQPseudo_UPD, ARM::VLD1d16Qwb_fixed, true, true, true, SingleLowSpc, 4, 4 ,false},
174 { ARM::VLD1q16LowTPseudo_UPD, ARM::VLD1d16Twb_fixed, true, true, true, SingleLowSpc, 3, 4 ,false},
175 { ARM::VLD1q32HighQPseudo, ARM::VLD1d32Q, true, false, false, SingleHighQSpc, 4, 2 ,false},
176 { ARM::VLD1q32HighTPseudo, ARM::VLD1d32T, true, false, false, SingleHighTSpc, 3, 2 ,false},
177 { ARM::VLD1q32LowQPseudo_UPD, ARM::VLD1d32Qwb_fixed, true, true, true, SingleLowSpc, 4, 2 ,false},
178 { ARM::VLD1q32LowTPseudo_UPD, ARM::VLD1d32Twb_fixed, true, true, true, SingleLowSpc, 3, 2 ,false},
179 { ARM::VLD1q64HighQPseudo, ARM::VLD1d64Q, true, false, false, SingleHighQSpc, 4, 1 ,false},
180 { ARM::VLD1q64HighTPseudo, ARM::VLD1d64T, true, false, false, SingleHighTSpc, 3, 1 ,false},
181 { ARM::VLD1q64LowQPseudo_UPD, ARM::VLD1d64Qwb_fixed, true, true, true, SingleLowSpc, 4, 1 ,false},
182 { ARM::VLD1q64LowTPseudo_UPD, ARM::VLD1d64Twb_fixed, true, true, true, SingleLowSpc, 3, 1 ,false},
183 { ARM::VLD1q8HighQPseudo, ARM::VLD1d8Q, true, false, false, SingleHighQSpc, 4, 8 ,false},
184 { ARM::VLD1q8HighTPseudo, ARM::VLD1d8T, true, false, false, SingleHighTSpc, 3, 8 ,false},
185 { ARM::VLD1q8LowQPseudo_UPD, ARM::VLD1d8Qwb_fixed, true, true, true, SingleLowSpc, 4, 8 ,false},
186 { ARM::VLD1q8LowTPseudo_UPD, ARM::VLD1d8Twb_fixed, true, true, true, SingleLowSpc, 3, 8 ,false},
187
188 { ARM::VLD2DUPq16EvenPseudo, ARM::VLD2DUPd16x2, true, false, false, EvenDblSpc, 2, 4 ,false},
189 { ARM::VLD2DUPq16OddPseudo, ARM::VLD2DUPd16x2, true, false, false, OddDblSpc, 2, 4 ,false},
190 { ARM::VLD2DUPq32EvenPseudo, ARM::VLD2DUPd32x2, true, false, false, EvenDblSpc, 2, 2 ,false},
191 { ARM::VLD2DUPq32OddPseudo, ARM::VLD2DUPd32x2, true, false, false, OddDblSpc, 2, 2 ,false},
192 { ARM::VLD2DUPq8EvenPseudo, ARM::VLD2DUPd8x2, true, false, false, EvenDblSpc, 2, 8 ,false},
193 { ARM::VLD2DUPq8OddPseudo, ARM::VLD2DUPd8x2, true, false, false, OddDblSpc, 2, 8 ,false},
194
195 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true},
196 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true},
197 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true},
198 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true},
199 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true},
200 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true},
201 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true},
202 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true},
203 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true},
204 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true},
205
206 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false},
207 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false},
208 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false},
209 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false},
210 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false},
211 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false},
212 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false},
213 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false},
214 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false},
215
216 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true},
217 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true},
218 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true},
219 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true},
220 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true},
221 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true},
222 { ARM::VLD3DUPq16EvenPseudo, ARM::VLD3DUPq16, true, false, false, EvenDblSpc, 3, 4 ,true},
223 { ARM::VLD3DUPq16OddPseudo, ARM::VLD3DUPq16, true, false, false, OddDblSpc, 3, 4 ,true},
224 { ARM::VLD3DUPq32EvenPseudo, ARM::VLD3DUPq32, true, false, false, EvenDblSpc, 3, 2 ,true},
225 { ARM::VLD3DUPq32OddPseudo, ARM::VLD3DUPq32, true, false, false, OddDblSpc, 3, 2 ,true},
226 { ARM::VLD3DUPq8EvenPseudo, ARM::VLD3DUPq8, true, false, false, EvenDblSpc, 3, 8 ,true},
227 { ARM::VLD3DUPq8OddPseudo, ARM::VLD3DUPq8, true, false, false, OddDblSpc, 3, 8 ,true},
228
229 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true},
230 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
231 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true},
232 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
233 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true},
234 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
235 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true},
236 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
237 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true},
238 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
239
240 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true},
241 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
242 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true},
243 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
244 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true},
245 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
246
247 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
248 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true},
249 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true},
250 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
251 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true},
252 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true},
253 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true},
254 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true},
255 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true},
256
257 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true},
258 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true},
259 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true},
260 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true},
261 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true},
262 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true},
263 { ARM::VLD4DUPq16EvenPseudo, ARM::VLD4DUPq16, true, false, false, EvenDblSpc, 4, 4 ,true},
264 { ARM::VLD4DUPq16OddPseudo, ARM::VLD4DUPq16, true, false, false, OddDblSpc, 4, 4 ,true},
265 { ARM::VLD4DUPq32EvenPseudo, ARM::VLD4DUPq32, true, false, false, EvenDblSpc, 4, 2 ,true},
266 { ARM::VLD4DUPq32OddPseudo, ARM::VLD4DUPq32, true, false, false, OddDblSpc, 4, 2 ,true},
267 { ARM::VLD4DUPq8EvenPseudo, ARM::VLD4DUPq8, true, false, false, EvenDblSpc, 4, 8 ,true},
268 { ARM::VLD4DUPq8OddPseudo, ARM::VLD4DUPq8, true, false, false, OddDblSpc, 4, 8 ,true},
269
270 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true},
271 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
272 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true},
273 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
274 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true},
275 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
276 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true},
277 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
278 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true},
279 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
280
281 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true},
282 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
283 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true},
284 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
285 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true},
286 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
287
288 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
289 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true},
290 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true},
291 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
292 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true},
293 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true},
294 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true},
295 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true},
296 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true},
297
298 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true},
299 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true},
300 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true},
301 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true},
302 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true},
303 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true},
304
305 { ARM::VST1d16QPseudo, ARM::VST1d16Q, false, false, false, SingleSpc, 4, 4 ,false},
306 { ARM::VST1d16TPseudo, ARM::VST1d16T, false, false, false, SingleSpc, 3, 4 ,false},
307 { ARM::VST1d32QPseudo, ARM::VST1d32Q, false, false, false, SingleSpc, 4, 2 ,false},
308 { ARM::VST1d32TPseudo, ARM::VST1d32T, false, false, false, SingleSpc, 3, 2 ,false},
309 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false},
310 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false},
311 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false},
312 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false},
313 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false},
314 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false},
315 { ARM::VST1d8QPseudo, ARM::VST1d8Q, false, false, false, SingleSpc, 4, 8 ,false},
316 { ARM::VST1d8TPseudo, ARM::VST1d8T, false, false, false, SingleSpc, 3, 8 ,false},
317 { ARM::VST1q16HighQPseudo, ARM::VST1d16Q, false, false, false, SingleHighQSpc, 4, 4 ,false},
318 { ARM::VST1q16HighTPseudo, ARM::VST1d16T, false, false, false, SingleHighTSpc, 3, 4 ,false},
319 { ARM::VST1q16LowQPseudo_UPD, ARM::VST1d16Qwb_fixed, false, true, true, SingleLowSpc, 4, 4 ,false},
320 { ARM::VST1q16LowTPseudo_UPD, ARM::VST1d16Twb_fixed, false, true, true, SingleLowSpc, 3, 4 ,false},
321 { ARM::VST1q32HighQPseudo, ARM::VST1d32Q, false, false, false, SingleHighQSpc, 4, 2 ,false},
322 { ARM::VST1q32HighTPseudo, ARM::VST1d32T, false, false, false, SingleHighTSpc, 3, 2 ,false},
323 { ARM::VST1q32LowQPseudo_UPD, ARM::VST1d32Qwb_fixed, false, true, true, SingleLowSpc, 4, 2 ,false},
324 { ARM::VST1q32LowTPseudo_UPD, ARM::VST1d32Twb_fixed, false, true, true, SingleLowSpc, 3, 2 ,false},
325 { ARM::VST1q64HighQPseudo, ARM::VST1d64Q, false, false, false, SingleHighQSpc, 4, 1 ,false},
326 { ARM::VST1q64HighTPseudo, ARM::VST1d64T, false, false, false, SingleHighTSpc, 3, 1 ,false},
327 { ARM::VST1q64LowQPseudo_UPD, ARM::VST1d64Qwb_fixed, false, true, true, SingleLowSpc, 4, 1 ,false},
328 { ARM::VST1q64LowTPseudo_UPD, ARM::VST1d64Twb_fixed, false, true, true, SingleLowSpc, 3, 1 ,false},
329 { ARM::VST1q8HighQPseudo, ARM::VST1d8Q, false, false, false, SingleHighQSpc, 4, 8 ,false},
330 { ARM::VST1q8HighTPseudo, ARM::VST1d8T, false, false, false, SingleHighTSpc, 3, 8 ,false},
331 { ARM::VST1q8LowQPseudo_UPD, ARM::VST1d8Qwb_fixed, false, true, true, SingleLowSpc, 4, 8 ,false},
332 { ARM::VST1q8LowTPseudo_UPD, ARM::VST1d8Twb_fixed, false, true, true, SingleLowSpc, 3, 8 ,false},
333
334 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true},
335 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true},
336 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true},
337 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true},
338 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true},
339 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true},
340 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true},
341 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true},
342 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true},
343 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true},
344
345 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false},
346 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
347 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false},
348 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false},
349 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false},
350 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false},
351 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false},
352 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false},
353 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false},
354
355 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true},
356 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
357 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true},
358 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
359 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true},
360 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
361 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true},
362 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true},
363 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true},
364 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true},
365
366 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true},
367 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
368 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true},
369 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
370 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true},
371 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
372
373 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true},
374 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true},
375 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true},
376 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true},
377 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true},
378 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true},
379 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true},
380 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true},
381 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true},
382
383 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true},
384 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
385 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true},
386 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
387 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true},
388 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
389 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true},
390 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true},
391 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true},
392 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true},
393
394 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true},
395 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
396 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true},
397 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
398 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true},
399 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
400
401 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true},
402 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true},
403 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true},
404 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true},
405 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true},
406 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true},
407 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true},
408 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true},
409 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true}
410 };
411
412 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
413 /// load or store pseudo instruction.
414 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
415 #ifndef NDEBUG
416 // Make sure the table is sorted.
417 static std::atomic<bool> TableChecked(false);
418 if (!TableChecked.load(std::memory_order_relaxed)) {
419 assert(std::is_sorted(std::begin(NEONLdStTable), std::end(NEONLdStTable)) &&
420 "NEONLdStTable is not sorted!");
421 TableChecked.store(true, std::memory_order_relaxed);
422 }
423 #endif
424
425 auto I = std::lower_bound(std::begin(NEONLdStTable),
426 std::end(NEONLdStTable), Opcode);
427 if (I != std::end(NEONLdStTable) && I->PseudoOpc == Opcode)
428 return I;
429 return nullptr;
430 }
431
432 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
433 /// corresponding to the specified register spacing. Not all of the results
434 /// are necessarily valid, e.g., a Q register only has 2 D subregisters.
435 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
436 const TargetRegisterInfo *TRI, unsigned &D0,
437 unsigned &D1, unsigned &D2, unsigned &D3) {
438 if (RegSpc == SingleSpc || RegSpc == SingleLowSpc) {
439 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
440 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
441 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
442 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
443 } else if (RegSpc == SingleHighQSpc) {
444 D0 = TRI->getSubReg(Reg, ARM::dsub_4);
445 D1 = TRI->getSubReg(Reg, ARM::dsub_5);
446 D2 = TRI->getSubReg(Reg, ARM::dsub_6);
447 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
448 } else if (RegSpc == SingleHighTSpc) {
449 D0 = TRI->getSubReg(Reg, ARM::dsub_3);
450 D1 = TRI->getSubReg(Reg, ARM::dsub_4);
451 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
452 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
453 } else if (RegSpc == EvenDblSpc) {
454 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
455 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
456 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
457 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
458 } else {
459 assert(RegSpc == OddDblSpc && "unknown register spacing");
460 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
461 D1 = TRI->getSubReg(Reg, ARM::dsub_3);
462 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
463 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
464 }
465 }
466
467 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
468 /// operands to real VLD instructions with D register operands.
469 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
470 MachineInstr &MI = *MBBI;
471 MachineBasicBlock &MBB = *MI.getParent();
472
473 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
474 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
475 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
476 unsigned NumRegs = TableEntry->NumRegs;
477
478 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
479 TII->get(TableEntry->RealOpc));
480 unsigned OpIdx = 0;
481
482 bool DstIsDead = MI.getOperand(OpIdx).isDead();
483 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
484 if(TableEntry->RealOpc == ARM::VLD2DUPd8x2 ||
485 TableEntry->RealOpc == ARM::VLD2DUPd16x2 ||
486 TableEntry->RealOpc == ARM::VLD2DUPd32x2) {
487 unsigned SubRegIndex;
488 if (RegSpc == EvenDblSpc) {
489 SubRegIndex = ARM::dsub_0;
490 } else {
491 assert(RegSpc == OddDblSpc && "Unexpected spacing!");
492 SubRegIndex = ARM::dsub_1;
493 }
494 unsigned SubReg = TRI->getSubReg(DstReg, SubRegIndex);
495 unsigned DstRegPair = TRI->getMatchingSuperReg(SubReg, ARM::dsub_0,
496 &ARM::DPairSpcRegClass);
497 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead));
498 } else {
499 unsigned D0, D1, D2, D3;
500 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
501 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
502 if (NumRegs > 1 && TableEntry->copyAllListRegs)
503 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
504 if (NumRegs > 2 && TableEntry->copyAllListRegs)
505 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
506 if (NumRegs > 3 && TableEntry->copyAllListRegs)
507 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
508 }
509
510 if (TableEntry->isUpdating)
511 MIB.add(MI.getOperand(OpIdx++));
512
513 // Copy the addrmode6 operands.
514 MIB.add(MI.getOperand(OpIdx++));
515 MIB.add(MI.getOperand(OpIdx++));
516
517 // Copy the am6offset operand.
518 if (TableEntry->hasWritebackOperand) {
519 // TODO: The writing-back pseudo instructions we translate here are all
520 // defined to take am6offset nodes that are capable to represent both fixed
521 // and register forms. Some real instructions, however, do not rely on
522 // am6offset and have separate definitions for such forms. When this is the
523 // case, fixed forms do not take any offset nodes, so here we skip them for
524 // such instructions. Once all real and pseudo writing-back instructions are
525 // rewritten without use of am6offset nodes, this code will go away.
526 const MachineOperand &AM6Offset = MI.getOperand(OpIdx++);
527 if (TableEntry->RealOpc == ARM::VLD1d8Qwb_fixed ||
528 TableEntry->RealOpc == ARM::VLD1d16Qwb_fixed ||
529 TableEntry->RealOpc == ARM::VLD1d32Qwb_fixed ||
530 TableEntry->RealOpc == ARM::VLD1d64Qwb_fixed ||
531 TableEntry->RealOpc == ARM::VLD1d8Twb_fixed ||
532 TableEntry->RealOpc == ARM::VLD1d16Twb_fixed ||
533 TableEntry->RealOpc == ARM::VLD1d32Twb_fixed ||
534 TableEntry->RealOpc == ARM::VLD1d64Twb_fixed) {
535 assert(AM6Offset.getReg() == 0 &&
536 "A fixed writing-back pseudo instruction provides an offset "
537 "register!");
538 } else {
539 MIB.add(AM6Offset);
540 }
541 }
542
543 // For an instruction writing double-spaced subregs, the pseudo instruction
544 // has an extra operand that is a use of the super-register. Record the
545 // operand index and skip over it.
546 unsigned SrcOpIdx = 0;
547 if(TableEntry->RealOpc != ARM::VLD2DUPd8x2 &&
548 TableEntry->RealOpc != ARM::VLD2DUPd16x2 &&
549 TableEntry->RealOpc != ARM::VLD2DUPd32x2) {
550 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc ||
551 RegSpc == SingleLowSpc || RegSpc == SingleHighQSpc ||
552 RegSpc == SingleHighTSpc)
553 SrcOpIdx = OpIdx++;
554 }
555
556 // Copy the predicate operands.
557 MIB.add(MI.getOperand(OpIdx++));
558 MIB.add(MI.getOperand(OpIdx++));
559
560 // Copy the super-register source operand used for double-spaced subregs over
561 // to the new instruction as an implicit operand.
562 if (SrcOpIdx != 0) {
563 MachineOperand MO = MI.getOperand(SrcOpIdx);
564 MO.setImplicit(true);
565 MIB.add(MO);
566 }
567 // Add an implicit def for the super-register.
568 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
569 TransferImpOps(MI, MIB, MIB);
570
571 // Transfer memoperands.
572 MIB.cloneMemRefs(MI);
573
574 MI.eraseFromParent();
575 }
576
577 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
578 /// operands to real VST instructions with D register operands.
579 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
580 MachineInstr &MI = *MBBI;
581 MachineBasicBlock &MBB = *MI.getParent();
582
583 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
584 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
585 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
586 unsigned NumRegs = TableEntry->NumRegs;
587
588 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
589 TII->get(TableEntry->RealOpc));
590 unsigned OpIdx = 0;
591 if (TableEntry->isUpdating)
592 MIB.add(MI.getOperand(OpIdx++));
593
594 // Copy the addrmode6 operands.
595 MIB.add(MI.getOperand(OpIdx++));
596 MIB.add(MI.getOperand(OpIdx++));
597
598 if (TableEntry->hasWritebackOperand) {
599 // TODO: The writing-back pseudo instructions we translate here are all
600 // defined to take am6offset nodes that are capable to represent both fixed
601 // and register forms. Some real instructions, however, do not rely on
602 // am6offset and have separate definitions for such forms. When this is the
603 // case, fixed forms do not take any offset nodes, so here we skip them for
604 // such instructions. Once all real and pseudo writing-back instructions are
605 // rewritten without use of am6offset nodes, this code will go away.
606 const MachineOperand &AM6Offset = MI.getOperand(OpIdx++);
607 if (TableEntry->RealOpc == ARM::VST1d8Qwb_fixed ||
608 TableEntry->RealOpc == ARM::VST1d16Qwb_fixed ||
609 TableEntry->RealOpc == ARM::VST1d32Qwb_fixed ||
610 TableEntry->RealOpc == ARM::VST1d64Qwb_fixed ||
611 TableEntry->RealOpc == ARM::VST1d8Twb_fixed ||
612 TableEntry->RealOpc == ARM::VST1d16Twb_fixed ||
613 TableEntry->RealOpc == ARM::VST1d32Twb_fixed ||
614 TableEntry->RealOpc == ARM::VST1d64Twb_fixed) {
615 assert(AM6Offset.getReg() == 0 &&
616 "A fixed writing-back pseudo instruction provides an offset "
617 "register!");
618 } else {
619 MIB.add(AM6Offset);
620 }
621 }
622
623 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
624 bool SrcIsUndef = MI.getOperand(OpIdx).isUndef();
625 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
626 unsigned D0, D1, D2, D3;
627 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
628 MIB.addReg(D0, getUndefRegState(SrcIsUndef));
629 if (NumRegs > 1 && TableEntry->copyAllListRegs)
630 MIB.addReg(D1, getUndefRegState(SrcIsUndef));
631 if (NumRegs > 2 && TableEntry->copyAllListRegs)
632 MIB.addReg(D2, getUndefRegState(SrcIsUndef));
633 if (NumRegs > 3 && TableEntry->copyAllListRegs)
634 MIB.addReg(D3, getUndefRegState(SrcIsUndef));
635
636 // Copy the predicate operands.
637 MIB.add(MI.getOperand(OpIdx++));
638 MIB.add(MI.getOperand(OpIdx++));
639
640 if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg.
641 MIB->addRegisterKilled(SrcReg, TRI, true);
642 else if (!SrcIsUndef)
643 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg.
644 TransferImpOps(MI, MIB, MIB);
645
646 // Transfer memoperands.
647 MIB.cloneMemRefs(MI);
648
649 MI.eraseFromParent();
650 }
651
652 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
653 /// register operands to real instructions with D register operands.
654 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
655 MachineInstr &MI = *MBBI;
656 MachineBasicBlock &MBB = *MI.getParent();
657
658 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
659 assert(TableEntry && "NEONLdStTable lookup failed");
660 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
661 unsigned NumRegs = TableEntry->NumRegs;
662 unsigned RegElts = TableEntry->RegElts;
663
664 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
665 TII->get(TableEntry->RealOpc));
666 unsigned OpIdx = 0;
667 // The lane operand is always the 3rd from last operand, before the 2
668 // predicate operands.
669 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
670
671 // Adjust the lane and spacing as needed for Q registers.
672 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
673 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
674 RegSpc = OddDblSpc;
675 Lane -= RegElts;
676 }
677 assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
678
679 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
680 unsigned DstReg = 0;
681 bool DstIsDead = false;
682 if (TableEntry->IsLoad) {
683 DstIsDead = MI.getOperand(OpIdx).isDead();
684 DstReg = MI.getOperand(OpIdx++).getReg();
685 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
686 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
687 if (NumRegs > 1)
688 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
689 if (NumRegs > 2)
690 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
691 if (NumRegs > 3)
692 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
693 }
694
695 if (TableEntry->isUpdating)
696 MIB.add(MI.getOperand(OpIdx++));
697
698 // Copy the addrmode6 operands.
699 MIB.add(MI.getOperand(OpIdx++));
700 MIB.add(MI.getOperand(OpIdx++));
701 // Copy the am6offset operand.
702 if (TableEntry->hasWritebackOperand)
703 MIB.add(MI.getOperand(OpIdx++));
704
705 // Grab the super-register source.
706 MachineOperand MO = MI.getOperand(OpIdx++);
707 if (!TableEntry->IsLoad)
708 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
709
710 // Add the subregs as sources of the new instruction.
711 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
712 getKillRegState(MO.isKill()));
713 MIB.addReg(D0, SrcFlags);
714 if (NumRegs > 1)
715 MIB.addReg(D1, SrcFlags);
716 if (NumRegs > 2)
717 MIB.addReg(D2, SrcFlags);
718 if (NumRegs > 3)
719 MIB.addReg(D3, SrcFlags);
720
721 // Add the lane number operand.
722 MIB.addImm(Lane);
723 OpIdx += 1;
724
725 // Copy the predicate operands.
726 MIB.add(MI.getOperand(OpIdx++));
727 MIB.add(MI.getOperand(OpIdx++));
728
729 // Copy the super-register source to be an implicit source.
730 MO.setImplicit(true);
731 MIB.add(MO);
732 if (TableEntry->IsLoad)
733 // Add an implicit def for the super-register.
734 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
735 TransferImpOps(MI, MIB, MIB);
736 // Transfer memoperands.
737 MIB.cloneMemRefs(MI);
738 MI.eraseFromParent();
739 }
740
741 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
742 /// register operands to real instructions with D register operands.
743 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
744 unsigned Opc, bool IsExt) {
745 MachineInstr &MI = *MBBI;
746 MachineBasicBlock &MBB = *MI.getParent();
747
748 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
749 unsigned OpIdx = 0;
750
751 // Transfer the destination register operand.
752 MIB.add(MI.getOperand(OpIdx++));
753 if (IsExt) {
754 MachineOperand VdSrc(MI.getOperand(OpIdx++));
755 MIB.add(VdSrc);
756 }
757
758 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
759 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
760 unsigned D0, D1, D2, D3;
761 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
762 MIB.addReg(D0);
763
764 // Copy the other source register operand.
765 MachineOperand VmSrc(MI.getOperand(OpIdx++));
766 MIB.add(VmSrc);
767
768 // Copy the predicate operands.
769 MIB.add(MI.getOperand(OpIdx++));
770 MIB.add(MI.getOperand(OpIdx++));
771
772 // Add an implicit kill and use for the super-reg.
773 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill));
774 TransferImpOps(MI, MIB, MIB);
775 MI.eraseFromParent();
776 }
777
778 static bool IsAnAddressOperand(const MachineOperand &MO) {
779 // This check is overly conservative. Unless we are certain that the machine
780 // operand is not a symbol reference, we return that it is a symbol reference.
781 // This is important as the load pair may not be split up Windows.
782 switch (MO.getType()) {
783 case MachineOperand::MO_Register:
784 case MachineOperand::MO_Immediate:
785 case MachineOperand::MO_CImmediate:
786 case MachineOperand::MO_FPImmediate:
787 return false;
788 case MachineOperand::MO_MachineBasicBlock:
789 return true;
790 case MachineOperand::MO_FrameIndex:
791 return false;
792 case MachineOperand::MO_ConstantPoolIndex:
793 case MachineOperand::MO_TargetIndex:
794 case MachineOperand::MO_JumpTableIndex:
795 case MachineOperand::MO_ExternalSymbol:
796 case MachineOperand::MO_GlobalAddress:
797 case MachineOperand::MO_BlockAddress:
798 return true;
799 case MachineOperand::MO_RegisterMask:
800 case MachineOperand::MO_RegisterLiveOut:
801 return false;
802 case MachineOperand::MO_Metadata:
803 case MachineOperand::MO_MCSymbol:
804 return true;
805 case MachineOperand::MO_CFIIndex:
806 return false;
807 case MachineOperand::MO_IntrinsicID:
808 case MachineOperand::MO_Predicate:
809 llvm_unreachable("should not exist post-isel");
810 }
811 llvm_unreachable("unhandled machine operand type");
812 }
813
814 static MachineOperand makeImplicit(const MachineOperand &MO) {
815 MachineOperand NewMO = MO;
816 NewMO.setImplicit();
817 return NewMO;
818 }
819
820 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
821 MachineBasicBlock::iterator &MBBI) {
822 MachineInstr &MI = *MBBI;
823 unsigned Opcode = MI.getOpcode();
824 unsigned PredReg = 0;
825 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
826 unsigned DstReg = MI.getOperand(0).getReg();
827 bool DstIsDead = MI.getOperand(0).isDead();
828 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
829 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
830 bool RequiresBundling = STI->isTargetWindows() && IsAnAddressOperand(MO);
831 MachineInstrBuilder LO16, HI16;
832
833 if (!STI->hasV6T2Ops() &&
834 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
835 // FIXME Windows CE supports older ARM CPUs
836 assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+");
837
838 // Expand into a movi + orr.
839 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
840 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
841 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
842 .addReg(DstReg);
843
844 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
845 unsigned ImmVal = (unsigned)MO.getImm();
846 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
847 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
848 LO16 = LO16.addImm(SOImmValV1);
849 HI16 = HI16.addImm(SOImmValV2);
850 LO16.cloneMemRefs(MI);
851 HI16.cloneMemRefs(MI);
852 LO16.addImm(Pred).addReg(PredReg).add(condCodeOp());
853 HI16.addImm(Pred).addReg(PredReg).add(condCodeOp());
854 if (isCC)
855 LO16.add(makeImplicit(MI.getOperand(1)));
856 TransferImpOps(MI, LO16, HI16);
857 MI.eraseFromParent();
858 return;
859 }
860
861 unsigned LO16Opc = 0;
862 unsigned HI16Opc = 0;
863 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
864 LO16Opc = ARM::t2MOVi16;
865 HI16Opc = ARM::t2MOVTi16;
866 } else {
867 LO16Opc = ARM::MOVi16;
868 HI16Opc = ARM::MOVTi16;
869 }
870
871 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
872 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
873 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
874 .addReg(DstReg);
875
876 switch (MO.getType()) {
877 case MachineOperand::MO_Immediate: {
878 unsigned Imm = MO.getImm();
879 unsigned Lo16 = Imm & 0xffff;
880 unsigned Hi16 = (Imm >> 16) & 0xffff;
881 LO16 = LO16.addImm(Lo16);
882 HI16 = HI16.addImm(Hi16);
883 break;
884 }
885 case MachineOperand::MO_ExternalSymbol: {
886 const char *ES = MO.getSymbolName();
887 unsigned TF = MO.getTargetFlags();
888 LO16 = LO16.addExternalSymbol(ES, TF | ARMII::MO_LO16);
889 HI16 = HI16.addExternalSymbol(ES, TF | ARMII::MO_HI16);
890 break;
891 }
892 default: {
893 const GlobalValue *GV = MO.getGlobal();
894 unsigned TF = MO.getTargetFlags();
895 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
896 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
897 break;
898 }
899 }
900
901 LO16.cloneMemRefs(MI);
902 HI16.cloneMemRefs(MI);
903 LO16.addImm(Pred).addReg(PredReg);
904 HI16.addImm(Pred).addReg(PredReg);
905
906 if (RequiresBundling)
907 finalizeBundle(MBB, LO16->getIterator(), MBBI->getIterator());
908
909 if (isCC)
910 LO16.add(makeImplicit(MI.getOperand(1)));
911 TransferImpOps(MI, LO16, HI16);
912 MI.eraseFromParent();
913 }
914
915 /// Expand a CMP_SWAP pseudo-inst to an ldrex/strex loop as simply as
916 /// possible. This only gets used at -O0 so we don't care about efficiency of
917 /// the generated code.
918 bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB,
919 MachineBasicBlock::iterator MBBI,
920 unsigned LdrexOp, unsigned StrexOp,
921 unsigned UxtOp,
922 MachineBasicBlock::iterator &NextMBBI) {
923 bool IsThumb = STI->isThumb();
924 MachineInstr &MI = *MBBI;
925 DebugLoc DL = MI.getDebugLoc();
926 const MachineOperand &Dest = MI.getOperand(0);
927 unsigned TempReg = MI.getOperand(1).getReg();
928 // Duplicating undef operands into 2 instructions does not guarantee the same
929 // value on both; However undef should be replaced by xzr anyway.
930 assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
931 unsigned AddrReg = MI.getOperand(2).getReg();
932 unsigned DesiredReg = MI.getOperand(3).getReg();
933 unsigned NewReg = MI.getOperand(4).getReg();
934
935 MachineFunction *MF = MBB.getParent();
936 auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
937 auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
938 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
939
940 MF->insert(++MBB.getIterator(), LoadCmpBB);
941 MF->insert(++LoadCmpBB->getIterator(), StoreBB);
942 MF->insert(++StoreBB->getIterator(), DoneBB);
943
944 if (UxtOp) {
945 MachineInstrBuilder MIB =
946 BuildMI(MBB, MBBI, DL, TII->get(UxtOp), DesiredReg)
947 .addReg(DesiredReg, RegState::Kill);
948 if (!IsThumb)
949 MIB.addImm(0);
950 MIB.add(predOps(ARMCC::AL));
951 }
952
953 // .Lloadcmp:
954 // ldrex rDest, [rAddr]
955 // cmp rDest, rDesired
956 // bne .Ldone
957
958 MachineInstrBuilder MIB;
959 MIB = BuildMI(LoadCmpBB, DL, TII->get(LdrexOp), Dest.getReg());
960 MIB.addReg(AddrReg);
961 if (LdrexOp == ARM::t2LDREX)
962 MIB.addImm(0); // a 32-bit Thumb ldrex (only) allows an offset.
963 MIB.add(predOps(ARMCC::AL));
964
965 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
966 BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
967 .addReg(Dest.getReg(), getKillRegState(Dest.isDead()))
968 .addReg(DesiredReg)
969 .add(predOps(ARMCC::AL));
970 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
971 BuildMI(LoadCmpBB, DL, TII->get(Bcc))
972 .addMBB(DoneBB)
973 .addImm(ARMCC::NE)
974 .addReg(ARM::CPSR, RegState::Kill);
975 LoadCmpBB->addSuccessor(DoneBB);
976 LoadCmpBB->addSuccessor(StoreBB);
977
978 // .Lstore:
979 // strex rTempReg, rNew, [rAddr]
980 // cmp rTempReg, #0
981 // bne .Lloadcmp
982 MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), TempReg)
983 .addReg(NewReg)
984 .addReg(AddrReg);
985 if (StrexOp == ARM::t2STREX)
986 MIB.addImm(0); // a 32-bit Thumb strex (only) allows an offset.
987 MIB.add(predOps(ARMCC::AL));
988
989 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
990 BuildMI(StoreBB, DL, TII->get(CMPri))
991 .addReg(TempReg, RegState::Kill)
992 .addImm(0)
993 .add(predOps(ARMCC::AL));
994 BuildMI(StoreBB, DL, TII->get(Bcc))
995 .addMBB(LoadCmpBB)
996 .addImm(ARMCC::NE)
997 .addReg(ARM::CPSR, RegState::Kill);
998 StoreBB->addSuccessor(LoadCmpBB);
999 StoreBB->addSuccessor(DoneBB);
1000
1001 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
1002 DoneBB->transferSuccessors(&MBB);
1003
1004 MBB.addSuccessor(LoadCmpBB);
1005
1006 NextMBBI = MBB.end();
1007 MI.eraseFromParent();
1008
1009 // Recompute livein lists.
1010 LivePhysRegs LiveRegs;
1011 computeAndAddLiveIns(LiveRegs, *DoneBB);
1012 computeAndAddLiveIns(LiveRegs, *StoreBB);
1013 computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
1014 // Do an extra pass around the loop to get loop carried registers right.
1015 StoreBB->clearLiveIns();
1016 computeAndAddLiveIns(LiveRegs, *StoreBB);
1017 LoadCmpBB->clearLiveIns();
1018 computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
1019
1020 return true;
1021 }
1022
1023 /// ARM's ldrexd/strexd take a consecutive register pair (represented as a
1024 /// single GPRPair register), Thumb's take two separate registers so we need to
1025 /// extract the subregs from the pair.
1026 static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg,
1027 unsigned Flags, bool IsThumb,
1028 const TargetRegisterInfo *TRI) {
1029 if (IsThumb) {
1030 unsigned RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0);
1031 unsigned RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1);
1032 MIB.addReg(RegLo, Flags);
1033 MIB.addReg(RegHi, Flags);
1034 } else
1035 MIB.addReg(Reg.getReg(), Flags);
1036 }
1037
1038 /// Expand a 64-bit CMP_SWAP to an ldrexd/strexd loop.
1039 bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
1040 MachineBasicBlock::iterator MBBI,
1041 MachineBasicBlock::iterator &NextMBBI) {
1042 bool IsThumb = STI->isThumb();
1043 MachineInstr &MI = *MBBI;
1044 DebugLoc DL = MI.getDebugLoc();
1045 MachineOperand &Dest = MI.getOperand(0);
1046 unsigned TempReg = MI.getOperand(1).getReg();
1047 // Duplicating undef operands into 2 instructions does not guarantee the same
1048 // value on both; However undef should be replaced by xzr anyway.
1049 assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
1050 unsigned AddrReg = MI.getOperand(2).getReg();
1051 unsigned DesiredReg = MI.getOperand(3).getReg();
1052 MachineOperand New = MI.getOperand(4);
1053 New.setIsKill(false);
1054
1055 unsigned DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0);
1056 unsigned DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1);
1057 unsigned DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0);
1058 unsigned DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1);
1059
1060 MachineFunction *MF = MBB.getParent();
1061 auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
1062 auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
1063 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
1064
1065 MF->insert(++MBB.getIterator(), LoadCmpBB);
1066 MF->insert(++LoadCmpBB->getIterator(), StoreBB);
1067 MF->insert(++StoreBB->getIterator(), DoneBB);
1068
1069 // .Lloadcmp:
1070 // ldrexd rDestLo, rDestHi, [rAddr]
1071 // cmp rDestLo, rDesiredLo
1072 // sbcs dead rTempReg, rDestHi, rDesiredHi
1073 // bne .Ldone
1074 unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD;
1075 MachineInstrBuilder MIB;
1076 MIB = BuildMI(LoadCmpBB, DL, TII->get(LDREXD));
1077 addExclusiveRegPair(MIB, Dest, RegState::Define, IsThumb, TRI);
1078 MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
1079
1080 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
1081 BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
1082 .addReg(DestLo, getKillRegState(Dest.isDead()))
1083 .addReg(DesiredLo)
1084 .add(predOps(ARMCC::AL));
1085
1086 BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
1087 .addReg(DestHi, getKillRegState(Dest.isDead()))
1088 .addReg(DesiredHi)
1089 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill);
1090
1091 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
1092 BuildMI(LoadCmpBB, DL, TII->get(Bcc))
1093 .addMBB(DoneBB)
1094 .addImm(ARMCC::NE)
1095 .addReg(ARM::CPSR, RegState::Kill);
1096 LoadCmpBB->addSuccessor(DoneBB);
1097 LoadCmpBB->addSuccessor(StoreBB);
1098
1099 // .Lstore:
1100 // strexd rTempReg, rNewLo, rNewHi, [rAddr]
1101 // cmp rTempReg, #0
1102 // bne .Lloadcmp
1103 unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD;
1104 MIB = BuildMI(StoreBB, DL, TII->get(STREXD), TempReg);
1105 unsigned Flags = getKillRegState(New.isDead());
1106 addExclusiveRegPair(MIB, New, Flags, IsThumb, TRI);
1107 MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
1108
1109 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
1110 BuildMI(StoreBB, DL, TII->get(CMPri))
1111 .addReg(TempReg, RegState::Kill)
1112 .addImm(0)
1113 .add(predOps(ARMCC::AL));
1114 BuildMI(StoreBB, DL, TII->get(Bcc))
1115 .addMBB(LoadCmpBB)
1116 .addImm(ARMCC::NE)
1117 .addReg(ARM::CPSR, RegState::Kill);
1118 StoreBB->addSuccessor(LoadCmpBB);
1119 StoreBB->addSuccessor(DoneBB);
1120
1121 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
1122 DoneBB->transferSuccessors(&MBB);
1123
1124 MBB.addSuccessor(LoadCmpBB);
1125
1126 NextMBBI = MBB.end();
1127 MI.eraseFromParent();
1128
1129 // Recompute livein lists.
1130 LivePhysRegs LiveRegs;
1131 computeAndAddLiveIns(LiveRegs, *DoneBB);
1132 computeAndAddLiveIns(LiveRegs, *StoreBB);
1133 computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
1134 // Do an extra pass around the loop to get loop carried registers right.
1135 StoreBB->clearLiveIns();
1136 computeAndAddLiveIns(LiveRegs, *StoreBB);
1137 LoadCmpBB->clearLiveIns();
1138 computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
1139
1140 return true;
1141 }
1142
1143
1144 bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
1145 MachineBasicBlock::iterator MBBI,
1146 MachineBasicBlock::iterator &NextMBBI) {
1147 MachineInstr &MI = *MBBI;
1148 unsigned Opcode = MI.getOpcode();
1149 switch (Opcode) {
1150 default:
1151 return false;
1152
1153 case ARM::TCRETURNdi:
1154 case ARM::TCRETURNri: {
1155 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
1156 assert(MBBI->isReturn() &&
1157 "Can only insert epilog into returning blocks");
1158 unsigned RetOpcode = MBBI->getOpcode();
1159 DebugLoc dl = MBBI->getDebugLoc();
1160 const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>(
1161 MBB.getParent()->getSubtarget().getInstrInfo());
1162
1163 // Tail call return: adjust the stack pointer and jump to callee.
1164 MBBI = MBB.getLastNonDebugInstr();
1165 MachineOperand &JumpTarget = MBBI->getOperand(0);
1166
1167 // Jump to label or value in register.
1168 if (RetOpcode == ARM::TCRETURNdi) {
1169 unsigned TCOpcode =
1170 STI->isThumb()
1171 ? (STI->isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND)
1172 : ARM::TAILJMPd;
1173 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
1174 if (JumpTarget.isGlobal())
1175 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1176 JumpTarget.getTargetFlags());
1177 else {
1178 assert(JumpTarget.isSymbol());
1179 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
1180 JumpTarget.getTargetFlags());
1181 }
1182
1183 // Add the default predicate in Thumb mode.
1184 if (STI->isThumb())
1185 MIB.add(predOps(ARMCC::AL));
1186 } else if (RetOpcode == ARM::TCRETURNri) {
1187 unsigned Opcode =
1188 STI->isThumb() ? ARM::tTAILJMPr
1189 : (STI->hasV4TOps() ? ARM::TAILJMPr : ARM::TAILJMPr4);
1190 BuildMI(MBB, MBBI, dl,
1191 TII.get(Opcode))
1192 .addReg(JumpTarget.getReg(), RegState::Kill);
1193 }
1194
1195 auto NewMI = std::prev(MBBI);
1196 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
1197 NewMI->addOperand(MBBI->getOperand(i));
1198
1199 // Delete the pseudo instruction TCRETURN.
1200 MBB.erase(MBBI);
1201 MBBI = NewMI;
1202 return true;
1203 }
1204 case ARM::VMOVScc:
1205 case ARM::VMOVDcc: {
1206 unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD;
1207 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
1208 MI.getOperand(1).getReg())
1209 .add(MI.getOperand(2))
1210 .addImm(MI.getOperand(3).getImm()) // 'pred'
1211 .add(MI.getOperand(4))
1212 .add(makeImplicit(MI.getOperand(1)));
1213
1214 MI.eraseFromParent();
1215 return true;
1216 }
1217 case ARM::t2MOVCCr:
1218 case ARM::MOVCCr: {
1219 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
1220 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1221 MI.getOperand(1).getReg())
1222 .add(MI.getOperand(2))
1223 .addImm(MI.getOperand(3).getImm()) // 'pred'
1224 .add(MI.getOperand(4))
1225 .add(condCodeOp()) // 's' bit
1226 .add(makeImplicit(MI.getOperand(1)));
1227
1228 MI.eraseFromParent();
1229 return true;
1230 }
1231 case ARM::MOVCCsi: {
1232 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1233 (MI.getOperand(1).getReg()))
1234 .add(MI.getOperand(2))
1235 .addImm(MI.getOperand(3).getImm())
1236 .addImm(MI.getOperand(4).getImm()) // 'pred'
1237 .add(MI.getOperand(5))
1238 .add(condCodeOp()) // 's' bit
1239 .add(makeImplicit(MI.getOperand(1)));
1240
1241 MI.eraseFromParent();
1242 return true;
1243 }
1244 case ARM::MOVCCsr: {
1245 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
1246 (MI.getOperand(1).getReg()))
1247 .add(MI.getOperand(2))
1248 .add(MI.getOperand(3))
1249 .addImm(MI.getOperand(4).getImm())
1250 .addImm(MI.getOperand(5).getImm()) // 'pred'
1251 .add(MI.getOperand(6))
1252 .add(condCodeOp()) // 's' bit
1253 .add(makeImplicit(MI.getOperand(1)));
1254
1255 MI.eraseFromParent();
1256 return true;
1257 }
1258 case ARM::t2MOVCCi16:
1259 case ARM::MOVCCi16: {
1260 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16;
1261 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
1262 MI.getOperand(1).getReg())
1263 .addImm(MI.getOperand(2).getImm())
1264 .addImm(MI.getOperand(3).getImm()) // 'pred'
1265 .add(MI.getOperand(4))
1266 .add(makeImplicit(MI.getOperand(1)));
1267 MI.eraseFromParent();
1268 return true;
1269 }
1270 case ARM::t2MOVCCi:
1271 case ARM::MOVCCi: {
1272 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
1273 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1274 MI.getOperand(1).getReg())
1275 .addImm(MI.getOperand(2).getImm())
1276 .addImm(MI.getOperand(3).getImm()) // 'pred'
1277 .add(MI.getOperand(4))
1278 .add(condCodeOp()) // 's' bit
1279 .add(makeImplicit(MI.getOperand(1)));
1280
1281 MI.eraseFromParent();
1282 return true;
1283 }
1284 case ARM::t2MVNCCi:
1285 case ARM::MVNCCi: {
1286 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi;
1287 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1288 MI.getOperand(1).getReg())
1289 .addImm(MI.getOperand(2).getImm())
1290 .addImm(MI.getOperand(3).getImm()) // 'pred'
1291 .add(MI.getOperand(4))
1292 .add(condCodeOp()) // 's' bit
1293 .add(makeImplicit(MI.getOperand(1)));
1294
1295 MI.eraseFromParent();
1296 return true;
1297 }
1298 case ARM::t2MOVCClsl:
1299 case ARM::t2MOVCClsr:
1300 case ARM::t2MOVCCasr:
1301 case ARM::t2MOVCCror: {
1302 unsigned NewOpc;
1303 switch (Opcode) {
1304 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break;
1305 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break;
1306 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break;
1307 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break;
1308 default: llvm_unreachable("unexpeced conditional move");
1309 }
1310 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
1311 MI.getOperand(1).getReg())
1312 .add(MI.getOperand(2))
1313 .addImm(MI.getOperand(3).getImm())
1314 .addImm(MI.getOperand(4).getImm()) // 'pred'
1315 .add(MI.getOperand(5))
1316 .add(condCodeOp()) // 's' bit
1317 .add(makeImplicit(MI.getOperand(1)));
1318 MI.eraseFromParent();
1319 return true;
1320 }
1321 case ARM::Int_eh_sjlj_dispatchsetup: {
1322 MachineFunction &MF = *MI.getParent()->getParent();
1323 const ARMBaseInstrInfo *AII =
1324 static_cast<const ARMBaseInstrInfo*>(TII);
1325 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
1326 // For functions using a base pointer, we rematerialize it (via the frame
1327 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it
1328 // for us. Otherwise, expand to nothing.
1329 if (RI.hasBasePointer(MF)) {
1330 int32_t NumBytes = AFI->getFramePtrSpillOffset();
1331 unsigned FramePtr = RI.getFrameRegister(MF);
1332 assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) &&
1333 "base pointer without frame pointer?");
1334
1335 if (AFI->isThumb2Function()) {
1336 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1337 FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
1338 } else if (AFI->isThumbFunction()) {
1339 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1340 FramePtr, -NumBytes, *TII, RI);
1341 } else {
1342 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1343 FramePtr, -NumBytes, ARMCC::AL, 0,
1344 *TII);
1345 }
1346 // If there's dynamic realignment, adjust for it.
1347 if (RI.needsStackRealignment(MF)) {
1348 MachineFrameInfo &MFI = MF.getFrameInfo();
1349 unsigned MaxAlign = MFI.getMaxAlignment();
1350 assert (!AFI->isThumb1OnlyFunction());
1351 // Emit bic r6, r6, MaxAlign
1352 assert(MaxAlign <= 256 && "The BIC instruction cannot encode "
1353 "immediates larger than 256 with all lower "
1354 "bits set.");
1355 unsigned bicOpc = AFI->isThumbFunction() ?
1356 ARM::t2BICri : ARM::BICri;
1357 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6)
1358 .addReg(ARM::R6, RegState::Kill)
1359 .addImm(MaxAlign - 1)
1360 .add(predOps(ARMCC::AL))
1361 .add(condCodeOp());
1362 }
1363
1364 }
1365 MI.eraseFromParent();
1366 return true;
1367 }
1368
1369 case ARM::MOVsrl_flag:
1370 case ARM::MOVsra_flag: {
1371 // These are just fancy MOVs instructions.
1372 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1373 MI.getOperand(0).getReg())
1374 .add(MI.getOperand(1))
1375 .addImm(ARM_AM::getSORegOpc(
1376 (Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr : ARM_AM::asr), 1))
1377 .add(predOps(ARMCC::AL))
1378 .addReg(ARM::CPSR, RegState::Define);
1379 MI.eraseFromParent();
1380 return true;
1381 }
1382 case ARM::RRX: {
1383 // This encodes as "MOVs Rd, Rm, rrx
1384 MachineInstrBuilder MIB =
1385 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1386 MI.getOperand(0).getReg())
1387 .add(MI.getOperand(1))
1388 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0))
1389 .add(predOps(ARMCC::AL))
1390 .add(condCodeOp());
1391 TransferImpOps(MI, MIB, MIB);
1392 MI.eraseFromParent();
1393 return true;
1394 }
1395 case ARM::tTPsoft:
1396 case ARM::TPsoft: {
1397 const bool Thumb = Opcode == ARM::tTPsoft;
1398
1399 MachineInstrBuilder MIB;
1400 if (STI->genLongCalls()) {
1401 MachineFunction *MF = MBB.getParent();
1402 MachineConstantPool *MCP = MF->getConstantPool();
1403 unsigned PCLabelID = AFI->createPICLabelUId();
1404 MachineConstantPoolValue *CPV =
1405 ARMConstantPoolSymbol::Create(MF->getFunction().getContext(),
1406 "__aeabi_read_tp", PCLabelID, 0);
1407 unsigned Reg = MI.getOperand(0).getReg();
1408 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1409 TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg)
1410 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4));
1411 if (!Thumb)
1412 MIB.addImm(0);
1413 MIB.add(predOps(ARMCC::AL));
1414
1415 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1416 TII->get(Thumb ? ARM::tBLXr : ARM::BLX));
1417 if (Thumb)
1418 MIB.add(predOps(ARMCC::AL));
1419 MIB.addReg(Reg, RegState::Kill);
1420 } else {
1421 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1422 TII->get(Thumb ? ARM::tBL : ARM::BL));
1423 if (Thumb)
1424 MIB.add(predOps(ARMCC::AL));
1425 MIB.addExternalSymbol("__aeabi_read_tp", 0);
1426 }
1427
1428 MIB.cloneMemRefs(MI);
1429 TransferImpOps(MI, MIB, MIB);
1430 MI.eraseFromParent();
1431 return true;
1432 }
1433 case ARM::tLDRpci_pic:
1434 case ARM::t2LDRpci_pic: {
1435 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
1436 ? ARM::tLDRpci : ARM::t2LDRpci;
1437 unsigned DstReg = MI.getOperand(0).getReg();
1438 bool DstIsDead = MI.getOperand(0).isDead();
1439 MachineInstrBuilder MIB1 =
1440 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewLdOpc), DstReg)
1441 .add(MI.getOperand(1))
1442 .add(predOps(ARMCC::AL));
1443 MIB1.cloneMemRefs(MI);
1444 MachineInstrBuilder MIB2 =
1445 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD))
1446 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1447 .addReg(DstReg)
1448 .add(MI.getOperand(2));
1449 TransferImpOps(MI, MIB1, MIB2);
1450 MI.eraseFromParent();
1451 return true;
1452 }
1453
1454 case ARM::LDRLIT_ga_abs:
1455 case ARM::LDRLIT_ga_pcrel:
1456 case ARM::LDRLIT_ga_pcrel_ldr:
1457 case ARM::tLDRLIT_ga_abs:
1458 case ARM::tLDRLIT_ga_pcrel: {
1459 unsigned DstReg = MI.getOperand(0).getReg();
1460 bool DstIsDead = MI.getOperand(0).isDead();
1461 const MachineOperand &MO1 = MI.getOperand(1);
1462 auto Flags = MO1.getTargetFlags();
1463 const GlobalValue *GV = MO1.getGlobal();
1464 bool IsARM =
1465 Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs;
1466 bool IsPIC =
1467 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs;
1468 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci;
1469 unsigned PICAddOpc =
1470 IsARM
1471 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
1472 : ARM::tPICADD;
1473
1474 // We need a new const-pool entry to load from.
1475 MachineConstantPool *MCP = MBB.getParent()->getConstantPool();
1476 unsigned ARMPCLabelIndex = 0;
1477 MachineConstantPoolValue *CPV;
1478
1479 if (IsPIC) {
1480 unsigned PCAdj = IsARM ? 8 : 4;
1481 auto Modifier = (Flags & ARMII::MO_GOT)
1482 ? ARMCP::GOT_PREL
1483 : ARMCP::no_modifier;
1484 ARMPCLabelIndex = AFI->createPICLabelUId();
1485 CPV = ARMConstantPoolConstant::Create(
1486 GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj, Modifier,
1487 /*AddCurrentAddr*/ Modifier == ARMCP::GOT_PREL);
1488 } else
1489 CPV = ARMConstantPoolConstant::Create(GV, ARMCP::no_modifier);
1490
1491 MachineInstrBuilder MIB =
1492 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg)
1493 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4));
1494 if (IsARM)
1495 MIB.addImm(0);
1496 MIB.add(predOps(ARMCC::AL));
1497
1498 if (IsPIC) {
1499 MachineInstrBuilder MIB =
1500 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc))
1501 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1502 .addReg(DstReg)
1503 .addImm(ARMPCLabelIndex);
1504
1505 if (IsARM)
1506 MIB.add(predOps(ARMCC::AL));
1507 }
1508
1509 MI.eraseFromParent();
1510 return true;
1511 }
1512 case ARM::MOV_ga_pcrel:
1513 case ARM::MOV_ga_pcrel_ldr:
1514 case ARM::t2MOV_ga_pcrel: {
1515 // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode.
1516 unsigned LabelId = AFI->createPICLabelUId();
1517 unsigned DstReg = MI.getOperand(0).getReg();
1518 bool DstIsDead = MI.getOperand(0).isDead();
1519 const MachineOperand &MO1 = MI.getOperand(1);
1520 const GlobalValue *GV = MO1.getGlobal();
1521 unsigned TF = MO1.getTargetFlags();
1522 bool isARM = Opcode != ARM::t2MOV_ga_pcrel;
1523 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
1524 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
1525 unsigned LO16TF = TF | ARMII::MO_LO16;
1526 unsigned HI16TF = TF | ARMII::MO_HI16;
1527 unsigned PICAddOpc = isARM
1528 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
1529 : ARM::tPICADD;
1530 MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1531 TII->get(LO16Opc), DstReg)
1532 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF)
1533 .addImm(LabelId);
1534
1535 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg)
1536 .addReg(DstReg)
1537 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF)
1538 .addImm(LabelId);
1539
1540 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1541 TII->get(PICAddOpc))
1542 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1543 .addReg(DstReg).addImm(LabelId);
1544 if (isARM) {
1545 MIB3.add(predOps(ARMCC::AL));
1546 if (Opcode == ARM::MOV_ga_pcrel_ldr)
1547 MIB3.cloneMemRefs(MI);
1548 }
1549 TransferImpOps(MI, MIB1, MIB3);
1550 MI.eraseFromParent();
1551 return true;
1552 }
1553
1554 case ARM::MOVi32imm:
1555 case ARM::MOVCCi32imm:
1556 case ARM::t2MOVi32imm:
1557 case ARM::t2MOVCCi32imm:
1558 ExpandMOV32BitImm(MBB, MBBI);
1559 return true;
1560
1561 case ARM::SUBS_PC_LR: {
1562 MachineInstrBuilder MIB =
1563 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC)
1564 .addReg(ARM::LR)
1565 .add(MI.getOperand(0))
1566 .add(MI.getOperand(1))
1567 .add(MI.getOperand(2))
1568 .addReg(ARM::CPSR, RegState::Undef);
1569 TransferImpOps(MI, MIB, MIB);
1570 MI.eraseFromParent();
1571 return true;
1572 }
1573 case ARM::VLDMQIA: {
1574 unsigned NewOpc = ARM::VLDMDIA;
1575 MachineInstrBuilder MIB =
1576 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1577 unsigned OpIdx = 0;
1578
1579 // Grab the Q register destination.
1580 bool DstIsDead = MI.getOperand(OpIdx).isDead();
1581 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
1582
1583 // Copy the source register.
1584 MIB.add(MI.getOperand(OpIdx++));
1585
1586 // Copy the predicate operands.
1587 MIB.add(MI.getOperand(OpIdx++));
1588 MIB.add(MI.getOperand(OpIdx++));
1589
1590 // Add the destination operands (D subregs).
1591 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
1592 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
1593 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
1594 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
1595
1596 // Add an implicit def for the super-register.
1597 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
1598 TransferImpOps(MI, MIB, MIB);
1599 MIB.cloneMemRefs(MI);
1600 MI.eraseFromParent();
1601 return true;
1602 }
1603
1604 case ARM::VSTMQIA: {
1605 unsigned NewOpc = ARM::VSTMDIA;
1606 MachineInstrBuilder MIB =
1607 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1608 unsigned OpIdx = 0;
1609
1610 // Grab the Q register source.
1611 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
1612 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
1613
1614 // Copy the destination register.
1615 MachineOperand Dst(MI.getOperand(OpIdx++));
1616 MIB.add(Dst);
1617
1618 // Copy the predicate operands.
1619 MIB.add(MI.getOperand(OpIdx++));
1620 MIB.add(MI.getOperand(OpIdx++));
1621
1622 // Add the source operands (D subregs).
1623 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
1624 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
1625 MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0)
1626 .addReg(D1, SrcIsKill ? RegState::Kill : 0);
1627
1628 if (SrcIsKill) // Add an implicit kill for the Q register.
1629 MIB->addRegisterKilled(SrcReg, TRI, true);
1630
1631 TransferImpOps(MI, MIB, MIB);
1632 MIB.cloneMemRefs(MI);
1633 MI.eraseFromParent();
1634 return true;
1635 }
1636
1637 case ARM::VLD2q8Pseudo:
1638 case ARM::VLD2q16Pseudo:
1639 case ARM::VLD2q32Pseudo:
1640 case ARM::VLD2q8PseudoWB_fixed:
1641 case ARM::VLD2q16PseudoWB_fixed:
1642 case ARM::VLD2q32PseudoWB_fixed:
1643 case ARM::VLD2q8PseudoWB_register:
1644 case ARM::VLD2q16PseudoWB_register:
1645 case ARM::VLD2q32PseudoWB_register:
1646 case ARM::VLD3d8Pseudo:
1647 case ARM::VLD3d16Pseudo:
1648 case ARM::VLD3d32Pseudo:
1649 case ARM::VLD1d8TPseudo:
1650 case ARM::VLD1d16TPseudo:
1651 case ARM::VLD1d32TPseudo:
1652 case ARM::VLD1d64TPseudo:
1653 case ARM::VLD1d64TPseudoWB_fixed:
1654 case ARM::VLD1d64TPseudoWB_register:
1655 case ARM::VLD3d8Pseudo_UPD:
1656 case ARM::VLD3d16Pseudo_UPD:
1657 case ARM::VLD3d32Pseudo_UPD:
1658 case ARM::VLD3q8Pseudo_UPD:
1659 case ARM::VLD3q16Pseudo_UPD:
1660 case ARM::VLD3q32Pseudo_UPD:
1661 case ARM::VLD3q8oddPseudo:
1662 case ARM::VLD3q16oddPseudo:
1663 case ARM::VLD3q32oddPseudo:
1664 case ARM::VLD3q8oddPseudo_UPD:
1665 case ARM::VLD3q16oddPseudo_UPD:
1666 case ARM::VLD3q32oddPseudo_UPD:
1667 case ARM::VLD4d8Pseudo:
1668 case ARM::VLD4d16Pseudo:
1669 case ARM::VLD4d32Pseudo:
1670 case ARM::VLD1d8QPseudo:
1671 case ARM::VLD1d16QPseudo:
1672 case ARM::VLD1d32QPseudo:
1673 case ARM::VLD1d64QPseudo:
1674 case ARM::VLD1d64QPseudoWB_fixed:
1675 case ARM::VLD1d64QPseudoWB_register:
1676 case ARM::VLD1q8HighQPseudo:
1677 case ARM::VLD1q8LowQPseudo_UPD:
1678 case ARM::VLD1q8HighTPseudo:
1679 case ARM::VLD1q8LowTPseudo_UPD:
1680 case ARM::VLD1q16HighQPseudo:
1681 case ARM::VLD1q16LowQPseudo_UPD:
1682 case ARM::VLD1q16HighTPseudo:
1683 case ARM::VLD1q16LowTPseudo_UPD:
1684 case ARM::VLD1q32HighQPseudo:
1685 case ARM::VLD1q32LowQPseudo_UPD:
1686 case ARM::VLD1q32HighTPseudo:
1687 case ARM::VLD1q32LowTPseudo_UPD:
1688 case ARM::VLD1q64HighQPseudo:
1689 case ARM::VLD1q64LowQPseudo_UPD:
1690 case ARM::VLD1q64HighTPseudo:
1691 case ARM::VLD1q64LowTPseudo_UPD:
1692 case ARM::VLD4d8Pseudo_UPD:
1693 case ARM::VLD4d16Pseudo_UPD:
1694 case ARM::VLD4d32Pseudo_UPD:
1695 case ARM::VLD4q8Pseudo_UPD:
1696 case ARM::VLD4q16Pseudo_UPD:
1697 case ARM::VLD4q32Pseudo_UPD:
1698 case ARM::VLD4q8oddPseudo:
1699 case ARM::VLD4q16oddPseudo:
1700 case ARM::VLD4q32oddPseudo:
1701 case ARM::VLD4q8oddPseudo_UPD:
1702 case ARM::VLD4q16oddPseudo_UPD:
1703 case ARM::VLD4q32oddPseudo_UPD:
1704 case ARM::VLD3DUPd8Pseudo:
1705 case ARM::VLD3DUPd16Pseudo:
1706 case ARM::VLD3DUPd32Pseudo:
1707 case ARM::VLD3DUPd8Pseudo_UPD:
1708 case ARM::VLD3DUPd16Pseudo_UPD:
1709 case ARM::VLD3DUPd32Pseudo_UPD:
1710 case ARM::VLD4DUPd8Pseudo:
1711 case ARM::VLD4DUPd16Pseudo:
1712 case ARM::VLD4DUPd32Pseudo:
1713 case ARM::VLD4DUPd8Pseudo_UPD:
1714 case ARM::VLD4DUPd16Pseudo_UPD:
1715 case ARM::VLD4DUPd32Pseudo_UPD:
1716 case ARM::VLD2DUPq8EvenPseudo:
1717 case ARM::VLD2DUPq8OddPseudo:
1718 case ARM::VLD2DUPq16EvenPseudo:
1719 case ARM::VLD2DUPq16OddPseudo:
1720 case ARM::VLD2DUPq32EvenPseudo:
1721 case ARM::VLD2DUPq32OddPseudo:
1722 case ARM::VLD3DUPq8EvenPseudo:
1723 case ARM::VLD3DUPq8OddPseudo:
1724 case ARM::VLD3DUPq16EvenPseudo:
1725 case ARM::VLD3DUPq16OddPseudo:
1726 case ARM::VLD3DUPq32EvenPseudo:
1727 case ARM::VLD3DUPq32OddPseudo:
1728 case ARM::VLD4DUPq8EvenPseudo:
1729 case ARM::VLD4DUPq8OddPseudo:
1730 case ARM::VLD4DUPq16EvenPseudo:
1731 case ARM::VLD4DUPq16OddPseudo:
1732 case ARM::VLD4DUPq32EvenPseudo:
1733 case ARM::VLD4DUPq32OddPseudo:
1734 ExpandVLD(MBBI);
1735 return true;
1736
1737 case ARM::VST2q8Pseudo:
1738 case ARM::VST2q16Pseudo:
1739 case ARM::VST2q32Pseudo:
1740 case ARM::VST2q8PseudoWB_fixed:
1741 case ARM::VST2q16PseudoWB_fixed:
1742 case ARM::VST2q32PseudoWB_fixed:
1743 case ARM::VST2q8PseudoWB_register:
1744 case ARM::VST2q16PseudoWB_register:
1745 case ARM::VST2q32PseudoWB_register:
1746 case ARM::VST3d8Pseudo:
1747 case ARM::VST3d16Pseudo:
1748 case ARM::VST3d32Pseudo:
1749 case ARM::VST1d8TPseudo:
1750 case ARM::VST1d16TPseudo:
1751 case ARM::VST1d32TPseudo:
1752 case ARM::VST1d64TPseudo:
1753 case ARM::VST3d8Pseudo_UPD:
1754 case ARM::VST3d16Pseudo_UPD:
1755 case ARM::VST3d32Pseudo_UPD:
1756 case ARM::VST1d64TPseudoWB_fixed:
1757 case ARM::VST1d64TPseudoWB_register:
1758 case ARM::VST3q8Pseudo_UPD:
1759 case ARM::VST3q16Pseudo_UPD:
1760 case ARM::VST3q32Pseudo_UPD:
1761 case ARM::VST3q8oddPseudo:
1762 case ARM::VST3q16oddPseudo:
1763 case ARM::VST3q32oddPseudo:
1764 case ARM::VST3q8oddPseudo_UPD:
1765 case ARM::VST3q16oddPseudo_UPD:
1766 case ARM::VST3q32oddPseudo_UPD:
1767 case ARM::VST4d8Pseudo:
1768 case ARM::VST4d16Pseudo:
1769 case ARM::VST4d32Pseudo:
1770 case ARM::VST1d8QPseudo:
1771 case ARM::VST1d16QPseudo:
1772 case ARM::VST1d32QPseudo:
1773 case ARM::VST1d64QPseudo:
1774 case ARM::VST4d8Pseudo_UPD:
1775 case ARM::VST4d16Pseudo_UPD:
1776 case ARM::VST4d32Pseudo_UPD:
1777 case ARM::VST1d64QPseudoWB_fixed:
1778 case ARM::VST1d64QPseudoWB_register:
1779 case ARM::VST1q8HighQPseudo:
1780 case ARM::VST1q8LowQPseudo_UPD:
1781 case ARM::VST1q8HighTPseudo:
1782 case ARM::VST1q8LowTPseudo_UPD:
1783 case ARM::VST1q16HighQPseudo:
1784 case ARM::VST1q16LowQPseudo_UPD:
1785 case ARM::VST1q16HighTPseudo:
1786 case ARM::VST1q16LowTPseudo_UPD:
1787 case ARM::VST1q32HighQPseudo:
1788 case ARM::VST1q32LowQPseudo_UPD:
1789 case ARM::VST1q32HighTPseudo:
1790 case ARM::VST1q32LowTPseudo_UPD:
1791 case ARM::VST1q64HighQPseudo:
1792 case ARM::VST1q64LowQPseudo_UPD:
1793 case ARM::VST1q64HighTPseudo:
1794 case ARM::VST1q64LowTPseudo_UPD:
1795 case ARM::VST4q8Pseudo_UPD:
1796 case ARM::VST4q16Pseudo_UPD:
1797 case ARM::VST4q32Pseudo_UPD:
1798 case ARM::VST4q8oddPseudo:
1799 case ARM::VST4q16oddPseudo:
1800 case ARM::VST4q32oddPseudo:
1801 case ARM::VST4q8oddPseudo_UPD:
1802 case ARM::VST4q16oddPseudo_UPD:
1803 case ARM::VST4q32oddPseudo_UPD:
1804 ExpandVST(MBBI);
1805 return true;
1806
1807 case ARM::VLD1LNq8Pseudo:
1808 case ARM::VLD1LNq16Pseudo:
1809 case ARM::VLD1LNq32Pseudo:
1810 case ARM::VLD1LNq8Pseudo_UPD:
1811 case ARM::VLD1LNq16Pseudo_UPD:
1812 case ARM::VLD1LNq32Pseudo_UPD:
1813 case ARM::VLD2LNd8Pseudo:
1814 case ARM::VLD2LNd16Pseudo:
1815 case ARM::VLD2LNd32Pseudo:
1816 case ARM::VLD2LNq16Pseudo:
1817 case ARM::VLD2LNq32Pseudo:
1818 case ARM::VLD2LNd8Pseudo_UPD:
1819 case ARM::VLD2LNd16Pseudo_UPD:
1820 case ARM::VLD2LNd32Pseudo_UPD:
1821 case ARM::VLD2LNq16Pseudo_UPD:
1822 case ARM::VLD2LNq32Pseudo_UPD:
1823 case ARM::VLD3LNd8Pseudo:
1824 case ARM::VLD3LNd16Pseudo:
1825 case ARM::VLD3LNd32Pseudo:
1826 case ARM::VLD3LNq16Pseudo:
1827 case ARM::VLD3LNq32Pseudo:
1828 case ARM::VLD3LNd8Pseudo_UPD:
1829 case ARM::VLD3LNd16Pseudo_UPD:
1830 case ARM::VLD3LNd32Pseudo_UPD:
1831 case ARM::VLD3LNq16Pseudo_UPD:
1832 case ARM::VLD3LNq32Pseudo_UPD:
1833 case ARM::VLD4LNd8Pseudo:
1834 case ARM::VLD4LNd16Pseudo:
1835 case ARM::VLD4LNd32Pseudo:
1836 case ARM::VLD4LNq16Pseudo:
1837 case ARM::VLD4LNq32Pseudo:
1838 case ARM::VLD4LNd8Pseudo_UPD:
1839 case ARM::VLD4LNd16Pseudo_UPD:
1840 case ARM::VLD4LNd32Pseudo_UPD:
1841 case ARM::VLD4LNq16Pseudo_UPD:
1842 case ARM::VLD4LNq32Pseudo_UPD:
1843 case ARM::VST1LNq8Pseudo:
1844 case ARM::VST1LNq16Pseudo:
1845 case ARM::VST1LNq32Pseudo:
1846 case ARM::VST1LNq8Pseudo_UPD:
1847 case ARM::VST1LNq16Pseudo_UPD:
1848 case ARM::VST1LNq32Pseudo_UPD:
1849 case ARM::VST2LNd8Pseudo:
1850 case ARM::VST2LNd16Pseudo:
1851 case ARM::VST2LNd32Pseudo:
1852 case ARM::VST2LNq16Pseudo:
1853 case ARM::VST2LNq32Pseudo:
1854 case ARM::VST2LNd8Pseudo_UPD:
1855 case ARM::VST2LNd16Pseudo_UPD:
1856 case ARM::VST2LNd32Pseudo_UPD:
1857 case ARM::VST2LNq16Pseudo_UPD:
1858 case ARM::VST2LNq32Pseudo_UPD:
1859 case ARM::VST3LNd8Pseudo:
1860 case ARM::VST3LNd16Pseudo:
1861 case ARM::VST3LNd32Pseudo:
1862 case ARM::VST3LNq16Pseudo:
1863 case ARM::VST3LNq32Pseudo:
1864 case ARM::VST3LNd8Pseudo_UPD:
1865 case ARM::VST3LNd16Pseudo_UPD:
1866 case ARM::VST3LNd32Pseudo_UPD:
1867 case ARM::VST3LNq16Pseudo_UPD:
1868 case ARM::VST3LNq32Pseudo_UPD:
1869 case ARM::VST4LNd8Pseudo:
1870 case ARM::VST4LNd16Pseudo:
1871 case ARM::VST4LNd32Pseudo:
1872 case ARM::VST4LNq16Pseudo:
1873 case ARM::VST4LNq32Pseudo:
1874 case ARM::VST4LNd8Pseudo_UPD:
1875 case ARM::VST4LNd16Pseudo_UPD:
1876 case ARM::VST4LNd32Pseudo_UPD:
1877 case ARM::VST4LNq16Pseudo_UPD:
1878 case ARM::VST4LNq32Pseudo_UPD:
1879 ExpandLaneOp(MBBI);
1880 return true;
1881
1882 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
1883 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
1884 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
1885 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true;
1886
1887 case ARM::CMP_SWAP_8:
1888 if (STI->isThumb())
1889 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB,
1890 ARM::tUXTB, NextMBBI);
1891 else
1892 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB,
1893 ARM::UXTB, NextMBBI);
1894 case ARM::CMP_SWAP_16:
1895 if (STI->isThumb())
1896 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH,
1897 ARM::tUXTH, NextMBBI);
1898 else
1899 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH,
1900 ARM::UXTH, NextMBBI);
1901 case ARM::CMP_SWAP_32:
1902 if (STI->isThumb())
1903 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0,
1904 NextMBBI);
1905 else
1906 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI);
1907
1908 case ARM::CMP_SWAP_64:
1909 return ExpandCMP_SWAP_64(MBB, MBBI, NextMBBI);
1910 }
1911 }
1912
1913 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
1914 bool Modified = false;
1915
1916 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1917 while (MBBI != E) {
1918 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
1919 Modified |= ExpandMI(MBB, MBBI, NMBBI);
1920 MBBI = NMBBI;
1921 }
1922
1923 return Modified;
1924 }
1925
1926 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
1927 STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget());
1928 TII = STI->getInstrInfo();
1929 TRI = STI->getRegisterInfo();
1930 AFI = MF.getInfo<ARMFunctionInfo>();
1931
1932 bool Modified = false;
1933 for (MachineBasicBlock &MBB : MF)
1934 Modified |= ExpandMBB(MBB);
1935 if (VerifyARMPseudo)
1936 MF.verify(this, "After expanding ARM pseudo instructions.");
1937 return Modified;
1938 }
1939
1940 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction
1941 /// expansion pass.
1942 FunctionPass *llvm::createARMExpandPseudoPass() {
1943 return new ARMExpandPseudo();
1944 }
The low level virtual machine