lib/Target/ARM/AsmParser/ARMAsmParser.cpp

   1 //===- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions -------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 #include "ARMFeatures.h"
  10 #include "InstPrinter/ARMInstPrinter.h"
  11 #include "Utils/ARMBaseInfo.h"
  12 #include "MCTargetDesc/ARMAddressingModes.h"
  13 #include "MCTargetDesc/ARMBaseInfo.h"
  14 #include "MCTargetDesc/ARMMCExpr.h"
  15 #include "MCTargetDesc/ARMMCTargetDesc.h"
  16 #include "llvm/ADT/APFloat.h"
  17 #include "llvm/ADT/APInt.h"
  18 #include "llvm/ADT/None.h"
  19 #include "llvm/ADT/STLExtras.h"
  20 #include "llvm/ADT/SmallSet.h"
  21 #include "llvm/ADT/SmallVector.h"
  22 #include "llvm/ADT/StringMap.h"
  23 #include "llvm/ADT/StringRef.h"
  24 #include "llvm/ADT/StringSwitch.h"
  25 #include "llvm/ADT/Triple.h"
  26 #include "llvm/ADT/Twine.h"
  27 #include "llvm/MC/MCContext.h"
  28 #include "llvm/MC/MCExpr.h"
  29 #include "llvm/MC/MCInst.h"
  30 #include "llvm/MC/MCInstrDesc.h"
  31 #include "llvm/MC/MCInstrInfo.h"
  32 #include "llvm/MC/MCObjectFileInfo.h"
  33 #include "llvm/MC/MCParser/MCAsmLexer.h"
  34 #include "llvm/MC/MCParser/MCAsmParser.h"
  35 #include "llvm/MC/MCParser/MCAsmParserExtension.h"
  36 #include "llvm/MC/MCParser/MCAsmParserUtils.h"
  37 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
  38 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
  39 #include "llvm/MC/MCRegisterInfo.h"
  40 #include "llvm/MC/MCSection.h"
  41 #include "llvm/MC/MCStreamer.h"
  42 #include "llvm/MC/MCSubtargetInfo.h"
  43 #include "llvm/MC/MCSymbol.h"
  44 #include "llvm/MC/SubtargetFeature.h"
  45 #include "llvm/Support/ARMBuildAttributes.h"
  46 #include "llvm/Support/ARMEHABI.h"
  47 #include "llvm/Support/Casting.h"
  48 #include "llvm/Support/CommandLine.h"
  49 #include "llvm/Support/Compiler.h"
  50 #include "llvm/Support/ErrorHandling.h"
  51 #include "llvm/Support/MathExtras.h"
  52 #include "llvm/Support/SMLoc.h"
  53 #include "llvm/Support/TargetParser.h"
  54 #include "llvm/Support/TargetRegistry.h"
  55 #include "llvm/Support/raw_ostream.h"
  56 #include <algorithm>
  57 #include <cassert>
  58 #include <cstddef>
  59 #include <cstdint>
  60 #include <iterator>
  61 #include <limits>
  62 #include <memory>
  63 #include <string>
  64 #include <utility>
  65 #include <vector>
  66
  67 #define DEBUG_TYPE "asm-parser"
  68
  69 using namespace llvm;
  70
  71 namespace {
  72
  73 enum class ImplicitItModeTy { Always, Never, ARMOnly, ThumbOnly };
  74
  75 static cl::opt<ImplicitItModeTy> ImplicitItMode(
  76     "arm-implicit-it", cl::init(ImplicitItModeTy::ARMOnly),
  77     cl::desc("Allow conditional instructions outdside of an IT block"),
  78     cl::values(clEnumValN(ImplicitItModeTy::Always, "always",
  79                           "Accept in both ISAs, emit implicit ITs in Thumb"),
  80                clEnumValN(ImplicitItModeTy::Never, "never",
  81                           "Warn in ARM, reject in Thumb"),
  82                clEnumValN(ImplicitItModeTy::ARMOnly, "arm",
  83                           "Accept in ARM, reject in Thumb"),
  84                clEnumValN(ImplicitItModeTy::ThumbOnly, "thumb",
  85                           "Warn in ARM, emit implicit ITs in Thumb")));
  86
  87 static cl::opt<bool> AddBuildAttributes("arm-add-build-attributes",
  88                                         cl::init(false));
  89
  90 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
  91
  92 class UnwindContext {
  93   using Locs = SmallVector<SMLoc, 4>;
  94
  95   MCAsmParser &Parser;
  96   Locs FnStartLocs;
  97   Locs CantUnwindLocs;
  98   Locs PersonalityLocs;
  99   Locs PersonalityIndexLocs;
 100   Locs HandlerDataLocs;
 101   int FPReg;
 102
 103 public:
 104   UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
 105
 106   bool hasFnStart() const { return !FnStartLocs.empty(); }
 107   bool cantUnwind() const { return !CantUnwindLocs.empty(); }
 108   bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
 109
 110   bool hasPersonality() const {
 111     return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
 112   }
 113
 114   void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
 115   void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
 116   void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
 117   void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
 118   void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
 119
 120   void saveFPReg(int Reg) { FPReg = Reg; }
 121   int getFPReg() const { return FPReg; }
 122
 123   void emitFnStartLocNotes() const {
 124     for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
 125          FI != FE; ++FI)
 126       Parser.Note(*FI, ".fnstart was specified here");
 127   }
 128
 129   void emitCantUnwindLocNotes() const {
 130     for (Locs::const_iterator UI = CantUnwindLocs.begin(),
 131                               UE = CantUnwindLocs.end(); UI != UE; ++UI)
 132       Parser.Note(*UI, ".cantunwind was specified here");
 133   }
 134
 135   void emitHandlerDataLocNotes() const {
 136     for (Locs::const_iterator HI = HandlerDataLocs.begin(),
 137                               HE = HandlerDataLocs.end(); HI != HE; ++HI)
 138       Parser.Note(*HI, ".handlerdata was specified here");
 139   }
 140
 141   void emitPersonalityLocNotes() const {
 142     for (Locs::const_iterator PI = PersonalityLocs.begin(),
 143                               PE = PersonalityLocs.end(),
 144                               PII = PersonalityIndexLocs.begin(),
 145                               PIE = PersonalityIndexLocs.end();
 146          PI != PE || PII != PIE;) {
 147       if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
 148         Parser.Note(*PI++, ".personality was specified here");
 149       else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
 150         Parser.Note(*PII++, ".personalityindex was specified here");
 151       else
 152         llvm_unreachable(".personality and .personalityindex cannot be "
 153                          "at the same location");
 154     }
 155   }
 156
 157   void reset() {
 158     FnStartLocs = Locs();
 159     CantUnwindLocs = Locs();
 160     PersonalityLocs = Locs();
 161     HandlerDataLocs = Locs();
 162     PersonalityIndexLocs = Locs();
 163     FPReg = ARM::SP;
 164   }
 165 };
 166
 167 class ARMAsmParser : public MCTargetAsmParser {
 168   const MCRegisterInfo *MRI;
 169   UnwindContext UC;
 170
 171   ARMTargetStreamer &getTargetStreamer() {
 172     assert(getParser().getStreamer().getTargetStreamer() &&
 173            "do not have a target streamer");
 174     MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
 175     return static_cast<ARMTargetStreamer &>(TS);
 176   }
 177
 178   // Map of register aliases registers via the .req directive.
 179   StringMap<unsigned> RegisterReqs;
 180
 181   bool NextSymbolIsThumb;
 182
 183   bool useImplicitITThumb() const {
 184     return ImplicitItMode == ImplicitItModeTy::Always ||
 185            ImplicitItMode == ImplicitItModeTy::ThumbOnly;
 186   }
 187
 188   bool useImplicitITARM() const {
 189     return ImplicitItMode == ImplicitItModeTy::Always ||
 190            ImplicitItMode == ImplicitItModeTy::ARMOnly;
 191   }
 192
 193   struct {
 194     ARMCC::CondCodes Cond;    // Condition for IT block.
 195     unsigned Mask:4;          // Condition mask for instructions.
 196                               // Starting at first 1 (from lsb).
 197                               //   '1'  condition as indicated in IT.
 198                               //   '0'  inverse of condition (else).
 199                               // Count of instructions in IT block is
 200                               // 4 - trailingzeroes(mask)
 201                               // Note that this does not have the same encoding
 202                               // as in the IT instruction, which also depends
 203                               // on the low bit of the condition code.
 204
 205     unsigned CurPosition;     // Current position in parsing of IT
 206                               // block. In range [0,4], with 0 being the IT
 207                               // instruction itself. Initialized according to
 208                               // count of instructions in block.  ~0U if no
 209                               // active IT block.
 210
 211     bool IsExplicit;          // true  - The IT instruction was present in the
 212                               //         input, we should not modify it.
 213                               // false - The IT instruction was added
 214                               //         implicitly, we can extend it if that
 215                               //         would be legal.
 216   } ITState;
 217
 218   SmallVector<MCInst, 4> PendingConditionalInsts;
 219
 220   void flushPendingInstructions(MCStreamer &Out) override {
 221     if (!inImplicitITBlock()) {
 222       assert(PendingConditionalInsts.size() == 0);
 223       return;
 224     }
 225
 226     // Emit the IT instruction
 227     unsigned Mask = getITMaskEncoding();
 228     MCInst ITInst;
 229     ITInst.setOpcode(ARM::t2IT);
 230     ITInst.addOperand(MCOperand::createImm(ITState.Cond));
 231     ITInst.addOperand(MCOperand::createImm(Mask));
 232     Out.EmitInstruction(ITInst, getSTI());
 233
 234     // Emit the conditonal instructions
 235     assert(PendingConditionalInsts.size() <= 4);
 236     for (const MCInst &Inst : PendingConditionalInsts) {
 237       Out.EmitInstruction(Inst, getSTI());
 238     }
 239     PendingConditionalInsts.clear();
 240
 241     // Clear the IT state
 242     ITState.Mask = 0;
 243     ITState.CurPosition = ~0U;
 244   }
 245
 246   bool inITBlock() { return ITState.CurPosition != ~0U; }
 247   bool inExplicitITBlock() { return inITBlock() && ITState.IsExplicit; }
 248   bool inImplicitITBlock() { return inITBlock() && !ITState.IsExplicit; }
 249
 250   bool lastInITBlock() {
 251     return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask);
 252   }
 253
 254   void forwardITPosition() {
 255     if (!inITBlock()) return;
 256     // Move to the next instruction in the IT block, if there is one. If not,
 257     // mark the block as done, except for implicit IT blocks, which we leave
 258     // open until we find an instruction that can't be added to it.
 259     unsigned TZ = countTrailingZeros(ITState.Mask);
 260     if (++ITState.CurPosition == 5 - TZ && ITState.IsExplicit)
 261       ITState.CurPosition = ~0U; // Done with the IT block after this.
 262   }
 263
 264   // Rewind the state of the current IT block, removing the last slot from it.
 265   void rewindImplicitITPosition() {
 266     assert(inImplicitITBlock());
 267     assert(ITState.CurPosition > 1);
 268     ITState.CurPosition--;
 269     unsigned TZ = countTrailingZeros(ITState.Mask);
 270     unsigned NewMask = 0;
 271     NewMask |= ITState.Mask & (0xC << TZ);
 272     NewMask |= 0x2 << TZ;
 273     ITState.Mask = NewMask;
 274   }
 275
 276   // Rewind the state of the current IT block, removing the last slot from it.
 277   // If we were at the first slot, this closes the IT block.
 278   void discardImplicitITBlock() {
 279     assert(inImplicitITBlock());
 280     assert(ITState.CurPosition == 1);
 281     ITState.CurPosition = ~0U;
 282   }
 283
 284   // Return the low-subreg of a given Q register.
 285   unsigned getDRegFromQReg(unsigned QReg) const {
 286     return MRI->getSubReg(QReg, ARM::dsub_0);
 287   }
 288
 289   // Get the encoding of the IT mask, as it will appear in an IT instruction.
 290   unsigned getITMaskEncoding() {
 291     assert(inITBlock());
 292     unsigned Mask = ITState.Mask;
 293     unsigned TZ = countTrailingZeros(Mask);
 294     if ((ITState.Cond & 1) == 0) {
 295       assert(Mask && TZ <= 3 && "illegal IT mask value!");
 296       Mask ^= (0xE << TZ) & 0xF;
 297     }
 298     return Mask;
 299   }
 300
 301   // Get the condition code corresponding to the current IT block slot.
 302   ARMCC::CondCodes currentITCond() {
 303     unsigned MaskBit;
 304     if (ITState.CurPosition == 1)
 305       MaskBit = 1;
 306     else
 307       MaskBit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
 308
 309     return MaskBit ? ITState.Cond : ARMCC::getOppositeCondition(ITState.Cond);
 310   }
 311
 312   // Invert the condition of the current IT block slot without changing any
 313   // other slots in the same block.
 314   void invertCurrentITCondition() {
 315     if (ITState.CurPosition == 1) {
 316       ITState.Cond = ARMCC::getOppositeCondition(ITState.Cond);
 317     } else {
 318       ITState.Mask ^= 1 << (5 - ITState.CurPosition);
 319     }
 320   }
 321
 322   // Returns true if the current IT block is full (all 4 slots used).
 323   bool isITBlockFull() {
 324     return inITBlock() && (ITState.Mask & 1);
 325   }
 326
 327   // Extend the current implicit IT block to have one more slot with the given
 328   // condition code.
 329   void extendImplicitITBlock(ARMCC::CondCodes Cond) {
 330     assert(inImplicitITBlock());
 331     assert(!isITBlockFull());
 332     assert(Cond == ITState.Cond ||
 333            Cond == ARMCC::getOppositeCondition(ITState.Cond));
 334     unsigned TZ = countTrailingZeros(ITState.Mask);
 335     unsigned NewMask = 0;
 336     // Keep any existing condition bits.
 337     NewMask |= ITState.Mask & (0xE << TZ);
 338     // Insert the new condition bit.
 339     NewMask |= (Cond == ITState.Cond) << TZ;
 340     // Move the trailing 1 down one bit.
 341     NewMask |= 1 << (TZ - 1);
 342     ITState.Mask = NewMask;
 343   }
 344
 345   // Create a new implicit IT block with a dummy condition code.
 346   void startImplicitITBlock() {
 347     assert(!inITBlock());
 348     ITState.Cond = ARMCC::AL;
 349     ITState.Mask = 8;
 350     ITState.CurPosition = 1;
 351     ITState.IsExplicit = false;
 352   }
 353
 354   // Create a new explicit IT block with the given condition and mask. The mask
 355   // should be in the parsed format, with a 1 implying 't', regardless of the
 356   // low bit of the condition.
 357   void startExplicitITBlock(ARMCC::CondCodes Cond, unsigned Mask) {
 358     assert(!inITBlock());
 359     ITState.Cond = Cond;
 360     ITState.Mask = Mask;
 361     ITState.CurPosition = 0;
 362     ITState.IsExplicit = true;
 363   }
 364
 365   void Note(SMLoc L, const Twine &Msg, SMRange Range = None) {
 366     return getParser().Note(L, Msg, Range);
 367   }
 368
 369   bool Warning(SMLoc L, const Twine &Msg, SMRange Range = None) {
 370     return getParser().Warning(L, Msg, Range);
 371   }
 372
 373   bool Error(SMLoc L, const Twine &Msg, SMRange Range = None) {
 374     return getParser().Error(L, Msg, Range);
 375   }
 376
 377   bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
 378                            unsigned ListNo, bool IsARPop = false);
 379   bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
 380                            unsigned ListNo);
 381
 382   int tryParseRegister();
 383   bool tryParseRegisterWithWriteBack(OperandVector &);
 384   int tryParseShiftRegister(OperandVector &);
 385   bool parseRegisterList(OperandVector &);
 386   bool parseMemory(OperandVector &);
 387   bool parseOperand(OperandVector &, StringRef Mnemonic);
 388   bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
 389   bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
 390                               unsigned &ShiftAmount);
 391   bool parseLiteralValues(unsigned Size, SMLoc L);
 392   bool parseDirectiveThumb(SMLoc L);
 393   bool parseDirectiveARM(SMLoc L);
 394   bool parseDirectiveThumbFunc(SMLoc L);
 395   bool parseDirectiveCode(SMLoc L);
 396   bool parseDirectiveSyntax(SMLoc L);
 397   bool parseDirectiveReq(StringRef Name, SMLoc L);
 398   bool parseDirectiveUnreq(SMLoc L);
 399   bool parseDirectiveArch(SMLoc L);
 400   bool parseDirectiveEabiAttr(SMLoc L);
 401   bool parseDirectiveCPU(SMLoc L);
 402   bool parseDirectiveFPU(SMLoc L);
 403   bool parseDirectiveFnStart(SMLoc L);
 404   bool parseDirectiveFnEnd(SMLoc L);
 405   bool parseDirectiveCantUnwind(SMLoc L);
 406   bool parseDirectivePersonality(SMLoc L);
 407   bool parseDirectiveHandlerData(SMLoc L);
 408   bool parseDirectiveSetFP(SMLoc L);
 409   bool parseDirectivePad(SMLoc L);
 410   bool parseDirectiveRegSave(SMLoc L, bool IsVector);
 411   bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
 412   bool parseDirectiveLtorg(SMLoc L);
 413   bool parseDirectiveEven(SMLoc L);
 414   bool parseDirectivePersonalityIndex(SMLoc L);
 415   bool parseDirectiveUnwindRaw(SMLoc L);
 416   bool parseDirectiveTLSDescSeq(SMLoc L);
 417   bool parseDirectiveMovSP(SMLoc L);
 418   bool parseDirectiveObjectArch(SMLoc L);
 419   bool parseDirectiveArchExtension(SMLoc L);
 420   bool parseDirectiveAlign(SMLoc L);
 421   bool parseDirectiveThumbSet(SMLoc L);
 422
 423   StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
 424                           bool &CarrySetting, unsigned &ProcessorIMod,
 425                           StringRef &ITMask);
 426   void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
 427                              bool &CanAcceptCarrySet,
 428                              bool &CanAcceptPredicationCode);
 429
 430   void tryConvertingToTwoOperandForm(StringRef Mnemonic, bool CarrySetting,
 431                                      OperandVector &Operands);
 432   bool isThumb() const {
 433     // FIXME: Can tablegen auto-generate this?
 434     return getSTI().getFeatureBits()[ARM::ModeThumb];
 435   }
 436
 437   bool isThumbOne() const {
 438     return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2];
 439   }
 440
 441   bool isThumbTwo() const {
 442     return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2];
 443   }
 444
 445   bool hasThumb() const {
 446     return getSTI().getFeatureBits()[ARM::HasV4TOps];
 447   }
 448
 449   bool hasThumb2() const {
 450     return getSTI().getFeatureBits()[ARM::FeatureThumb2];
 451   }
 452
 453   bool hasV6Ops() const {
 454     return getSTI().getFeatureBits()[ARM::HasV6Ops];
 455   }
 456
 457   bool hasV6T2Ops() const {
 458     return getSTI().getFeatureBits()[ARM::HasV6T2Ops];
 459   }
 460
 461   bool hasV6MOps() const {
 462     return getSTI().getFeatureBits()[ARM::HasV6MOps];
 463   }
 464
 465   bool hasV7Ops() const {
 466     return getSTI().getFeatureBits()[ARM::HasV7Ops];
 467   }
 468
 469   bool hasV8Ops() const {
 470     return getSTI().getFeatureBits()[ARM::HasV8Ops];
 471   }
 472
 473   bool hasV8MBaseline() const {
 474     return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps];
 475   }
 476
 477   bool hasV8MMainline() const {
 478     return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps];
 479   }
 480
 481   bool has8MSecExt() const {
 482     return getSTI().getFeatureBits()[ARM::Feature8MSecExt];
 483   }
 484
 485   bool hasARM() const {
 486     return !getSTI().getFeatureBits()[ARM::FeatureNoARM];
 487   }
 488
 489   bool hasDSP() const {
 490     return getSTI().getFeatureBits()[ARM::FeatureDSP];
 491   }
 492
 493   bool hasD16() const {
 494     return getSTI().getFeatureBits()[ARM::FeatureD16];
 495   }
 496
 497   bool hasV8_1aOps() const {
 498     return getSTI().getFeatureBits()[ARM::HasV8_1aOps];
 499   }
 500
 501   bool hasRAS() const {
 502     return getSTI().getFeatureBits()[ARM::FeatureRAS];
 503   }
 504
 505   void SwitchMode() {
 506     MCSubtargetInfo &STI = copySTI();
 507     uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
 508     setAvailableFeatures(FB);
 509   }
 510
 511   void FixModeAfterArchChange(bool WasThumb, SMLoc Loc);
 512
 513   bool isMClass() const {
 514     return getSTI().getFeatureBits()[ARM::FeatureMClass];
 515   }
 516
 517   /// @name Auto-generated Match Functions
 518   /// {
 519
 520 #define GET_ASSEMBLER_HEADER
 521 #include "ARMGenAsmMatcher.inc"
 522
 523   /// }
 524
 525   OperandMatchResultTy parseITCondCode(OperandVector &);
 526   OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
 527   OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
 528   OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
 529   OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
 530   OperandMatchResultTy parseTraceSyncBarrierOptOperand(OperandVector &);
 531   OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
 532   OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
 533   OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
 534   OperandMatchResultTy parseBankedRegOperand(OperandVector &);
 535   OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
 536                                    int High);
 537   OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
 538     return parsePKHImm(O, "lsl", 0, 31);
 539   }
 540   OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
 541     return parsePKHImm(O, "asr", 1, 32);
 542   }
 543   OperandMatchResultTy parseSetEndImm(OperandVector &);
 544   OperandMatchResultTy parseShifterImm(OperandVector &);
 545   OperandMatchResultTy parseRotImm(OperandVector &);
 546   OperandMatchResultTy parseModImm(OperandVector &);
 547   OperandMatchResultTy parseBitfield(OperandVector &);
 548   OperandMatchResultTy parsePostIdxReg(OperandVector &);
 549   OperandMatchResultTy parseAM3Offset(OperandVector &);
 550   OperandMatchResultTy parseFPImm(OperandVector &);
 551   OperandMatchResultTy parseVectorList(OperandVector &);
 552   OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
 553                                        SMLoc &EndLoc);
 554
 555   // Asm Match Converter Methods
 556   void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
 557   void cvtThumbBranches(MCInst &Inst, const OperandVector &);
 558
 559   bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
 560   bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
 561   bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
 562   bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
 563   bool isITBlockTerminator(MCInst &Inst) const;
 564   void fixupGNULDRDAlias(StringRef Mnemonic, OperandVector &Operands);
 565   bool validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands,
 566                         bool Load, bool ARMMode, bool Writeback);
 567
 568 public:
 569   enum ARMMatchResultTy {
 570     Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
 571     Match_RequiresNotITBlock,
 572     Match_RequiresV6,
 573     Match_RequiresThumb2,
 574     Match_RequiresV8,
 575     Match_RequiresFlagSetting,
 576 #define GET_OPERAND_DIAGNOSTIC_TYPES
 577 #include "ARMGenAsmMatcher.inc"
 578
 579   };
 580
 581   ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
 582                const MCInstrInfo &MII, const MCTargetOptions &Options)
 583     : MCTargetAsmParser(Options, STI, MII), UC(Parser) {
 584     MCAsmParserExtension::Initialize(Parser);
 585
 586     // Cache the MCRegisterInfo.
 587     MRI = getContext().getRegisterInfo();
 588
 589     // Initialize the set of available features.
 590     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
 591
 592     // Add build attributes based on the selected target.
 593     if (AddBuildAttributes)
 594       getTargetStreamer().emitTargetAttributes(STI);
 595
 596     // Not in an ITBlock to start with.
 597     ITState.CurPosition = ~0U;
 598
 599     NextSymbolIsThumb = false;
 600   }
 601
 602   // Implementation of the MCTargetAsmParser interface:
 603   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
 604   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
 605                         SMLoc NameLoc, OperandVector &Operands) override;
 606   bool ParseDirective(AsmToken DirectiveID) override;
 607
 608   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
 609                                       unsigned Kind) override;
 610   unsigned checkTargetMatchPredicate(MCInst &Inst) override;
 611
 612   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
 613                                OperandVector &Operands, MCStreamer &Out,
 614                                uint64_t &ErrorInfo,
 615                                bool MatchingInlineAsm) override;
 616   unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst,
 617                             SmallVectorImpl<NearMissInfo> &NearMisses,
 618                             bool MatchingInlineAsm, bool &EmitInITBlock,
 619                             MCStreamer &Out);
 620
 621   struct NearMissMessage {
 622     SMLoc Loc;
 623     SmallString<128> Message;
 624   };
 625
 626   const char *getCustomOperandDiag(ARMMatchResultTy MatchError);
 627
 628   void FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn,
 629                         SmallVectorImpl<NearMissMessage> &NearMissesOut,
 630                         SMLoc IDLoc, OperandVector &Operands);
 631   void ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses, SMLoc IDLoc,
 632                         OperandVector &Operands);
 633
 634   void doBeforeLabelEmit(MCSymbol *Symbol) override;
 635
 636   void onLabelParsed(MCSymbol *Symbol) override;
 637 };
 638
 639 /// ARMOperand - Instances of this class represent a parsed ARM machine
 640 /// operand.
 641 class ARMOperand : public MCParsedAsmOperand {
 642   enum KindTy {
 643     k_CondCode,
 644     k_CCOut,
 645     k_ITCondMask,
 646     k_CoprocNum,
 647     k_CoprocReg,
 648     k_CoprocOption,
 649     k_Immediate,
 650     k_MemBarrierOpt,
 651     k_InstSyncBarrierOpt,
 652     k_TraceSyncBarrierOpt,
 653     k_Memory,
 654     k_PostIndexRegister,
 655     k_MSRMask,
 656     k_BankedReg,
 657     k_ProcIFlags,
 658     k_VectorIndex,
 659     k_Register,
 660     k_RegisterList,
 661     k_DPRRegisterList,
 662     k_SPRRegisterList,
 663     k_VectorList,
 664     k_VectorListAllLanes,
 665     k_VectorListIndexed,
 666     k_ShiftedRegister,
 667     k_ShiftedImmediate,
 668     k_ShifterImmediate,
 669     k_RotateImmediate,
 670     k_ModifiedImmediate,
 671     k_ConstantPoolImmediate,
 672     k_BitfieldDescriptor,
 673     k_Token,
 674   } Kind;
 675
 676   SMLoc StartLoc, EndLoc, AlignmentLoc;
 677   SmallVector<unsigned, 8> Registers;
 678
 679   struct CCOp {
 680     ARMCC::CondCodes Val;
 681   };
 682
 683   struct CopOp {
 684     unsigned Val;
 685   };
 686
 687   struct CoprocOptionOp {
 688     unsigned Val;
 689   };
 690
 691   struct ITMaskOp {
 692     unsigned Mask:4;
 693   };
 694
 695   struct MBOptOp {
 696     ARM_MB::MemBOpt Val;
 697   };
 698
 699   struct ISBOptOp {
 700     ARM_ISB::InstSyncBOpt Val;
 701   };
 702
 703   struct TSBOptOp {
 704     ARM_TSB::TraceSyncBOpt Val;
 705   };
 706
 707   struct IFlagsOp {
 708     ARM_PROC::IFlags Val;
 709   };
 710
 711   struct MMaskOp {
 712     unsigned Val;
 713   };
 714
 715   struct BankedRegOp {
 716     unsigned Val;
 717   };
 718
 719   struct TokOp {
 720     const char *Data;
 721     unsigned Length;
 722   };
 723
 724   struct RegOp {
 725     unsigned RegNum;
 726   };
 727
 728   // A vector register list is a sequential list of 1 to 4 registers.
 729   struct VectorListOp {
 730     unsigned RegNum;
 731     unsigned Count;
 732     unsigned LaneIndex;
 733     bool isDoubleSpaced;
 734   };
 735
 736   struct VectorIndexOp {
 737     unsigned Val;
 738   };
 739
 740   struct ImmOp {
 741     const MCExpr *Val;
 742   };
 743
 744   /// Combined record for all forms of ARM address expressions.
 745   struct MemoryOp {
 746     unsigned BaseRegNum;
 747     // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
 748     // was specified.
 749     const MCConstantExpr *OffsetImm;  // Offset immediate value
 750     unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
 751     ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
 752     unsigned ShiftImm;        // shift for OffsetReg.
 753     unsigned Alignment;       // 0 = no alignment specified
 754     // n = alignment in bytes (2, 4, 8, 16, or 32)
 755     unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
 756   };
 757
 758   struct PostIdxRegOp {
 759     unsigned RegNum;
 760     bool isAdd;
 761     ARM_AM::ShiftOpc ShiftTy;
 762     unsigned ShiftImm;
 763   };
 764
 765   struct ShifterImmOp {
 766     bool isASR;
 767     unsigned Imm;
 768   };
 769
 770   struct RegShiftedRegOp {
 771     ARM_AM::ShiftOpc ShiftTy;
 772     unsigned SrcReg;
 773     unsigned ShiftReg;
 774     unsigned ShiftImm;
 775   };
 776
 777   struct RegShiftedImmOp {
 778     ARM_AM::ShiftOpc ShiftTy;
 779     unsigned SrcReg;
 780     unsigned ShiftImm;
 781   };
 782
 783   struct RotImmOp {
 784     unsigned Imm;
 785   };
 786
 787   struct ModImmOp {
 788     unsigned Bits;
 789     unsigned Rot;
 790   };
 791
 792   struct BitfieldOp {
 793     unsigned LSB;
 794     unsigned Width;
 795   };
 796
 797   union {
 798     struct CCOp CC;
 799     struct CopOp Cop;
 800     struct CoprocOptionOp CoprocOption;
 801     struct MBOptOp MBOpt;
 802     struct ISBOptOp ISBOpt;
 803     struct TSBOptOp TSBOpt;
 804     struct ITMaskOp ITMask;
 805     struct IFlagsOp IFlags;
 806     struct MMaskOp MMask;
 807     struct BankedRegOp BankedReg;
 808     struct TokOp Tok;
 809     struct RegOp Reg;
 810     struct VectorListOp VectorList;
 811     struct VectorIndexOp VectorIndex;
 812     struct ImmOp Imm;
 813     struct MemoryOp Memory;
 814     struct PostIdxRegOp PostIdxReg;
 815     struct ShifterImmOp ShifterImm;
 816     struct RegShiftedRegOp RegShiftedReg;
 817     struct RegShiftedImmOp RegShiftedImm;
 818     struct RotImmOp RotImm;
 819     struct ModImmOp ModImm;
 820     struct BitfieldOp Bitfield;
 821   };
 822
 823 public:
 824   ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
 825
 826   /// getStartLoc - Get the location of the first token of this operand.
 827   SMLoc getStartLoc() const override { return StartLoc; }
 828
 829   /// getEndLoc - Get the location of the last token of this operand.
 830   SMLoc getEndLoc() const override { return EndLoc; }
 831
 832   /// getLocRange - Get the range between the first and last token of this
 833   /// operand.
 834   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
 835
 836   /// getAlignmentLoc - Get the location of the Alignment token of this operand.
 837   SMLoc getAlignmentLoc() const {
 838     assert(Kind == k_Memory && "Invalid access!");
 839     return AlignmentLoc;
 840   }
 841
 842   ARMCC::CondCodes getCondCode() const {
 843     assert(Kind == k_CondCode && "Invalid access!");
 844     return CC.Val;
 845   }
 846
 847   unsigned getCoproc() const {
 848     assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
 849     return Cop.Val;
 850   }
 851
 852   StringRef getToken() const {
 853     assert(Kind == k_Token && "Invalid access!");
 854     return StringRef(Tok.Data, Tok.Length);
 855   }
 856
 857   unsigned getReg() const override {
 858     assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
 859     return Reg.RegNum;
 860   }
 861
 862   const SmallVectorImpl<unsigned> &getRegList() const {
 863     assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
 864             Kind == k_SPRRegisterList) && "Invalid access!");
 865     return Registers;
 866   }
 867
 868   const MCExpr *getImm() const {
 869     assert(isImm() && "Invalid access!");
 870     return Imm.Val;
 871   }
 872
 873   const MCExpr *getConstantPoolImm() const {
 874     assert(isConstantPoolImm() && "Invalid access!");
 875     return Imm.Val;
 876   }
 877
 878   unsigned getVectorIndex() const {
 879     assert(Kind == k_VectorIndex && "Invalid access!");
 880     return VectorIndex.Val;
 881   }
 882
 883   ARM_MB::MemBOpt getMemBarrierOpt() const {
 884     assert(Kind == k_MemBarrierOpt && "Invalid access!");
 885     return MBOpt.Val;
 886   }
 887
 888   ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
 889     assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
 890     return ISBOpt.Val;
 891   }
 892
 893   ARM_TSB::TraceSyncBOpt getTraceSyncBarrierOpt() const {
 894     assert(Kind == k_TraceSyncBarrierOpt && "Invalid access!");
 895     return TSBOpt.Val;
 896   }
 897
 898   ARM_PROC::IFlags getProcIFlags() const {
 899     assert(Kind == k_ProcIFlags && "Invalid access!");
 900     return IFlags.Val;
 901   }
 902
 903   unsigned getMSRMask() const {
 904     assert(Kind == k_MSRMask && "Invalid access!");
 905     return MMask.Val;
 906   }
 907
 908   unsigned getBankedReg() const {
 909     assert(Kind == k_BankedReg && "Invalid access!");
 910     return BankedReg.Val;
 911   }
 912
 913   bool isCoprocNum() const { return Kind == k_CoprocNum; }
 914   bool isCoprocReg() const { return Kind == k_CoprocReg; }
 915   bool isCoprocOption() const { return Kind == k_CoprocOption; }
 916   bool isCondCode() const { return Kind == k_CondCode; }
 917   bool isCCOut() const { return Kind == k_CCOut; }
 918   bool isITMask() const { return Kind == k_ITCondMask; }
 919   bool isITCondCode() const { return Kind == k_CondCode; }
 920   bool isImm() const override {
 921     return Kind == k_Immediate;
 922   }
 923
 924   bool isARMBranchTarget() const {
 925     if (!isImm()) return false;
 926
 927     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
 928       return CE->getValue() % 4 == 0;
 929     return true;
 930   }
 931
 932
 933   bool isThumbBranchTarget() const {
 934     if (!isImm()) return false;
 935
 936     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
 937       return CE->getValue() % 2 == 0;
 938     return true;
 939   }
 940
 941   // checks whether this operand is an unsigned offset which fits is a field
 942   // of specified width and scaled by a specific number of bits
 943   template<unsigned width, unsigned scale>
 944   bool isUnsignedOffset() const {
 945     if (!isImm()) return false;
 946     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
 947     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
 948       int64_t Val = CE->getValue();
 949       int64_t Align = 1LL << scale;
 950       int64_t Max = Align * ((1LL << width) - 1);
 951       return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
 952     }
 953     return false;
 954   }
 955
 956   // checks whether this operand is an signed offset which fits is a field
 957   // of specified width and scaled by a specific number of bits
 958   template<unsigned width, unsigned scale>
 959   bool isSignedOffset() const {
 960     if (!isImm()) return false;
 961     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
 962     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
 963       int64_t Val = CE->getValue();
 964       int64_t Align = 1LL << scale;
 965       int64_t Max = Align * ((1LL << (width-1)) - 1);
 966       int64_t Min = -Align * (1LL << (width-1));
 967       return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
 968     }
 969     return false;
 970   }
 971
 972   // checks whether this operand is a memory operand computed as an offset
 973   // applied to PC. the offset may have 8 bits of magnitude and is represented
 974   // with two bits of shift. textually it may be either [pc, #imm], #imm or
 975   // relocable expression...
 976   bool isThumbMemPC() const {
 977     int64_t Val = 0;
 978     if (isImm()) {
 979       if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
 980       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
 981       if (!CE) return false;
 982       Val = CE->getValue();
 983     }
 984     else if (isMem()) {
 985       if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
 986       if(Memory.BaseRegNum != ARM::PC) return false;
 987       Val = Memory.OffsetImm->getValue();
 988     }
 989     else return false;
 990     return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
 991   }
 992
 993   bool isFPImm() const {
 994     if (!isImm()) return false;
 995     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
 996     if (!CE) return false;
 997     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
 998     return Val != -1;
 999   }
1000
1001   template<int64_t N, int64_t M>
1002   bool isImmediate() const {
1003     if (!isImm()) return false;
1004     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1005     if (!CE) return false;
1006     int64_t Value = CE->getValue();
1007     return Value >= N && Value <= M;
1008   }
1009
1010   template<int64_t N, int64_t M>
1011   bool isImmediateS4() const {
1012     if (!isImm()) return false;
1013     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1014     if (!CE) return false;
1015     int64_t Value = CE->getValue();
1016     return ((Value & 3) == 0) && Value >= N && Value <= M;
1017   }
1018
1019   bool isFBits16() const {
1020     return isImmediate<0, 17>();
1021   }
1022   bool isFBits32() const {
1023     return isImmediate<1, 33>();
1024   }
1025   bool isImm8s4() const {
1026     return isImmediateS4<-1020, 1020>();
1027   }
1028   bool isImm0_1020s4() const {
1029     return isImmediateS4<0, 1020>();
1030   }
1031   bool isImm0_508s4() const {
1032     return isImmediateS4<0, 508>();
1033   }
1034   bool isImm0_508s4Neg() const {
1035     if (!isImm()) return false;
1036     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1037     if (!CE) return false;
1038     int64_t Value = -CE->getValue();
1039     // explicitly exclude zero. we want that to use the normal 0_508 version.
1040     return ((Value & 3) == 0) && Value > 0 && Value <= 508;
1041   }
1042
1043   bool isImm0_4095Neg() const {
1044     if (!isImm()) return false;
1045     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1046     if (!CE) return false;
1047     // isImm0_4095Neg is used with 32-bit immediates only.
1048     // 32-bit immediates are zero extended to 64-bit when parsed,
1049     // thus simple -CE->getValue() results in a big negative number,
1050     // not a small positive number as intended
1051     if ((CE->getValue() >> 32) > 0) return false;
1052     uint32_t Value = -static_cast<uint32_t>(CE->getValue());
1053     return Value > 0 && Value < 4096;
1054   }
1055
1056   bool isImm0_7() const {
1057     return isImmediate<0, 7>();
1058   }
1059
1060   bool isImm1_16() const {
1061     return isImmediate<1, 16>();
1062   }
1063
1064   bool isImm1_32() const {
1065     return isImmediate<1, 32>();
1066   }
1067
1068   bool isImm8_255() const {
1069     return isImmediate<8, 255>();
1070   }
1071
1072   bool isImm256_65535Expr() const {
1073     if (!isImm()) return false;
1074     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1075     // If it's not a constant expression, it'll generate a fixup and be
1076     // handled later.
1077     if (!CE) return true;
1078     int64_t Value = CE->getValue();
1079     return Value >= 256 && Value < 65536;
1080   }
1081
1082   bool isImm0_65535Expr() const {
1083     if (!isImm()) return false;
1084     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1085     // If it's not a constant expression, it'll generate a fixup and be
1086     // handled later.
1087     if (!CE) return true;
1088     int64_t Value = CE->getValue();
1089     return Value >= 0 && Value < 65536;
1090   }
1091
1092   bool isImm24bit() const {
1093     return isImmediate<0, 0xffffff + 1>();
1094   }
1095
1096   bool isImmThumbSR() const {
1097     return isImmediate<1, 33>();
1098   }
1099
1100   bool isPKHLSLImm() const {
1101     return isImmediate<0, 32>();
1102   }
1103
1104   bool isPKHASRImm() const {
1105     return isImmediate<0, 33>();
1106   }
1107
1108   bool isAdrLabel() const {
1109     // If we have an immediate that's not a constant, treat it as a label
1110     // reference needing a fixup.
1111     if (isImm() && !isa<MCConstantExpr>(getImm()))
1112       return true;
1113
1114     // If it is a constant, it must fit into a modified immediate encoding.
1115     if (!isImm()) return false;
1116     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1117     if (!CE) return false;
1118     int64_t Value = CE->getValue();
1119     return (ARM_AM::getSOImmVal(Value) != -1 ||
1120             ARM_AM::getSOImmVal(-Value) != -1);
1121   }
1122
1123   bool isT2SOImm() const {
1124     // If we have an immediate that's not a constant, treat it as an expression
1125     // needing a fixup.
1126     if (isImm() && !isa<MCConstantExpr>(getImm())) {
1127       // We want to avoid matching :upper16: and :lower16: as we want these
1128       // expressions to match in isImm0_65535Expr()
1129       const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(getImm());
1130       return (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
1131                              ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16));
1132     }
1133     if (!isImm()) return false;
1134     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1135     if (!CE) return false;
1136     int64_t Value = CE->getValue();
1137     return ARM_AM::getT2SOImmVal(Value) != -1;
1138   }
1139
1140   bool isT2SOImmNot() const {
1141     if (!isImm()) return false;
1142     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1143     if (!CE) return false;
1144     int64_t Value = CE->getValue();
1145     return ARM_AM::getT2SOImmVal(Value) == -1 &&
1146       ARM_AM::getT2SOImmVal(~Value) != -1;
1147   }
1148
1149   bool isT2SOImmNeg() const {
1150     if (!isImm()) return false;
1151     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1152     if (!CE) return false;
1153     int64_t Value = CE->getValue();
1154     // Only use this when not representable as a plain so_imm.
1155     return ARM_AM::getT2SOImmVal(Value) == -1 &&
1156       ARM_AM::getT2SOImmVal(-Value) != -1;
1157   }
1158
1159   bool isSetEndImm() const {
1160     if (!isImm()) return false;
1161     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1162     if (!CE) return false;
1163     int64_t Value = CE->getValue();
1164     return Value == 1 || Value == 0;
1165   }
1166
1167   bool isReg() const override { return Kind == k_Register; }
1168   bool isRegList() const { return Kind == k_RegisterList; }
1169   bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1170   bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1171   bool isToken() const override { return Kind == k_Token; }
1172   bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1173   bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1174   bool isTraceSyncBarrierOpt() const { return Kind == k_TraceSyncBarrierOpt; }
1175   bool isMem() const override {
1176     if (Kind != k_Memory)
1177       return false;
1178     if (Memory.BaseRegNum &&
1179         !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum))
1180       return false;
1181     if (Memory.OffsetRegNum &&
1182         !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.OffsetRegNum))
1183       return false;
1184     return true;
1185   }
1186   bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1187   bool isRegShiftedReg() const {
1188     return Kind == k_ShiftedRegister &&
1189            ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1190                RegShiftedReg.SrcReg) &&
1191            ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1192                RegShiftedReg.ShiftReg);
1193   }
1194   bool isRegShiftedImm() const {
1195     return Kind == k_ShiftedImmediate &&
1196            ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1197                RegShiftedImm.SrcReg);
1198   }
1199   bool isRotImm() const { return Kind == k_RotateImmediate; }
1200   bool isModImm() const { return Kind == k_ModifiedImmediate; }
1201
1202   bool isModImmNot() const {
1203     if (!isImm()) return false;
1204     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1205     if (!CE) return false;
1206     int64_t Value = CE->getValue();
1207     return ARM_AM::getSOImmVal(~Value) != -1;
1208   }
1209
1210   bool isModImmNeg() const {
1211     if (!isImm()) return false;
1212     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1213     if (!CE) return false;
1214     int64_t Value = CE->getValue();
1215     return ARM_AM::getSOImmVal(Value) == -1 &&
1216       ARM_AM::getSOImmVal(-Value) != -1;
1217   }
1218
1219   bool isThumbModImmNeg1_7() const {
1220     if (!isImm()) return false;
1221     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1222     if (!CE) return false;
1223     int32_t Value = -(int32_t)CE->getValue();
1224     return 0 < Value && Value < 8;
1225   }
1226
1227   bool isThumbModImmNeg8_255() const {
1228     if (!isImm()) return false;
1229     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1230     if (!CE) return false;
1231     int32_t Value = -(int32_t)CE->getValue();
1232     return 7 < Value && Value < 256;
1233   }
1234
1235   bool isConstantPoolImm() const { return Kind == k_ConstantPoolImmediate; }
1236   bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1237   bool isPostIdxRegShifted() const {
1238     return Kind == k_PostIndexRegister &&
1239            ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum);
1240   }
1241   bool isPostIdxReg() const {
1242     return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift;
1243   }
1244   bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1245     if (!isMem())
1246       return false;
1247     // No offset of any kind.
1248     return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1249      (alignOK || Memory.Alignment == Alignment);
1250   }
1251   bool isMemPCRelImm12() const {
1252     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1253       return false;
1254     // Base register must be PC.
1255     if (Memory.BaseRegNum != ARM::PC)
1256       return false;
1257     // Immediate offset in range [-4095, 4095].
1258     if (!Memory.OffsetImm) return true;
1259     int64_t Val = Memory.OffsetImm->getValue();
1260     return (Val > -4096 && Val < 4096) ||
1261            (Val == std::numeric_limits<int32_t>::min());
1262   }
1263
1264   bool isAlignedMemory() const {
1265     return isMemNoOffset(true);
1266   }
1267
1268   bool isAlignedMemoryNone() const {
1269     return isMemNoOffset(false, 0);
1270   }
1271
1272   bool isDupAlignedMemoryNone() const {
1273     return isMemNoOffset(false, 0);
1274   }
1275
1276   bool isAlignedMemory16() const {
1277     if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1278       return true;
1279     return isMemNoOffset(false, 0);
1280   }
1281
1282   bool isDupAlignedMemory16() const {
1283     if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1284       return true;
1285     return isMemNoOffset(false, 0);
1286   }
1287
1288   bool isAlignedMemory32() const {
1289     if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1290       return true;
1291     return isMemNoOffset(false, 0);
1292   }
1293
1294   bool isDupAlignedMemory32() const {
1295     if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1296       return true;
1297     return isMemNoOffset(false, 0);
1298   }
1299
1300   bool isAlignedMemory64() const {
1301     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1302       return true;
1303     return isMemNoOffset(false, 0);
1304   }
1305
1306   bool isDupAlignedMemory64() const {
1307     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1308       return true;
1309     return isMemNoOffset(false, 0);
1310   }
1311
1312   bool isAlignedMemory64or128() const {
1313     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1314       return true;
1315     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1316       return true;
1317     return isMemNoOffset(false, 0);
1318   }
1319
1320   bool isDupAlignedMemory64or128() const {
1321     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1322       return true;
1323     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1324       return true;
1325     return isMemNoOffset(false, 0);
1326   }
1327
1328   bool isAlignedMemory64or128or256() const {
1329     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1330       return true;
1331     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1332       return true;
1333     if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1334       return true;
1335     return isMemNoOffset(false, 0);
1336   }
1337
1338   bool isAddrMode2() const {
1339     if (!isMem() || Memory.Alignment != 0) return false;
1340     // Check for register offset.
1341     if (Memory.OffsetRegNum) return true;
1342     // Immediate offset in range [-4095, 4095].
1343     if (!Memory.OffsetImm) return true;
1344     int64_t Val = Memory.OffsetImm->getValue();
1345     return Val > -4096 && Val < 4096;
1346   }
1347
1348   bool isAM2OffsetImm() const {
1349     if (!isImm()) return false;
1350     // Immediate offset in range [-4095, 4095].
1351     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1352     if (!CE) return false;
1353     int64_t Val = CE->getValue();
1354     return (Val == std::numeric_limits<int32_t>::min()) ||
1355            (Val > -4096 && Val < 4096);
1356   }
1357
1358   bool isAddrMode3() const {
1359     // If we have an immediate that's not a constant, treat it as a label
1360     // reference needing a fixup. If it is a constant, it's something else
1361     // and we reject it.
1362     if (isImm() && !isa<MCConstantExpr>(getImm()))
1363       return true;
1364     if (!isMem() || Memory.Alignment != 0) return false;
1365     // No shifts are legal for AM3.
1366     if (Memory.ShiftType != ARM_AM::no_shift) return false;
1367     // Check for register offset.
1368     if (Memory.OffsetRegNum) return true;
1369     // Immediate offset in range [-255, 255].
1370     if (!Memory.OffsetImm) return true;
1371     int64_t Val = Memory.OffsetImm->getValue();
1372     // The #-0 offset is encoded as std::numeric_limits<int32_t>::min(), and we
1373     // have to check for this too.
1374     return (Val > -256 && Val < 256) ||
1375            Val == std::numeric_limits<int32_t>::min();
1376   }
1377
1378   bool isAM3Offset() const {
1379     if (isPostIdxReg())
1380       return true;
1381     if (!isImm())
1382       return false;
1383     // Immediate offset in range [-255, 255].
1384     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1385     if (!CE) return false;
1386     int64_t Val = CE->getValue();
1387     // Special case, #-0 is std::numeric_limits<int32_t>::min().
1388     return (Val > -256 && Val < 256) ||
1389            Val == std::numeric_limits<int32_t>::min();
1390   }
1391
1392   bool isAddrMode5() const {
1393     // If we have an immediate that's not a constant, treat it as a label
1394     // reference needing a fixup. If it is a constant, it's something else
1395     // and we reject it.
1396     if (isImm() && !isa<MCConstantExpr>(getImm()))
1397       return true;
1398     if (!isMem() || Memory.Alignment != 0) return false;
1399     // Check for register offset.
1400     if (Memory.OffsetRegNum) return false;
1401     // Immediate offset in range [-1020, 1020] and a multiple of 4.
1402     if (!Memory.OffsetImm) return true;
1403     int64_t Val = Memory.OffsetImm->getValue();
1404     return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1405       Val == std::numeric_limits<int32_t>::min();
1406   }
1407
1408   bool isAddrMode5FP16() const {
1409     // If we have an immediate that's not a constant, treat it as a label
1410     // reference needing a fixup. If it is a constant, it's something else
1411     // and we reject it.
1412     if (isImm() && !isa<MCConstantExpr>(getImm()))
1413       return true;
1414     if (!isMem() || Memory.Alignment != 0) return false;
1415     // Check for register offset.
1416     if (Memory.OffsetRegNum) return false;
1417     // Immediate offset in range [-510, 510] and a multiple of 2.
1418     if (!Memory.OffsetImm) return true;
1419     int64_t Val = Memory.OffsetImm->getValue();
1420     return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) ||
1421            Val == std::numeric_limits<int32_t>::min();
1422   }
1423
1424   bool isMemTBB() const {
1425     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1426         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1427       return false;
1428     return true;
1429   }
1430
1431   bool isMemTBH() const {
1432     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1433         Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1434         Memory.Alignment != 0 )
1435       return false;
1436     return true;
1437   }
1438
1439   bool isMemRegOffset() const {
1440     if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1441       return false;
1442     return true;
1443   }
1444
1445   bool isT2MemRegOffset() const {
1446     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1447         Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC)
1448       return false;
1449     // Only lsl #{0, 1, 2, 3} allowed.
1450     if (Memory.ShiftType == ARM_AM::no_shift)
1451       return true;
1452     if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1453       return false;
1454     return true;
1455   }
1456
1457   bool isMemThumbRR() const {
1458     // Thumb reg+reg addressing is simple. Just two registers, a base and
1459     // an offset. No shifts, negations or any other complicating factors.
1460     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1461         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1462       return false;
1463     return isARMLowRegister(Memory.BaseRegNum) &&
1464       (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1465   }
1466
1467   bool isMemThumbRIs4() const {
1468     if (!isMem() || Memory.OffsetRegNum != 0 ||
1469         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1470       return false;
1471     // Immediate offset, multiple of 4 in range [0, 124].
1472     if (!Memory.OffsetImm) return true;
1473     int64_t Val = Memory.OffsetImm->getValue();
1474     return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1475   }
1476
1477   bool isMemThumbRIs2() const {
1478     if (!isMem() || Memory.OffsetRegNum != 0 ||
1479         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1480       return false;
1481     // Immediate offset, multiple of 4 in range [0, 62].
1482     if (!Memory.OffsetImm) return true;
1483     int64_t Val = Memory.OffsetImm->getValue();
1484     return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1485   }
1486
1487   bool isMemThumbRIs1() const {
1488     if (!isMem() || Memory.OffsetRegNum != 0 ||
1489         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1490       return false;
1491     // Immediate offset in range [0, 31].
1492     if (!Memory.OffsetImm) return true;
1493     int64_t Val = Memory.OffsetImm->getValue();
1494     return Val >= 0 && Val <= 31;
1495   }
1496
1497   bool isMemThumbSPI() const {
1498     if (!isMem() || Memory.OffsetRegNum != 0 ||
1499         Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1500       return false;
1501     // Immediate offset, multiple of 4 in range [0, 1020].
1502     if (!Memory.OffsetImm) return true;
1503     int64_t Val = Memory.OffsetImm->getValue();
1504     return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1505   }
1506
1507   bool isMemImm8s4Offset() const {
1508     // If we have an immediate that's not a constant, treat it as a label
1509     // reference needing a fixup. If it is a constant, it's something else
1510     // and we reject it.
1511     if (isImm() && !isa<MCConstantExpr>(getImm()))
1512       return true;
1513     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1514       return false;
1515     // Immediate offset a multiple of 4 in range [-1020, 1020].
1516     if (!Memory.OffsetImm) return true;
1517     int64_t Val = Memory.OffsetImm->getValue();
1518     // Special case, #-0 is std::numeric_limits<int32_t>::min().
1519     return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) ||
1520            Val == std::numeric_limits<int32_t>::min();
1521   }
1522
1523   bool isMemImm0_1020s4Offset() const {
1524     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1525       return false;
1526     // Immediate offset a multiple of 4 in range [0, 1020].
1527     if (!Memory.OffsetImm) return true;
1528     int64_t Val = Memory.OffsetImm->getValue();
1529     return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1530   }
1531
1532   bool isMemImm8Offset() const {
1533     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1534       return false;
1535     // Base reg of PC isn't allowed for these encodings.
1536     if (Memory.BaseRegNum == ARM::PC) return false;
1537     // Immediate offset in range [-255, 255].
1538     if (!Memory.OffsetImm) return true;
1539     int64_t Val = Memory.OffsetImm->getValue();
1540     return (Val == std::numeric_limits<int32_t>::min()) ||
1541            (Val > -256 && Val < 256);
1542   }
1543
1544   bool isMemPosImm8Offset() const {
1545     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1546       return false;
1547     // Immediate offset in range [0, 255].
1548     if (!Memory.OffsetImm) return true;
1549     int64_t Val = Memory.OffsetImm->getValue();
1550     return Val >= 0 && Val < 256;
1551   }
1552
1553   bool isMemNegImm8Offset() const {
1554     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1555       return false;
1556     // Base reg of PC isn't allowed for these encodings.
1557     if (Memory.BaseRegNum == ARM::PC) return false;
1558     // Immediate offset in range [-255, -1].
1559     if (!Memory.OffsetImm) return false;
1560     int64_t Val = Memory.OffsetImm->getValue();
1561     return (Val == std::numeric_limits<int32_t>::min()) ||
1562            (Val > -256 && Val < 0);
1563   }
1564
1565   bool isMemUImm12Offset() const {
1566     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1567       return false;
1568     // Immediate offset in range [0, 4095].
1569     if (!Memory.OffsetImm) return true;
1570     int64_t Val = Memory.OffsetImm->getValue();
1571     return (Val >= 0 && Val < 4096);
1572   }
1573
1574   bool isMemImm12Offset() const {
1575     // If we have an immediate that's not a constant, treat it as a label
1576     // reference needing a fixup. If it is a constant, it's something else
1577     // and we reject it.
1578
1579     if (isImm() && !isa<MCConstantExpr>(getImm()))
1580       return true;
1581
1582     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1583       return false;
1584     // Immediate offset in range [-4095, 4095].
1585     if (!Memory.OffsetImm) return true;
1586     int64_t Val = Memory.OffsetImm->getValue();
1587     return (Val > -4096 && Val < 4096) ||
1588            (Val == std::numeric_limits<int32_t>::min());
1589   }
1590
1591   bool isConstPoolAsmImm() const {
1592     // Delay processing of Constant Pool Immediate, this will turn into
1593     // a constant. Match no other operand
1594     return (isConstantPoolImm());
1595   }
1596
1597   bool isPostIdxImm8() const {
1598     if (!isImm()) return false;
1599     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1600     if (!CE) return false;
1601     int64_t Val = CE->getValue();
1602     return (Val > -256 && Val < 256) ||
1603            (Val == std::numeric_limits<int32_t>::min());
1604   }
1605
1606   bool isPostIdxImm8s4() const {
1607     if (!isImm()) return false;
1608     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1609     if (!CE) return false;
1610     int64_t Val = CE->getValue();
1611     return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1612            (Val == std::numeric_limits<int32_t>::min());
1613   }
1614
1615   bool isMSRMask() const { return Kind == k_MSRMask; }
1616   bool isBankedReg() const { return Kind == k_BankedReg; }
1617   bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1618
1619   // NEON operands.
1620   bool isSingleSpacedVectorList() const {
1621     return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1622   }
1623
1624   bool isDoubleSpacedVectorList() const {
1625     return Kind == k_VectorList && VectorList.isDoubleSpaced;
1626   }
1627
1628   bool isVecListOneD() const {
1629     if (!isSingleSpacedVectorList()) return false;
1630     return VectorList.Count == 1;
1631   }
1632
1633   bool isVecListDPair() const {
1634     if (!isSingleSpacedVectorList()) return false;
1635     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1636               .contains(VectorList.RegNum));
1637   }
1638
1639   bool isVecListThreeD() const {
1640     if (!isSingleSpacedVectorList()) return false;
1641     return VectorList.Count == 3;
1642   }
1643
1644   bool isVecListFourD() const {
1645     if (!isSingleSpacedVectorList()) return false;
1646     return VectorList.Count == 4;
1647   }
1648
1649   bool isVecListDPairSpaced() const {
1650     if (Kind != k_VectorList) return false;
1651     if (isSingleSpacedVectorList()) return false;
1652     return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1653               .contains(VectorList.RegNum));
1654   }
1655
1656   bool isVecListThreeQ() const {
1657     if (!isDoubleSpacedVectorList()) return false;
1658     return VectorList.Count == 3;
1659   }
1660
1661   bool isVecListFourQ() const {
1662     if (!isDoubleSpacedVectorList()) return false;
1663     return VectorList.Count == 4;
1664   }
1665
1666   bool isSingleSpacedVectorAllLanes() const {
1667     return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1668   }
1669
1670   bool isDoubleSpacedVectorAllLanes() const {
1671     return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1672   }
1673
1674   bool isVecListOneDAllLanes() const {
1675     if (!isSingleSpacedVectorAllLanes()) return false;
1676     return VectorList.Count == 1;
1677   }
1678
1679   bool isVecListDPairAllLanes() const {
1680     if (!isSingleSpacedVectorAllLanes()) return false;
1681     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1682               .contains(VectorList.RegNum));
1683   }
1684
1685   bool isVecListDPairSpacedAllLanes() const {
1686     if (!isDoubleSpacedVectorAllLanes()) return false;
1687     return VectorList.Count == 2;
1688   }
1689
1690   bool isVecListThreeDAllLanes() const {
1691     if (!isSingleSpacedVectorAllLanes()) return false;
1692     return VectorList.Count == 3;
1693   }
1694
1695   bool isVecListThreeQAllLanes() const {
1696     if (!isDoubleSpacedVectorAllLanes()) return false;
1697     return VectorList.Count == 3;
1698   }
1699
1700   bool isVecListFourDAllLanes() const {
1701     if (!isSingleSpacedVectorAllLanes()) return false;
1702     return VectorList.Count == 4;
1703   }
1704
1705   bool isVecListFourQAllLanes() const {
1706     if (!isDoubleSpacedVectorAllLanes()) return false;
1707     return VectorList.Count == 4;
1708   }
1709
1710   bool isSingleSpacedVectorIndexed() const {
1711     return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1712   }
1713
1714   bool isDoubleSpacedVectorIndexed() const {
1715     return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1716   }
1717
1718   bool isVecListOneDByteIndexed() const {
1719     if (!isSingleSpacedVectorIndexed()) return false;
1720     return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1721   }
1722
1723   bool isVecListOneDHWordIndexed() const {
1724     if (!isSingleSpacedVectorIndexed()) return false;
1725     return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1726   }
1727
1728   bool isVecListOneDWordIndexed() const {
1729     if (!isSingleSpacedVectorIndexed()) return false;
1730     return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1731   }
1732
1733   bool isVecListTwoDByteIndexed() const {
1734     if (!isSingleSpacedVectorIndexed()) return false;
1735     return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1736   }
1737
1738   bool isVecListTwoDHWordIndexed() const {
1739     if (!isSingleSpacedVectorIndexed()) return false;
1740     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1741   }
1742
1743   bool isVecListTwoQWordIndexed() const {
1744     if (!isDoubleSpacedVectorIndexed()) return false;
1745     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1746   }
1747
1748   bool isVecListTwoQHWordIndexed() const {
1749     if (!isDoubleSpacedVectorIndexed()) return false;
1750     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1751   }
1752
1753   bool isVecListTwoDWordIndexed() const {
1754     if (!isSingleSpacedVectorIndexed()) return false;
1755     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1756   }
1757
1758   bool isVecListThreeDByteIndexed() const {
1759     if (!isSingleSpacedVectorIndexed()) return false;
1760     return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1761   }
1762
1763   bool isVecListThreeDHWordIndexed() const {
1764     if (!isSingleSpacedVectorIndexed()) return false;
1765     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1766   }
1767
1768   bool isVecListThreeQWordIndexed() const {
1769     if (!isDoubleSpacedVectorIndexed()) return false;
1770     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1771   }
1772
1773   bool isVecListThreeQHWordIndexed() const {
1774     if (!isDoubleSpacedVectorIndexed()) return false;
1775     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1776   }
1777
1778   bool isVecListThreeDWordIndexed() const {
1779     if (!isSingleSpacedVectorIndexed()) return false;
1780     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1781   }
1782
1783   bool isVecListFourDByteIndexed() const {
1784     if (!isSingleSpacedVectorIndexed()) return false;
1785     return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1786   }
1787
1788   bool isVecListFourDHWordIndexed() const {
1789     if (!isSingleSpacedVectorIndexed()) return false;
1790     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1791   }
1792
1793   bool isVecListFourQWordIndexed() const {
1794     if (!isDoubleSpacedVectorIndexed()) return false;
1795     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1796   }
1797
1798   bool isVecListFourQHWordIndexed() const {
1799     if (!isDoubleSpacedVectorIndexed()) return false;
1800     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1801   }
1802
1803   bool isVecListFourDWordIndexed() const {
1804     if (!isSingleSpacedVectorIndexed()) return false;
1805     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1806   }
1807
1808   bool isVectorIndex8() const {
1809     if (Kind != k_VectorIndex) return false;
1810     return VectorIndex.Val < 8;
1811   }
1812
1813   bool isVectorIndex16() const {
1814     if (Kind != k_VectorIndex) return false;
1815     return VectorIndex.Val < 4;
1816   }
1817
1818   bool isVectorIndex32() const {
1819     if (Kind != k_VectorIndex) return false;
1820     return VectorIndex.Val < 2;
1821   }
1822   bool isVectorIndex64() const {
1823     if (Kind != k_VectorIndex) return false;
1824     return VectorIndex.Val < 1;
1825   }
1826
1827   bool isNEONi8splat() const {
1828     if (!isImm()) return false;
1829     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1830     // Must be a constant.
1831     if (!CE) return false;
1832     int64_t Value = CE->getValue();
1833     // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1834     // value.
1835     return Value >= 0 && Value < 256;
1836   }
1837
1838   bool isNEONi16splat() const {
1839     if (isNEONByteReplicate(2))
1840       return false; // Leave that for bytes replication and forbid by default.
1841     if (!isImm())
1842       return false;
1843     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1844     // Must be a constant.
1845     if (!CE) return false;
1846     unsigned Value = CE->getValue();
1847     return ARM_AM::isNEONi16splat(Value);
1848   }
1849
1850   bool isNEONi16splatNot() const {
1851     if (!isImm())
1852       return false;
1853     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1854     // Must be a constant.
1855     if (!CE) return false;
1856     unsigned Value = CE->getValue();
1857     return ARM_AM::isNEONi16splat(~Value & 0xffff);
1858   }
1859
1860   bool isNEONi32splat() const {
1861     if (isNEONByteReplicate(4))
1862       return false; // Leave that for bytes replication and forbid by default.
1863     if (!isImm())
1864       return false;
1865     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1866     // Must be a constant.
1867     if (!CE) return false;
1868     unsigned Value = CE->getValue();
1869     return ARM_AM::isNEONi32splat(Value);
1870   }
1871
1872   bool isNEONi32splatNot() const {
1873     if (!isImm())
1874       return false;
1875     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1876     // Must be a constant.
1877     if (!CE) return false;
1878     unsigned Value = CE->getValue();
1879     return ARM_AM::isNEONi32splat(~Value);
1880   }
1881
1882   static bool isValidNEONi32vmovImm(int64_t Value) {
1883     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1884     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1885     return ((Value & 0xffffffffffffff00) == 0) ||
1886            ((Value & 0xffffffffffff00ff) == 0) ||
1887            ((Value & 0xffffffffff00ffff) == 0) ||
1888            ((Value & 0xffffffff00ffffff) == 0) ||
1889            ((Value & 0xffffffffffff00ff) == 0xff) ||
1890            ((Value & 0xffffffffff00ffff) == 0xffff);
1891   }
1892
1893   bool isNEONReplicate(unsigned Width, unsigned NumElems, bool Inv) const {
1894     assert((Width == 8 || Width == 16 || Width == 32) &&
1895            "Invalid element width");
1896     assert(NumElems * Width <= 64 && "Invalid result width");
1897
1898     if (!isImm())
1899       return false;
1900     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1901     // Must be a constant.
1902     if (!CE)
1903       return false;
1904     int64_t Value = CE->getValue();
1905     if (!Value)
1906       return false; // Don't bother with zero.
1907     if (Inv)
1908       Value = ~Value;
1909
1910     uint64_t Mask = (1ull << Width) - 1;
1911     uint64_t Elem = Value & Mask;
1912     if (Width == 16 && (Elem & 0x00ff) != 0 && (Elem & 0xff00) != 0)
1913       return false;
1914     if (Width == 32 && !isValidNEONi32vmovImm(Elem))
1915       return false;
1916
1917     for (unsigned i = 1; i < NumElems; ++i) {
1918       Value >>= Width;
1919       if ((Value & Mask) != Elem)
1920         return false;
1921     }
1922     return true;
1923   }
1924
1925   bool isNEONByteReplicate(unsigned NumBytes) const {
1926     return isNEONReplicate(8, NumBytes, false);
1927   }
1928
1929   static void checkNeonReplicateArgs(unsigned FromW, unsigned ToW) {
1930     assert((FromW == 8 || FromW == 16 || FromW == 32) &&
1931            "Invalid source width");
1932     assert((ToW == 16 || ToW == 32 || ToW == 64) &&
1933            "Invalid destination width");
1934     assert(FromW < ToW && "ToW is not less than FromW");
1935   }
1936
1937   template<unsigned FromW, unsigned ToW>
1938   bool isNEONmovReplicate() const {
1939     checkNeonReplicateArgs(FromW, ToW);
1940     if (ToW == 64 && isNEONi64splat())
1941       return false;
1942     return isNEONReplicate(FromW, ToW / FromW, false);
1943   }
1944
1945   template<unsigned FromW, unsigned ToW>
1946   bool isNEONinvReplicate() const {
1947     checkNeonReplicateArgs(FromW, ToW);
1948     return isNEONReplicate(FromW, ToW / FromW, true);
1949   }
1950
1951   bool isNEONi32vmov() const {
1952     if (isNEONByteReplicate(4))
1953       return false; // Let it to be classified as byte-replicate case.
1954     if (!isImm())
1955       return false;
1956     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1957     // Must be a constant.
1958     if (!CE)
1959       return false;
1960     return isValidNEONi32vmovImm(CE->getValue());
1961   }
1962
1963   bool isNEONi32vmovNeg() const {
1964     if (!isImm()) return false;
1965     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1966     // Must be a constant.
1967     if (!CE) return false;
1968     return isValidNEONi32vmovImm(~CE->getValue());
1969   }
1970
1971   bool isNEONi64splat() const {
1972     if (!isImm()) return false;
1973     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1974     // Must be a constant.
1975     if (!CE) return false;
1976     uint64_t Value = CE->getValue();
1977     // i64 value with each byte being either 0 or 0xff.
1978     for (unsigned i = 0; i < 8; ++i, Value >>= 8)
1979       if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1980     return true;
1981   }
1982
1983   template<int64_t Angle, int64_t Remainder>
1984   bool isComplexRotation() const {
1985     if (!isImm()) return false;
1986
1987     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1988     if (!CE) return false;
1989     uint64_t Value = CE->getValue();
1990
1991     return (Value % Angle == Remainder && Value <= 270);
1992   }
1993
1994   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1995     // Add as immediates when possible.  Null MCExpr = 0.
1996     if (!Expr)
1997       Inst.addOperand(MCOperand::createImm(0));
1998     else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1999       Inst.addOperand(MCOperand::createImm(CE->getValue()));
2000     else
2001       Inst.addOperand(MCOperand::createExpr(Expr));
2002   }
2003
2004   void addARMBranchTargetOperands(MCInst &Inst, unsigned N) const {
2005     assert(N == 1 && "Invalid number of operands!");
2006     addExpr(Inst, getImm());
2007   }
2008
2009   void addThumbBranchTargetOperands(MCInst &Inst, unsigned N) const {
2010     assert(N == 1 && "Invalid number of operands!");
2011     addExpr(Inst, getImm());
2012   }
2013
2014   void addCondCodeOperands(MCInst &Inst, unsigned N) const {
2015     assert(N == 2 && "Invalid number of operands!");
2016     Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
2017     unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
2018     Inst.addOperand(MCOperand::createReg(RegNum));
2019   }
2020
2021   void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
2022     assert(N == 1 && "Invalid number of operands!");
2023     Inst.addOperand(MCOperand::createImm(getCoproc()));
2024   }
2025
2026   void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
2027     assert(N == 1 && "Invalid number of operands!");
2028     Inst.addOperand(MCOperand::createImm(getCoproc()));
2029   }
2030
2031   void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
2032     assert(N == 1 && "Invalid number of operands!");
2033     Inst.addOperand(MCOperand::createImm(CoprocOption.Val));
2034   }
2035
2036   void addITMaskOperands(MCInst &Inst, unsigned N) const {
2037     assert(N == 1 && "Invalid number of operands!");
2038     Inst.addOperand(MCOperand::createImm(ITMask.Mask));
2039   }
2040
2041   void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
2042     assert(N == 1 && "Invalid number of operands!");
2043     Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
2044   }
2045
2046   void addCCOutOperands(MCInst &Inst, unsigned N) const {
2047     assert(N == 1 && "Invalid number of operands!");
2048     Inst.addOperand(MCOperand::createReg(getReg()));
2049   }
2050
2051   void addRegOperands(MCInst &Inst, unsigned N) const {
2052     assert(N == 1 && "Invalid number of operands!");
2053     Inst.addOperand(MCOperand::createReg(getReg()));
2054   }
2055
2056   void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
2057     assert(N == 3 && "Invalid number of operands!");
2058     assert(isRegShiftedReg() &&
2059            "addRegShiftedRegOperands() on non-RegShiftedReg!");
2060     Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg));
2061     Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg));
2062     Inst.addOperand(MCOperand::createImm(
2063       ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
2064   }
2065
2066   void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
2067     assert(N == 2 && "Invalid number of operands!");
2068     assert(isRegShiftedImm() &&
2069            "addRegShiftedImmOperands() on non-RegShiftedImm!");
2070     Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg));
2071     // Shift of #32 is encoded as 0 where permitted
2072     unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
2073     Inst.addOperand(MCOperand::createImm(
2074       ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
2075   }
2076
2077   void addShifterImmOperands(MCInst &Inst, unsigned N) const {
2078     assert(N == 1 && "Invalid number of operands!");
2079     Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) |
2080                                          ShifterImm.Imm));
2081   }
2082
2083   void addRegListOperands(MCInst &Inst, unsigned N) const {
2084     assert(N == 1 && "Invalid number of operands!");
2085     const SmallVectorImpl<unsigned> &RegList = getRegList();
2086     for (SmallVectorImpl<unsigned>::const_iterator
2087            I = RegList.begin(), E = RegList.end(); I != E; ++I)
2088       Inst.addOperand(MCOperand::createReg(*I));
2089   }
2090
2091   void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
2092     addRegListOperands(Inst, N);
2093   }
2094
2095   void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
2096     addRegListOperands(Inst, N);
2097   }
2098
2099   void addRotImmOperands(MCInst &Inst, unsigned N) const {
2100     assert(N == 1 && "Invalid number of operands!");
2101     // Encoded as val>>3. The printer handles display as 8, 16, 24.
2102     Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3));
2103   }
2104
2105   void addModImmOperands(MCInst &Inst, unsigned N) const {
2106     assert(N == 1 && "Invalid number of operands!");
2107
2108     // Support for fixups (MCFixup)
2109     if (isImm())
2110       return addImmOperands(Inst, N);
2111
2112     Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7)));
2113   }
2114
2115   void addModImmNotOperands(MCInst &Inst, unsigned N) const {
2116     assert(N == 1 && "Invalid number of operands!");
2117     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2118     uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
2119     Inst.addOperand(MCOperand::createImm(Enc));
2120   }
2121
2122   void addModImmNegOperands(MCInst &Inst, unsigned N) const {
2123     assert(N == 1 && "Invalid number of operands!");
2124     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2125     uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
2126     Inst.addOperand(MCOperand::createImm(Enc));
2127   }
2128
2129   void addThumbModImmNeg8_255Operands(MCInst &Inst, unsigned N) const {
2130     assert(N == 1 && "Invalid number of operands!");
2131     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2132     uint32_t Val = -CE->getValue();
2133     Inst.addOperand(MCOperand::createImm(Val));
2134   }
2135
2136   void addThumbModImmNeg1_7Operands(MCInst &Inst, unsigned N) const {
2137     assert(N == 1 && "Invalid number of operands!");
2138     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2139     uint32_t Val = -CE->getValue();
2140     Inst.addOperand(MCOperand::createImm(Val));
2141   }
2142
2143   void addBitfieldOperands(MCInst &Inst, unsigned N) const {
2144     assert(N == 1 && "Invalid number of operands!");
2145     // Munge the lsb/width into a bitfield mask.
2146     unsigned lsb = Bitfield.LSB;
2147     unsigned width = Bitfield.Width;
2148     // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
2149     uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
2150                       (32 - (lsb + width)));
2151     Inst.addOperand(MCOperand::createImm(Mask));
2152   }
2153
2154   void addImmOperands(MCInst &Inst, unsigned N) const {
2155     assert(N == 1 && "Invalid number of operands!");
2156     addExpr(Inst, getImm());
2157   }
2158
2159   void addFBits16Operands(MCInst &Inst, unsigned N) const {
2160     assert(N == 1 && "Invalid number of operands!");
2161     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2162     Inst.addOperand(MCOperand::createImm(16 - CE->getValue()));
2163   }
2164
2165   void addFBits32Operands(MCInst &Inst, unsigned N) const {
2166     assert(N == 1 && "Invalid number of operands!");
2167     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2168     Inst.addOperand(MCOperand::createImm(32 - CE->getValue()));
2169   }
2170
2171   void addFPImmOperands(MCInst &Inst, unsigned N) const {
2172     assert(N == 1 && "Invalid number of operands!");
2173     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2174     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
2175     Inst.addOperand(MCOperand::createImm(Val));
2176   }
2177
2178   void addImm8s4Operands(MCInst &Inst, unsigned N) const {
2179     assert(N == 1 && "Invalid number of operands!");
2180     // FIXME: We really want to scale the value here, but the LDRD/STRD
2181     // instruction don't encode operands that way yet.
2182     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2183     Inst.addOperand(MCOperand::createImm(CE->getValue()));
2184   }
2185
2186   void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
2187     assert(N == 1 && "Invalid number of operands!");
2188     // The immediate is scaled by four in the encoding and is stored
2189     // in the MCInst as such. Lop off the low two bits here.
2190     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2191     Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
2192   }
2193
2194   void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
2195     assert(N == 1 && "Invalid number of operands!");
2196     // The immediate is scaled by four in the encoding and is stored
2197     // in the MCInst as such. Lop off the low two bits here.
2198     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2199     Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4)));
2200   }
2201
2202   void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
2203     assert(N == 1 && "Invalid number of operands!");
2204     // The immediate is scaled by four in the encoding and is stored
2205     // in the MCInst as such. Lop off the low two bits here.
2206     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2207     Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
2208   }
2209
2210   void addImm1_16Operands(MCInst &Inst, unsigned N) const {
2211     assert(N == 1 && "Invalid number of operands!");
2212     // The constant encodes as the immediate-1, and we store in the instruction
2213     // the bits as encoded, so subtract off one here.
2214     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2215     Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
2216   }
2217
2218   void addImm1_32Operands(MCInst &Inst, unsigned N) const {
2219     assert(N == 1 && "Invalid number of operands!");
2220     // The constant encodes as the immediate-1, and we store in the instruction
2221     // the bits as encoded, so subtract off one here.
2222     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2223     Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
2224   }
2225
2226   void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
2227     assert(N == 1 && "Invalid number of operands!");
2228     // The constant encodes as the immediate, except for 32, which encodes as
2229     // zero.
2230     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2231     unsigned Imm = CE->getValue();
2232     Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm)));
2233   }
2234
2235   void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
2236     assert(N == 1 && "Invalid number of operands!");
2237     // An ASR value of 32 encodes as 0, so that's how we want to add it to
2238     // the instruction as well.
2239     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2240     int Val = CE->getValue();
2241     Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val));
2242   }
2243
2244   void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
2245     assert(N == 1 && "Invalid number of operands!");
2246     // The operand is actually a t2_so_imm, but we have its bitwise
2247     // negation in the assembly source, so twiddle it here.
2248     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2249     Inst.addOperand(MCOperand::createImm(~(uint32_t)CE->getValue()));
2250   }
2251
2252   void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
2253     assert(N == 1 && "Invalid number of operands!");
2254     // The operand is actually a t2_so_imm, but we have its
2255     // negation in the assembly source, so twiddle it here.
2256     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2257     Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue()));
2258   }
2259
2260   void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
2261     assert(N == 1 && "Invalid number of operands!");
2262     // The operand is actually an imm0_4095, but we have its
2263     // negation in the assembly source, so twiddle it here.
2264     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2265     Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue()));
2266   }
2267
2268   void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
2269     if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
2270       Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2));
2271       return;
2272     }
2273
2274     const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2275     assert(SR && "Unknown value type!");
2276     Inst.addOperand(MCOperand::createExpr(SR));
2277   }
2278
2279   void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
2280     assert(N == 1 && "Invalid number of operands!");
2281     if (isImm()) {
2282       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2283       if (CE) {
2284         Inst.addOperand(MCOperand::createImm(CE->getValue()));
2285         return;
2286       }
2287
2288       const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2289
2290       assert(SR && "Unknown value type!");
2291       Inst.addOperand(MCOperand::createExpr(SR));
2292       return;
2293     }
2294
2295     assert(isMem()  && "Unknown value type!");
2296     assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
2297     Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue()));
2298   }
2299
2300   void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
2301     assert(N == 1 && "Invalid number of operands!");
2302     Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt())));
2303   }
2304
2305   void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2306     assert(N == 1 && "Invalid number of operands!");
2307     Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt())));
2308   }
2309
2310   void addTraceSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2311     assert(N == 1 && "Invalid number of operands!");
2312     Inst.addOperand(MCOperand::createImm(unsigned(getTraceSyncBarrierOpt())));
2313   }
2314
2315   void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
2316     assert(N == 1 && "Invalid number of operands!");
2317     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2318   }
2319
2320   void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
2321     assert(N == 1 && "Invalid number of operands!");
2322     int32_t Imm = Memory.OffsetImm->getValue();
2323     Inst.addOperand(MCOperand::createImm(Imm));
2324   }
2325
2326   void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2327     assert(N == 1 && "Invalid number of operands!");
2328     assert(isImm() && "Not an immediate!");
2329
2330     // If we have an immediate that's not a constant, treat it as a label
2331     // reference needing a fixup.
2332     if (!isa<MCConstantExpr>(getImm())) {
2333       Inst.addOperand(MCOperand::createExpr(getImm()));
2334       return;
2335     }
2336
2337     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2338     int Val = CE->getValue();
2339     Inst.addOperand(MCOperand::createImm(Val));
2340   }
2341
2342   void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2343     assert(N == 2 && "Invalid number of operands!");
2344     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2345     Inst.addOperand(MCOperand::createImm(Memory.Alignment));
2346   }
2347
2348   void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2349     addAlignedMemoryOperands(Inst, N);
2350   }
2351
2352   void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2353     addAlignedMemoryOperands(Inst, N);
2354   }
2355
2356   void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2357     addAlignedMemoryOperands(Inst, N);
2358   }
2359
2360   void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2361     addAlignedMemoryOperands(Inst, N);
2362   }
2363
2364   void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2365     addAlignedMemoryOperands(Inst, N);
2366   }
2367
2368   void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2369     addAlignedMemoryOperands(Inst, N);
2370   }
2371
2372   void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2373     addAlignedMemoryOperands(Inst, N);
2374   }
2375
2376   void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2377     addAlignedMemoryOperands(Inst, N);
2378   }
2379
2380   void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2381     addAlignedMemoryOperands(Inst, N);
2382   }
2383
2384   void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2385     addAlignedMemoryOperands(Inst, N);
2386   }
2387
2388   void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2389     addAlignedMemoryOperands(Inst, N);
2390   }
2391
2392   void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2393     assert(N == 3 && "Invalid number of operands!");
2394     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2395     if (!Memory.OffsetRegNum) {
2396       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2397       // Special case for #-0
2398       if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2399       if (Val < 0) Val = -Val;
2400       Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2401     } else {
2402       // For register offset, we encode the shift type and negation flag
2403       // here.
2404       Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2405                               Memory.ShiftImm, Memory.ShiftType);
2406     }
2407     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2408     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2409     Inst.addOperand(MCOperand::createImm(Val));
2410   }
2411
2412   void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2413     assert(N == 2 && "Invalid number of operands!");
2414     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2415     assert(CE && "non-constant AM2OffsetImm operand!");
2416     int32_t Val = CE->getValue();
2417     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2418     // Special case for #-0
2419     if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2420     if (Val < 0) Val = -Val;
2421     Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2422     Inst.addOperand(MCOperand::createReg(0));
2423     Inst.addOperand(MCOperand::createImm(Val));
2424   }
2425
2426   void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2427     assert(N == 3 && "Invalid number of operands!");
2428     // If we have an immediate that's not a constant, treat it as a label
2429     // reference needing a fixup. If it is a constant, it's something else
2430     // and we reject it.
2431     if (isImm()) {
2432       Inst.addOperand(MCOperand::createExpr(getImm()));
2433       Inst.addOperand(MCOperand::createReg(0));
2434       Inst.addOperand(MCOperand::createImm(0));
2435       return;
2436     }
2437
2438     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2439     if (!Memory.OffsetRegNum) {
2440       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2441       // Special case for #-0
2442       if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2443       if (Val < 0) Val = -Val;
2444       Val = ARM_AM::getAM3Opc(AddSub, Val);
2445     } else {
2446       // For register offset, we encode the shift type and negation flag
2447       // here.
2448       Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2449     }
2450     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2451     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2452     Inst.addOperand(MCOperand::createImm(Val));
2453   }
2454
2455   void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2456     assert(N == 2 && "Invalid number of operands!");
2457     if (Kind == k_PostIndexRegister) {
2458       int32_t Val =
2459         ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2460       Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2461       Inst.addOperand(MCOperand::createImm(Val));
2462       return;
2463     }
2464
2465     // Constant offset.
2466     const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2467     int32_t Val = CE->getValue();
2468     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2469     // Special case for #-0
2470     if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2471     if (Val < 0) Val = -Val;
2472     Val = ARM_AM::getAM3Opc(AddSub, Val);
2473     Inst.addOperand(MCOperand::createReg(0));
2474     Inst.addOperand(MCOperand::createImm(Val));
2475   }
2476
2477   void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2478     assert(N == 2 && "Invalid number of operands!");
2479     // If we have an immediate that's not a constant, treat it as a label
2480     // reference needing a fixup. If it is a constant, it's something else
2481     // and we reject it.
2482     if (isImm()) {
2483       Inst.addOperand(MCOperand::createExpr(getImm()));
2484       Inst.addOperand(MCOperand::createImm(0));
2485       return;
2486     }
2487
2488     // The lower two bits are always zero and as such are not encoded.
2489     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2490     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2491     // Special case for #-0
2492     if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2493     if (Val < 0) Val = -Val;
2494     Val = ARM_AM::getAM5Opc(AddSub, Val);
2495     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2496     Inst.addOperand(MCOperand::createImm(Val));
2497   }
2498
2499   void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const {
2500     assert(N == 2 && "Invalid number of operands!");
2501     // If we have an immediate that's not a constant, treat it as a label
2502     // reference needing a fixup. If it is a constant, it's something else
2503     // and we reject it.
2504     if (isImm()) {
2505       Inst.addOperand(MCOperand::createExpr(getImm()));
2506       Inst.addOperand(MCOperand::createImm(0));
2507       return;
2508     }
2509
2510     // The lower bit is always zero and as such is not encoded.
2511     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 2 : 0;
2512     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2513     // Special case for #-0
2514     if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2515     if (Val < 0) Val = -Val;
2516     Val = ARM_AM::getAM5FP16Opc(AddSub, Val);
2517     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2518     Inst.addOperand(MCOperand::createImm(Val));
2519   }
2520
2521   void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2522     assert(N == 2 && "Invalid number of operands!");
2523     // If we have an immediate that's not a constant, treat it as a label
2524     // reference needing a fixup. If it is a constant, it's something else
2525     // and we reject it.
2526     if (isImm()) {
2527       Inst.addOperand(MCOperand::createExpr(getImm()));
2528       Inst.addOperand(MCOperand::createImm(0));
2529       return;
2530     }
2531
2532     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2533     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2534     Inst.addOperand(MCOperand::createImm(Val));
2535   }
2536
2537   void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2538     assert(N == 2 && "Invalid number of operands!");
2539     // The lower two bits are always zero and as such are not encoded.
2540     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2541     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2542     Inst.addOperand(MCOperand::createImm(Val));
2543   }
2544
2545   void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2546     assert(N == 2 && "Invalid number of operands!");
2547     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2548     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2549     Inst.addOperand(MCOperand::createImm(Val));
2550   }
2551
2552   void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2553     addMemImm8OffsetOperands(Inst, N);
2554   }
2555
2556   void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2557     addMemImm8OffsetOperands(Inst, N);
2558   }
2559
2560   void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2561     assert(N == 2 && "Invalid number of operands!");
2562     // If this is an immediate, it's a label reference.
2563     if (isImm()) {
2564       addExpr(Inst, getImm());
2565       Inst.addOperand(MCOperand::createImm(0));
2566       return;
2567     }
2568
2569     // Otherwise, it's a normal memory reg+offset.
2570     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2571     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2572     Inst.addOperand(MCOperand::createImm(Val));
2573   }
2574
2575   void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2576     assert(N == 2 && "Invalid number of operands!");
2577     // If this is an immediate, it's a label reference.
2578     if (isImm()) {
2579       addExpr(Inst, getImm());
2580       Inst.addOperand(MCOperand::createImm(0));
2581       return;
2582     }
2583
2584     // Otherwise, it's a normal memory reg+offset.
2585     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2586     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2587     Inst.addOperand(MCOperand::createImm(Val));
2588   }
2589
2590   void addConstPoolAsmImmOperands(MCInst &Inst, unsigned N) const {
2591     assert(N == 1 && "Invalid number of operands!");
2592     // This is container for the immediate that we will create the constant
2593     // pool from
2594     addExpr(Inst, getConstantPoolImm());
2595     return;
2596   }
2597
2598   void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2599     assert(N == 2 && "Invalid number of operands!");
2600     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2601     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2602   }
2603
2604   void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2605     assert(N == 2 && "Invalid number of operands!");
2606     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2607     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2608   }
2609
2610   void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2611     assert(N == 3 && "Invalid number of operands!");
2612     unsigned Val =
2613       ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2614                         Memory.ShiftImm, Memory.ShiftType);
2615     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2616     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2617     Inst.addOperand(MCOperand::createImm(Val));
2618   }
2619
2620   void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2621     assert(N == 3 && "Invalid number of operands!");
2622     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2623     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2624     Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
2625   }
2626
2627   void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2628     assert(N == 2 && "Invalid number of operands!");
2629     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2630     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2631   }
2632
2633   void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2634     assert(N == 2 && "Invalid number of operands!");
2635     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2636     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2637     Inst.addOperand(MCOperand::createImm(Val));
2638   }
2639
2640   void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2641     assert(N == 2 && "Invalid number of operands!");
2642     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2643     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2644     Inst.addOperand(MCOperand::createImm(Val));
2645   }
2646
2647   void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2648     assert(N == 2 && "Invalid number of operands!");
2649     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2650     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2651     Inst.addOperand(MCOperand::createImm(Val));
2652   }
2653
2654   void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2655     assert(N == 2 && "Invalid number of operands!");
2656     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2657     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2658     Inst.addOperand(MCOperand::createImm(Val));
2659   }
2660
2661   void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2662     assert(N == 1 && "Invalid number of operands!");
2663     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2664     assert(CE && "non-constant post-idx-imm8 operand!");
2665     int Imm = CE->getValue();
2666     bool isAdd = Imm >= 0;
2667     if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0;
2668     Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2669     Inst.addOperand(MCOperand::createImm(Imm));
2670   }
2671
2672   void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2673     assert(N == 1 && "Invalid number of operands!");
2674     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2675     assert(CE && "non-constant post-idx-imm8s4 operand!");
2676     int Imm = CE->getValue();
2677     bool isAdd = Imm >= 0;
2678     if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0;
2679     // Immediate is scaled by 4.
2680     Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2681     Inst.addOperand(MCOperand::createImm(Imm));
2682   }
2683
2684   void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2685     assert(N == 2 && "Invalid number of operands!");
2686     Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2687     Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd));
2688   }
2689
2690   void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2691     assert(N == 2 && "Invalid number of operands!");
2692     Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2693     // The sign, shift type, and shift amount are encoded in a single operand
2694     // using the AM2 encoding helpers.
2695     ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2696     unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2697                                      PostIdxReg.ShiftTy);
2698     Inst.addOperand(MCOperand::createImm(Imm));
2699   }
2700
2701   void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2702     assert(N == 1 && "Invalid number of operands!");
2703     Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask())));
2704   }
2705
2706   void addBankedRegOperands(MCInst &Inst, unsigned N) const {
2707     assert(N == 1 && "Invalid number of operands!");
2708     Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg())));
2709   }
2710
2711   void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2712     assert(N == 1 && "Invalid number of operands!");
2713     Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags())));
2714   }
2715
2716   void addVecListOperands(MCInst &Inst, unsigned N) const {
2717     assert(N == 1 && "Invalid number of operands!");
2718     Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
2719   }
2720
2721   void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2722     assert(N == 2 && "Invalid number of operands!");
2723     Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
2724     Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex));
2725   }
2726
2727   void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2728     assert(N == 1 && "Invalid number of operands!");
2729     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2730   }
2731
2732   void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2733     assert(N == 1 && "Invalid number of operands!");
2734     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2735   }
2736
2737   void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2738     assert(N == 1 && "Invalid number of operands!");
2739     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2740   }
2741
2742   void addVectorIndex64Operands(MCInst &Inst, unsigned N) const {
2743     assert(N == 1 && "Invalid number of operands!");
2744     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2745   }
2746
2747   void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2748     assert(N == 1 && "Invalid number of operands!");
2749     // The immediate encodes the type of constant as well as the value.
2750     // Mask in that this is an i8 splat.
2751     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2752     Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00));
2753   }
2754
2755   void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2756     assert(N == 1 && "Invalid number of operands!");
2757     // The immediate encodes the type of constant as well as the value.
2758     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2759     unsigned Value = CE->getValue();
2760     Value = ARM_AM::encodeNEONi16splat(Value);
2761     Inst.addOperand(MCOperand::createImm(Value));
2762   }
2763
2764   void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
2765     assert(N == 1 && "Invalid number of operands!");
2766     // The immediate encodes the type of constant as well as the value.
2767     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2768     unsigned Value = CE->getValue();
2769     Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
2770     Inst.addOperand(MCOperand::createImm(Value));
2771   }
2772
2773   void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2774     assert(N == 1 && "Invalid number of operands!");
2775     // The immediate encodes the type of constant as well as the value.
2776     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2777     unsigned Value = CE->getValue();
2778     Value = ARM_AM::encodeNEONi32splat(Value);
2779     Inst.addOperand(MCOperand::createImm(Value));
2780   }
2781
2782   void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
2783     assert(N == 1 && "Invalid number of operands!");
2784     // The immediate encodes the type of constant as well as the value.
2785     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2786     unsigned Value = CE->getValue();
2787     Value = ARM_AM::encodeNEONi32splat(~Value);
2788     Inst.addOperand(MCOperand::createImm(Value));
2789   }
2790
2791   void addNEONi8ReplicateOperands(MCInst &Inst, bool Inv) const {
2792     // The immediate encodes the type of constant as well as the value.
2793     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2794     assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2795             Inst.getOpcode() == ARM::VMOVv16i8) &&
2796           "All instructions that wants to replicate non-zero byte "
2797           "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2798     unsigned Value = CE->getValue();
2799     if (Inv)
2800       Value = ~Value;
2801     unsigned B = Value & 0xff;
2802     B |= 0xe00; // cmode = 0b1110
2803     Inst.addOperand(MCOperand::createImm(B));
2804   }
2805
2806   void addNEONinvi8ReplicateOperands(MCInst &Inst, unsigned N) const {
2807     assert(N == 1 && "Invalid number of operands!");
2808     addNEONi8ReplicateOperands(Inst, true);
2809   }
2810
2811   static unsigned encodeNeonVMOVImmediate(unsigned Value) {
2812     if (Value >= 256 && Value <= 0xffff)
2813       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2814     else if (Value > 0xffff && Value <= 0xffffff)
2815       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2816     else if (Value > 0xffffff)
2817       Value = (Value >> 24) | 0x600;
2818     return Value;
2819   }
2820
2821   void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2822     assert(N == 1 && "Invalid number of operands!");
2823     // The immediate encodes the type of constant as well as the value.
2824     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2825     unsigned Value = encodeNeonVMOVImmediate(CE->getValue());
2826     Inst.addOperand(MCOperand::createImm(Value));
2827   }
2828
2829   void addNEONvmovi8ReplicateOperands(MCInst &Inst, unsigned N) const {
2830     assert(N == 1 && "Invalid number of operands!");
2831     addNEONi8ReplicateOperands(Inst, false);
2832   }
2833
2834   void addNEONvmovi16ReplicateOperands(MCInst &Inst, unsigned N) const {
2835     assert(N == 1 && "Invalid number of operands!");
2836     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2837     assert((Inst.getOpcode() == ARM::VMOVv4i16 ||
2838             Inst.getOpcode() == ARM::VMOVv8i16 ||
2839             Inst.getOpcode() == ARM::VMVNv4i16 ||
2840             Inst.getOpcode() == ARM::VMVNv8i16) &&
2841           "All instructions that want to replicate non-zero half-word "
2842           "always must be replaced with V{MOV,MVN}v{4,8}i16.");
2843     uint64_t Value = CE->getValue();
2844     unsigned Elem = Value & 0xffff;
2845     if (Elem >= 256)
2846       Elem = (Elem >> 8) | 0x200;
2847     Inst.addOperand(MCOperand::createImm(Elem));
2848   }
2849
2850   void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2851     assert(N == 1 && "Invalid number of operands!");
2852     // The immediate encodes the type of constant as well as the value.
2853     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2854     unsigned Value = encodeNeonVMOVImmediate(~CE->getValue());
2855     Inst.addOperand(MCOperand::createImm(Value));
2856   }
2857
2858   void addNEONvmovi32ReplicateOperands(MCInst &Inst, unsigned N) const {
2859     assert(N == 1 && "Invalid number of operands!");
2860     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2861     assert((Inst.getOpcode() == ARM::VMOVv2i32 ||
2862             Inst.getOpcode() == ARM::VMOVv4i32 ||
2863             Inst.getOpcode() == ARM::VMVNv2i32 ||
2864             Inst.getOpcode() == ARM::VMVNv4i32) &&
2865           "All instructions that want to replicate non-zero word "
2866           "always must be replaced with V{MOV,MVN}v{2,4}i32.");
2867     uint64_t Value = CE->getValue();
2868     unsigned Elem = encodeNeonVMOVImmediate(Value & 0xffffffff);
2869     Inst.addOperand(MCOperand::createImm(Elem));
2870   }
2871
2872   void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2873     assert(N == 1 && "Invalid number of operands!");
2874     // The immediate encodes the type of constant as well as the value.
2875     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2876     uint64_t Value = CE->getValue();
2877     unsigned Imm = 0;
2878     for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2879       Imm |= (Value & 1) << i;
2880     }
2881     Inst.addOperand(MCOperand::createImm(Imm | 0x1e00));
2882   }
2883
2884   void addComplexRotationEvenOperands(MCInst &Inst, unsigned N) const {
2885     assert(N == 1 && "Invalid number of operands!");
2886     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2887     Inst.addOperand(MCOperand::createImm(CE->getValue() / 90));
2888   }
2889
2890   void addComplexRotationOddOperands(MCInst &Inst, unsigned N) const {
2891     assert(N == 1 && "Invalid number of operands!");
2892     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2893     Inst.addOperand(MCOperand::createImm((CE->getValue() - 90) / 180));
2894   }
2895
2896   void print(raw_ostream &OS) const override;
2897
2898   static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
2899     auto Op = make_unique<ARMOperand>(k_ITCondMask);
2900     Op->ITMask.Mask = Mask;
2901     Op->StartLoc = S;
2902     Op->EndLoc = S;
2903     return Op;
2904   }
2905
2906   static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
2907                                                     SMLoc S) {
2908     auto Op = make_unique<ARMOperand>(k_CondCode);
2909     Op->CC.Val = CC;
2910     Op->StartLoc = S;
2911     Op->EndLoc = S;
2912     return Op;
2913   }
2914
2915   static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
2916     auto Op = make_unique<ARMOperand>(k_CoprocNum);
2917     Op->Cop.Val = CopVal;
2918     Op->StartLoc = S;
2919     Op->EndLoc = S;
2920     return Op;
2921   }
2922
2923   static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
2924     auto Op = make_unique<ARMOperand>(k_CoprocReg);
2925     Op->Cop.Val = CopVal;
2926     Op->StartLoc = S;
2927     Op->EndLoc = S;
2928     return Op;
2929   }
2930
2931   static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
2932                                                         SMLoc E) {
2933     auto Op = make_unique<ARMOperand>(k_CoprocOption);
2934     Op->Cop.Val = Val;
2935     Op->StartLoc = S;
2936     Op->EndLoc = E;
2937     return Op;
2938   }
2939
2940   static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
2941     auto Op = make_unique<ARMOperand>(k_CCOut);
2942     Op->Reg.RegNum = RegNum;
2943     Op->StartLoc = S;
2944     Op->EndLoc = S;
2945     return Op;
2946   }
2947
2948   static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
2949     auto Op = make_unique<ARMOperand>(k_Token);
2950     Op->Tok.Data = Str.data();
2951     Op->Tok.Length = Str.size();
2952     Op->StartLoc = S;
2953     Op->EndLoc = S;
2954     return Op;
2955   }
2956
2957   static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
2958                                                SMLoc E) {
2959     auto Op = make_unique<ARMOperand>(k_Register);
2960     Op->Reg.RegNum = RegNum;
2961     Op->StartLoc = S;
2962     Op->EndLoc = E;
2963     return Op;
2964   }
2965
2966   static std::unique_ptr<ARMOperand>
2967   CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2968                         unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
2969                         SMLoc E) {
2970     auto Op = make_unique<ARMOperand>(k_ShiftedRegister);
2971     Op->RegShiftedReg.ShiftTy = ShTy;
2972     Op->RegShiftedReg.SrcReg = SrcReg;
2973     Op->RegShiftedReg.ShiftReg = ShiftReg;
2974     Op->RegShiftedReg.ShiftImm = ShiftImm;
2975     Op->StartLoc = S;
2976     Op->EndLoc = E;
2977     return Op;
2978   }
2979
2980   static std::unique_ptr<ARMOperand>
2981   CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2982                          unsigned ShiftImm, SMLoc S, SMLoc E) {
2983     auto Op = make_unique<ARMOperand>(k_ShiftedImmediate);
2984     Op->RegShiftedImm.ShiftTy = ShTy;
2985     Op->RegShiftedImm.SrcReg = SrcReg;
2986     Op->RegShiftedImm.ShiftImm = ShiftImm;
2987     Op->StartLoc = S;
2988     Op->EndLoc = E;
2989     return Op;
2990   }
2991
2992   static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
2993                                                       SMLoc S, SMLoc E) {
2994     auto Op = make_unique<ARMOperand>(k_ShifterImmediate);
2995     Op->ShifterImm.isASR = isASR;
2996     Op->ShifterImm.Imm = Imm;
2997     Op->StartLoc = S;
2998     Op->EndLoc = E;
2999     return Op;
3000   }
3001
3002   static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
3003                                                   SMLoc E) {
3004     auto Op = make_unique<ARMOperand>(k_RotateImmediate);
3005     Op->RotImm.Imm = Imm;
3006     Op->StartLoc = S;
3007     Op->EndLoc = E;
3008     return Op;
3009   }
3010
3011   static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot,
3012                                                   SMLoc S, SMLoc E) {
3013     auto Op = make_unique<ARMOperand>(k_ModifiedImmediate);
3014     Op->ModImm.Bits = Bits;
3015     Op->ModImm.Rot = Rot;
3016     Op->StartLoc = S;
3017     Op->EndLoc = E;
3018     return Op;
3019   }
3020
3021   static std::unique_ptr<ARMOperand>
3022   CreateConstantPoolImm(const MCExpr *Val, SMLoc S, SMLoc E) {
3023     auto Op = make_unique<ARMOperand>(k_ConstantPoolImmediate);
3024     Op->Imm.Val = Val;
3025     Op->StartLoc = S;
3026     Op->EndLoc = E;
3027     return Op;
3028   }
3029
3030   static std::unique_ptr<ARMOperand>
3031   CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
3032     auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor);
3033     Op->Bitfield.LSB = LSB;
3034     Op->Bitfield.Width = Width;
3035     Op->StartLoc = S;
3036     Op->EndLoc = E;
3037     return Op;
3038   }
3039
3040   static std::unique_ptr<ARMOperand>
3041   CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
3042                 SMLoc StartLoc, SMLoc EndLoc) {
3043     assert(Regs.size() > 0 && "RegList contains no registers?");
3044     KindTy Kind = k_RegisterList;
3045
3046     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
3047       Kind = k_DPRRegisterList;
3048     else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
3049              contains(Regs.front().second))
3050       Kind = k_SPRRegisterList;
3051
3052     // Sort based on the register encoding values.
3053     array_pod_sort(Regs.begin(), Regs.end());
3054
3055     auto Op = make_unique<ARMOperand>(Kind);
3056     for (SmallVectorImpl<std::pair<unsigned, unsigned>>::const_iterator
3057            I = Regs.begin(), E = Regs.end(); I != E; ++I)
3058       Op->Registers.push_back(I->second);
3059     Op->StartLoc = StartLoc;
3060     Op->EndLoc = EndLoc;
3061     return Op;
3062   }
3063
3064   static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
3065                                                       unsigned Count,
3066                                                       bool isDoubleSpaced,
3067                                                       SMLoc S, SMLoc E) {
3068     auto Op = make_unique<ARMOperand>(k_VectorList);
3069     Op->VectorList.RegNum = RegNum;
3070     Op->VectorList.Count = Count;
3071     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3072     Op->StartLoc = S;
3073     Op->EndLoc = E;
3074     return Op;
3075   }
3076
3077   static std::unique_ptr<ARMOperand>
3078   CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
3079                            SMLoc S, SMLoc E) {
3080     auto Op = make_unique<ARMOperand>(k_VectorListAllLanes);
3081     Op->VectorList.RegNum = RegNum;
3082     Op->VectorList.Count = Count;
3083     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3084     Op->StartLoc = S;
3085     Op->EndLoc = E;
3086     return Op;
3087   }
3088
3089   static std::unique_ptr<ARMOperand>
3090   CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
3091                           bool isDoubleSpaced, SMLoc S, SMLoc E) {
3092     auto Op = make_unique<ARMOperand>(k_VectorListIndexed);
3093     Op->VectorList.RegNum = RegNum;
3094     Op->VectorList.Count = Count;
3095     Op->VectorList.LaneIndex = Index;
3096     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3097     Op->StartLoc = S;
3098     Op->EndLoc = E;
3099     return Op;
3100   }
3101
3102   static std::unique_ptr<ARMOperand>
3103   CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
3104     auto Op = make_unique<ARMOperand>(k_VectorIndex);
3105     Op->VectorIndex.Val = Idx;
3106     Op->StartLoc = S;
3107     Op->EndLoc = E;
3108     return Op;
3109   }
3110
3111   static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
3112                                                SMLoc E) {
3113     auto Op = make_unique<ARMOperand>(k_Immediate);
3114     Op->Imm.Val = Val;
3115     Op->StartLoc = S;
3116     Op->EndLoc = E;
3117     return Op;
3118   }
3119
3120   static std::unique_ptr<ARMOperand>
3121   CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
3122             unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
3123             unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
3124             SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
3125     auto Op = make_unique<ARMOperand>(k_Memory);
3126     Op->Memory.BaseRegNum = BaseRegNum;
3127     Op->Memory.OffsetImm = OffsetImm;
3128     Op->Memory.OffsetRegNum = OffsetRegNum;
3129     Op->Memory.ShiftType = ShiftType;
3130     Op->Memory.ShiftImm = ShiftImm;
3131     Op->Memory.Alignment = Alignment;
3132     Op->Memory.isNegative = isNegative;
3133     Op->StartLoc = S;
3134     Op->EndLoc = E;
3135     Op->AlignmentLoc = AlignmentLoc;
3136     return Op;
3137   }
3138
3139   static std::unique_ptr<ARMOperand>
3140   CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
3141                    unsigned ShiftImm, SMLoc S, SMLoc E) {
3142     auto Op = make_unique<ARMOperand>(k_PostIndexRegister);
3143     Op->PostIdxReg.RegNum = RegNum;
3144     Op->PostIdxReg.isAdd = isAdd;
3145     Op->PostIdxReg.ShiftTy = ShiftTy;
3146     Op->PostIdxReg.ShiftImm = ShiftImm;
3147     Op->StartLoc = S;
3148     Op->EndLoc = E;
3149     return Op;
3150   }
3151
3152   static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
3153                                                          SMLoc S) {
3154     auto Op = make_unique<ARMOperand>(k_MemBarrierOpt);
3155     Op->MBOpt.Val = Opt;
3156     Op->StartLoc = S;
3157     Op->EndLoc = S;
3158     return Op;
3159   }
3160
3161   static std::unique_ptr<ARMOperand>
3162   CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
3163     auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt);
3164     Op->ISBOpt.Val = Opt;
3165     Op->StartLoc = S;
3166     Op->EndLoc = S;
3167     return Op;
3168   }
3169
3170   static std::unique_ptr<ARMOperand>
3171   CreateTraceSyncBarrierOpt(ARM_TSB::TraceSyncBOpt Opt, SMLoc S) {
3172     auto Op = make_unique<ARMOperand>(k_TraceSyncBarrierOpt);
3173     Op->TSBOpt.Val = Opt;
3174     Op->StartLoc = S;
3175     Op->EndLoc = S;
3176     return Op;
3177   }
3178
3179   static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
3180                                                       SMLoc S) {
3181     auto Op = make_unique<ARMOperand>(k_ProcIFlags);
3182     Op->IFlags.Val = IFlags;
3183     Op->StartLoc = S;
3184     Op->EndLoc = S;
3185     return Op;
3186   }
3187
3188   static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
3189     auto Op = make_unique<ARMOperand>(k_MSRMask);
3190     Op->MMask.Val = MMask;
3191     Op->StartLoc = S;
3192     Op->EndLoc = S;
3193     return Op;
3194   }
3195
3196   static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) {
3197     auto Op = make_unique<ARMOperand>(k_BankedReg);
3198     Op->BankedReg.Val = Reg;
3199     Op->StartLoc = S;
3200     Op->EndLoc = S;
3201     return Op;
3202   }
3203 };
3204
3205 } // end anonymous namespace.
3206
3207 void ARMOperand::print(raw_ostream &OS) const {
3208   auto RegName = [](unsigned Reg) {
3209     if (Reg)
3210       return ARMInstPrinter::getRegisterName(Reg);
3211     else
3212       return "noreg";
3213   };
3214
3215   switch (Kind) {
3216   case k_CondCode:
3217     OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
3218     break;
3219   case k_CCOut:
3220     OS << "<ccout " << RegName(getReg()) << ">";
3221     break;
3222   case k_ITCondMask: {
3223     static const char *const MaskStr[] = {
3224       "(invalid)", "(teee)", "(tee)", "(teet)",
3225       "(te)",      "(tete)", "(tet)", "(tett)",
3226       "(t)",       "(ttee)", "(tte)", "(ttet)",
3227       "(tt)",      "(ttte)", "(ttt)", "(tttt)"
3228     };
3229     assert((ITMask.Mask & 0xf) == ITMask.Mask);
3230     OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
3231     break;
3232   }
3233   case k_CoprocNum:
3234     OS << "<coprocessor number: " << getCoproc() << ">";
3235     break;
3236   case k_CoprocReg:
3237     OS << "<coprocessor register: " << getCoproc() << ">";
3238     break;
3239   case k_CoprocOption:
3240     OS << "<coprocessor option: " << CoprocOption.Val << ">";
3241     break;
3242   case k_MSRMask:
3243     OS << "<mask: " << getMSRMask() << ">";
3244     break;
3245   case k_BankedReg:
3246     OS << "<banked reg: " << getBankedReg() << ">";
3247     break;
3248   case k_Immediate:
3249     OS << *getImm();
3250     break;
3251   case k_MemBarrierOpt:
3252     OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
3253     break;
3254   case k_InstSyncBarrierOpt:
3255     OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
3256     break;
3257   case k_TraceSyncBarrierOpt:
3258     OS << "<ARM_TSB::" << TraceSyncBOptToString(getTraceSyncBarrierOpt()) << ">";
3259     break;
3260   case k_Memory:
3261     OS << "<memory";
3262     if (Memory.BaseRegNum)
3263       OS << " base:" << RegName(Memory.BaseRegNum);
3264     if (Memory.OffsetImm)
3265       OS << " offset-imm:" << *Memory.OffsetImm;
3266     if (Memory.OffsetRegNum)
3267       OS << " offset-reg:" << (Memory.isNegative ? "-" : "")
3268          << RegName(Memory.OffsetRegNum);
3269     if (Memory.ShiftType != ARM_AM::no_shift) {
3270       OS << " shift-type:" << ARM_AM::getShiftOpcStr(Memory.ShiftType);
3271       OS << " shift-imm:" << Memory.ShiftImm;
3272     }
3273     if (Memory.Alignment)
3274       OS << " alignment:" << Memory.Alignment;
3275     OS << ">";
3276     break;
3277   case k_PostIndexRegister:
3278     OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
3279        << RegName(PostIdxReg.RegNum);
3280     if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
3281       OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
3282          << PostIdxReg.ShiftImm;
3283     OS << ">";
3284     break;
3285   case k_ProcIFlags: {
3286     OS << "<ARM_PROC::";
3287     unsigned IFlags = getProcIFlags();
3288     for (int i=2; i >= 0; --i)
3289       if (IFlags & (1 << i))
3290         OS << ARM_PROC::IFlagsToString(1 << i);
3291     OS << ">";
3292     break;
3293   }
3294   case k_Register:
3295     OS << "<register " << RegName(getReg()) << ">";
3296     break;
3297   case k_ShifterImmediate:
3298     OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
3299        << " #" << ShifterImm.Imm << ">";
3300     break;
3301   case k_ShiftedRegister:
3302     OS << "<so_reg_reg " << RegName(RegShiftedReg.SrcReg) << " "
3303        << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) << " "
3304        << RegName(RegShiftedReg.ShiftReg) << ">";
3305     break;
3306   case k_ShiftedImmediate:
3307     OS << "<so_reg_imm " << RegName(RegShiftedImm.SrcReg) << " "
3308        << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) << " #"
3309        << RegShiftedImm.ShiftImm << ">";
3310     break;
3311   case k_RotateImmediate:
3312     OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
3313     break;
3314   case k_ModifiedImmediate:
3315     OS << "<mod_imm #" << ModImm.Bits << ", #"
3316        <<  ModImm.Rot << ")>";
3317     break;
3318   case k_ConstantPoolImmediate:
3319     OS << "<constant_pool_imm #" << *getConstantPoolImm();
3320     break;
3321   case k_BitfieldDescriptor:
3322     OS << "<bitfield " << "lsb: " << Bitfield.LSB
3323        << ", width: " << Bitfield.Width << ">";
3324     break;
3325   case k_RegisterList:
3326   case k_DPRRegisterList:
3327   case k_SPRRegisterList: {
3328     OS << "<register_list ";
3329
3330     const SmallVectorImpl<unsigned> &RegList = getRegList();
3331     for (SmallVectorImpl<unsigned>::const_iterator
3332            I = RegList.begin(), E = RegList.end(); I != E; ) {
3333       OS << RegName(*I);
3334       if (++I < E) OS << ", ";
3335     }
3336
3337     OS << ">";
3338     break;
3339   }
3340   case k_VectorList:
3341     OS << "<vector_list " << VectorList.Count << " * "
3342        << RegName(VectorList.RegNum) << ">";
3343     break;
3344   case k_VectorListAllLanes:
3345     OS << "<vector_list(all lanes) " << VectorList.Count << " * "
3346        << RegName(VectorList.RegNum) << ">";
3347     break;
3348   case k_VectorListIndexed:
3349     OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
3350        << VectorList.Count << " * " << RegName(VectorList.RegNum) << ">";
3351     break;
3352   case k_Token:
3353     OS << "'" << getToken() << "'";
3354     break;
3355   case k_VectorIndex:
3356     OS << "<vectorindex " << getVectorIndex() << ">";
3357     break;
3358   }
3359 }
3360
3361 /// @name Auto-generated Match Functions
3362 /// {
3363
3364 static unsigned MatchRegisterName(StringRef Name);
3365
3366 /// }
3367
3368 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
3369                                  SMLoc &StartLoc, SMLoc &EndLoc) {
3370   const AsmToken &Tok = getParser().getTok();
3371   StartLoc = Tok.getLoc();
3372   EndLoc = Tok.getEndLoc();
3373   RegNo = tryParseRegister();
3374
3375   return (RegNo == (unsigned)-1);
3376 }
3377
3378 /// Try to parse a register name.  The token must be an Identifier when called,
3379 /// and if it is a register name the token is eaten and the register number is
3380 /// returned.  Otherwise return -1.
3381 int ARMAsmParser::tryParseRegister() {
3382   MCAsmParser &Parser = getParser();
3383   const AsmToken &Tok = Parser.getTok();
3384   if (Tok.isNot(AsmToken::Identifier)) return -1;
3385
3386   std::string lowerCase = Tok.getString().lower();
3387   unsigned RegNum = MatchRegisterName(lowerCase);
3388   if (!RegNum) {
3389     RegNum = StringSwitch<unsigned>(lowerCase)
3390       .Case("r13", ARM::SP)
3391       .Case("r14", ARM::LR)
3392       .Case("r15", ARM::PC)
3393       .Case("ip", ARM::R12)
3394       // Additional register name aliases for 'gas' compatibility.
3395       .Case("a1", ARM::R0)
3396       .Case("a2", ARM::R1)
3397       .Case("a3", ARM::R2)
3398       .Case("a4", ARM::R3)
3399       .Case("v1", ARM::R4)
3400       .Case("v2", ARM::R5)
3401       .Case("v3", ARM::R6)
3402       .Case("v4", ARM::R7)
3403       .Case("v5", ARM::R8)
3404       .Case("v6", ARM::R9)
3405       .Case("v7", ARM::R10)
3406       .Case("v8", ARM::R11)
3407       .Case("sb", ARM::R9)
3408       .Case("sl", ARM::R10)
3409       .Case("fp", ARM::R11)
3410       .Default(0);
3411   }
3412   if (!RegNum) {
3413     // Check for aliases registered via .req. Canonicalize to lower case.
3414     // That's more consistent since register names are case insensitive, and
3415     // it's how the original entry was passed in from MC/MCParser/AsmParser.
3416     StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
3417     // If no match, return failure.
3418     if (Entry == RegisterReqs.end())
3419       return -1;
3420     Parser.Lex(); // Eat identifier token.
3421     return Entry->getValue();
3422   }
3423
3424   // Some FPUs only have 16 D registers, so D16-D31 are invalid
3425   if (hasD16() && RegNum >= ARM::D16 && RegNum <= ARM::D31)
3426     return -1;
3427
3428   Parser.Lex(); // Eat identifier token.
3429
3430   return RegNum;
3431 }
3432
3433 // Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
3434 // If a recoverable error occurs, return 1. If an irrecoverable error
3435 // occurs, return -1. An irrecoverable error is one where tokens have been
3436 // consumed in the process of trying to parse the shifter (i.e., when it is
3437 // indeed a shifter operand, but malformed).
3438 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
3439   MCAsmParser &Parser = getParser();
3440   SMLoc S = Parser.getTok().getLoc();
3441   const AsmToken &Tok = Parser.getTok();
3442   if (Tok.isNot(AsmToken::Identifier))
3443     return -1;
3444
3445   std::string lowerCase = Tok.getString().lower();
3446   ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
3447       .Case("asl", ARM_AM::lsl)
3448       .Case("lsl", ARM_AM::lsl)
3449       .Case("lsr", ARM_AM::lsr)
3450       .Case("asr", ARM_AM::asr)
3451       .Case("ror", ARM_AM::ror)
3452       .Case("rrx", ARM_AM::rrx)
3453       .Default(ARM_AM::no_shift);
3454
3455   if (ShiftTy == ARM_AM::no_shift)
3456     return 1;
3457
3458   Parser.Lex(); // Eat the operator.
3459
3460   // The source register for the shift has already been added to the
3461   // operand list, so we need to pop it off and combine it into the shifted
3462   // register operand instead.
3463   std::unique_ptr<ARMOperand> PrevOp(
3464       (ARMOperand *)Operands.pop_back_val().release());
3465   if (!PrevOp->isReg())
3466     return Error(PrevOp->getStartLoc(), "shift must be of a register");
3467   int SrcReg = PrevOp->getReg();
3468
3469   SMLoc EndLoc;
3470   int64_t Imm = 0;
3471   int ShiftReg = 0;
3472   if (ShiftTy == ARM_AM::rrx) {
3473     // RRX Doesn't have an explicit shift amount. The encoder expects
3474     // the shift register to be the same as the source register. Seems odd,
3475     // but OK.
3476     ShiftReg = SrcReg;
3477   } else {
3478     // Figure out if this is shifted by a constant or a register (for non-RRX).
3479     if (Parser.getTok().is(AsmToken::Hash) ||
3480         Parser.getTok().is(AsmToken::Dollar)) {
3481       Parser.Lex(); // Eat hash.
3482       SMLoc ImmLoc = Parser.getTok().getLoc();
3483       const MCExpr *ShiftExpr = nullptr;
3484       if (getParser().parseExpression(ShiftExpr, EndLoc)) {
3485         Error(ImmLoc, "invalid immediate shift value");
3486         return -1;
3487       }
3488       // The expression must be evaluatable as an immediate.
3489       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
3490       if (!CE) {
3491         Error(ImmLoc, "invalid immediate shift value");
3492         return -1;
3493       }
3494       // Range check the immediate.
3495       // lsl, ror: 0 <= imm <= 31
3496       // lsr, asr: 0 <= imm <= 32
3497       Imm = CE->getValue();
3498       if (Imm < 0 ||
3499           ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
3500           ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
3501         Error(ImmLoc, "immediate shift value out of range");
3502         return -1;
3503       }
3504       // shift by zero is a nop. Always send it through as lsl.
3505       // ('as' compatibility)
3506       if (Imm == 0)
3507         ShiftTy = ARM_AM::lsl;
3508     } else if (Parser.getTok().is(AsmToken::Identifier)) {
3509       SMLoc L = Parser.getTok().getLoc();
3510       EndLoc = Parser.getTok().getEndLoc();
3511       ShiftReg = tryParseRegister();
3512       if (ShiftReg == -1) {
3513         Error(L, "expected immediate or register in shift operand");
3514         return -1;
3515       }
3516     } else {
3517       Error(Parser.getTok().getLoc(),
3518             "expected immediate or register in shift operand");
3519       return -1;
3520     }
3521   }
3522
3523   if (ShiftReg && ShiftTy != ARM_AM::rrx)
3524     Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
3525                                                          ShiftReg, Imm,
3526                                                          S, EndLoc));
3527   else
3528     Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
3529                                                           S, EndLoc));
3530
3531   return 0;
3532 }
3533
3534 /// Try to parse a register name.  The token must be an Identifier when called.
3535 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
3536 /// if there is a "writeback". 'true' if it's not a register.
3537 ///
3538 /// TODO this is likely to change to allow different register types and or to
3539 /// parse for a specific register type.
3540 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
3541   MCAsmParser &Parser = getParser();
3542   SMLoc RegStartLoc = Parser.getTok().getLoc();
3543   SMLoc RegEndLoc = Parser.getTok().getEndLoc();
3544   int RegNo = tryParseRegister();
3545   if (RegNo == -1)
3546     return true;
3547
3548   Operands.push_back(ARMOperand::CreateReg(RegNo, RegStartLoc, RegEndLoc));
3549
3550   const AsmToken &ExclaimTok = Parser.getTok();
3551   if (ExclaimTok.is(AsmToken::Exclaim)) {
3552     Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
3553                                                ExclaimTok.getLoc()));
3554     Parser.Lex(); // Eat exclaim token
3555     return false;
3556   }
3557
3558   // Also check for an index operand. This is only legal for vector registers,
3559   // but that'll get caught OK in operand matching, so we don't need to
3560   // explicitly filter everything else out here.
3561   if (Parser.getTok().is(AsmToken::LBrac)) {
3562     SMLoc SIdx = Parser.getTok().getLoc();
3563     Parser.Lex(); // Eat left bracket token.
3564
3565     const MCExpr *ImmVal;
3566     if (getParser().parseExpression(ImmVal))
3567       return true;
3568     const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
3569     if (!MCE)
3570       return TokError("immediate value expected for vector index");
3571
3572     if (Parser.getTok().isNot(AsmToken::RBrac))
3573       return Error(Parser.getTok().getLoc(), "']' expected");
3574
3575     SMLoc E = Parser.getTok().getEndLoc();
3576     Parser.Lex(); // Eat right bracket token.
3577
3578     Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
3579                                                      SIdx, E,
3580                                                      getContext()));
3581   }
3582
3583   return false;
3584 }
3585
3586 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
3587 /// instruction with a symbolic operand name.
3588 /// We accept "crN" syntax for GAS compatibility.
3589 /// <operand-name> ::= <prefix><number>
3590 /// If CoprocOp is 'c', then:
3591 ///   <prefix> ::= c | cr
3592 /// If CoprocOp is 'p', then :
3593 ///   <prefix> ::= p
3594 /// <number> ::= integer in range [0, 15]
3595 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
3596   // Use the same layout as the tablegen'erated register name matcher. Ugly,
3597   // but efficient.
3598   if (Name.size() < 2 || Name[0] != CoprocOp)
3599     return -1;
3600   Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
3601
3602   switch (Name.size()) {
3603   default: return -1;
3604   case 1:
3605     switch (Name[0]) {
3606     default:  return -1;
3607     case '0': return 0;
3608     case '1': return 1;
3609     case '2': return 2;
3610     case '3': return 3;
3611     case '4': return 4;
3612     case '5': return 5;
3613     case '6': return 6;
3614     case '7': return 7;
3615     case '8': return 8;
3616     case '9': return 9;
3617     }
3618   case 2:
3619     if (Name[0] != '1')
3620       return -1;
3621     switch (Name[1]) {
3622     default:  return -1;
3623     // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
3624     // However, old cores (v5/v6) did use them in that way.
3625     case '0': return 10;
3626     case '1': return 11;
3627     case '2': return 12;
3628     case '3': return 13;
3629     case '4': return 14;
3630     case '5': return 15;
3631     }
3632   }
3633 }
3634
3635 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3636 OperandMatchResultTy
3637 ARMAsmParser::parseITCondCode(OperandVector &Operands) {
3638   MCAsmParser &Parser = getParser();
3639   SMLoc S = Parser.getTok().getLoc();
3640   const AsmToken &Tok = Parser.getTok();
3641   if (!Tok.is(AsmToken::Identifier))
3642     return MatchOperand_NoMatch;
3643   unsigned CC = ARMCondCodeFromString(Tok.getString());
3644   if (CC == ~0U)
3645     return MatchOperand_NoMatch;
3646   Parser.Lex(); // Eat the token.
3647
3648   Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3649
3650   return MatchOperand_Success;
3651 }
3652
3653 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3654 /// token must be an Identifier when called, and if it is a coprocessor
3655 /// number, the token is eaten and the operand is added to the operand list.
3656 OperandMatchResultTy
3657 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
3658   MCAsmParser &Parser = getParser();
3659   SMLoc S = Parser.getTok().getLoc();
3660   const AsmToken &Tok = Parser.getTok();
3661   if (Tok.isNot(AsmToken::Identifier))
3662     return MatchOperand_NoMatch;
3663
3664   int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3665   if (Num == -1)
3666     return MatchOperand_NoMatch;
3667   // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions
3668   if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11))
3669     return MatchOperand_NoMatch;
3670
3671   Parser.Lex(); // Eat identifier token.
3672   Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3673   return MatchOperand_Success;
3674 }
3675
3676 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3677 /// token must be an Identifier when called, and if it is a coprocessor
3678 /// number, the token is eaten and the operand is added to the operand list.
3679 OperandMatchResultTy
3680 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
3681   MCAsmParser &Parser = getParser();
3682   SMLoc S = Parser.getTok().getLoc();
3683   const AsmToken &Tok = Parser.getTok();
3684   if (Tok.isNot(AsmToken::Identifier))
3685     return MatchOperand_NoMatch;
3686
3687   int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3688   if (Reg == -1)
3689     return MatchOperand_NoMatch;
3690
3691   Parser.Lex(); // Eat identifier token.
3692   Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3693   return MatchOperand_Success;
3694 }
3695
3696 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3697 /// coproc_option : '{' imm0_255 '}'
3698 OperandMatchResultTy
3699 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
3700   MCAsmParser &Parser = getParser();
3701   SMLoc S = Parser.getTok().getLoc();
3702
3703   // If this isn't a '{', this isn't a coprocessor immediate operand.
3704   if (Parser.getTok().isNot(AsmToken::LCurly))
3705     return MatchOperand_NoMatch;
3706   Parser.Lex(); // Eat the '{'
3707
3708   const MCExpr *Expr;
3709   SMLoc Loc = Parser.getTok().getLoc();
3710   if (getParser().parseExpression(Expr)) {
3711     Error(Loc, "illegal expression");
3712     return MatchOperand_ParseFail;
3713   }
3714   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3715   if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3716     Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3717     return MatchOperand_ParseFail;
3718   }
3719   int Val = CE->getValue();
3720
3721   // Check for and consume the closing '}'
3722   if (Parser.getTok().isNot(AsmToken::RCurly))
3723     return MatchOperand_ParseFail;
3724   SMLoc E = Parser.getTok().getEndLoc();
3725   Parser.Lex(); // Eat the '}'
3726
3727   Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3728   return MatchOperand_Success;
3729 }
3730
3731 // For register list parsing, we need to map from raw GPR register numbering
3732 // to the enumeration values. The enumeration values aren't sorted by
3733 // register number due to our using "sp", "lr" and "pc" as canonical names.
3734 static unsigned getNextRegister(unsigned Reg) {
3735   // If this is a GPR, we need to do it manually, otherwise we can rely
3736   // on the sort ordering of the enumeration since the other reg-classes
3737   // are sane.
3738   if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3739     return Reg + 1;
3740   switch(Reg) {
3741   default: llvm_unreachable("Invalid GPR number!");
3742   case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
3743   case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
3744   case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
3745   case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
3746   case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
3747   case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3748   case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
3749   case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
3750   }
3751 }
3752
3753 /// Parse a register list.
3754 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) {
3755   MCAsmParser &Parser = getParser();
3756   if (Parser.getTok().isNot(AsmToken::LCurly))
3757     return TokError("Token is not a Left Curly Brace");
3758   SMLoc S = Parser.getTok().getLoc();
3759   Parser.Lex(); // Eat '{' token.
3760   SMLoc RegLoc = Parser.getTok().getLoc();
3761
3762   // Check the first register in the list to see what register class
3763   // this is a list of.
3764   int Reg = tryParseRegister();
3765   if (Reg == -1)
3766     return Error(RegLoc, "register expected");
3767
3768   // The reglist instructions have at most 16 registers, so reserve
3769   // space for that many.
3770   int EReg = 0;
3771   SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3772
3773   // Allow Q regs and just interpret them as the two D sub-registers.
3774   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3775     Reg = getDRegFromQReg(Reg);
3776     EReg = MRI->getEncodingValue(Reg);
3777     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3778     ++Reg;
3779   }
3780   const MCRegisterClass *RC;
3781   if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3782     RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3783   else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3784     RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3785   else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3786     RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3787   else
3788     return Error(RegLoc, "invalid register in register list");
3789
3790   // Store the register.
3791   EReg = MRI->getEncodingValue(Reg);
3792   Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3793
3794   // This starts immediately after the first register token in the list,
3795   // so we can see either a comma or a minus (range separator) as a legal
3796   // next token.
3797   while (Parser.getTok().is(AsmToken::Comma) ||
3798          Parser.getTok().is(AsmToken::Minus)) {
3799     if (Parser.getTok().is(AsmToken::Minus)) {
3800       Parser.Lex(); // Eat the minus.
3801       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3802       int EndReg = tryParseRegister();
3803       if (EndReg == -1)
3804         return Error(AfterMinusLoc, "register expected");
3805       // Allow Q regs and just interpret them as the two D sub-registers.
3806       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3807         EndReg = getDRegFromQReg(EndReg) + 1;
3808       // If the register is the same as the start reg, there's nothing
3809       // more to do.
3810       if (Reg == EndReg)
3811         continue;
3812       // The register must be in the same register class as the first.
3813       if (!RC->contains(EndReg))
3814         return Error(AfterMinusLoc, "invalid register in register list");
3815       // Ranges must go from low to high.
3816       if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3817         return Error(AfterMinusLoc, "bad range in register list");
3818
3819       // Add all the registers in the range to the register list.
3820       while (Reg != EndReg) {
3821         Reg = getNextRegister(Reg);
3822         EReg = MRI->getEncodingValue(Reg);
3823         Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3824       }
3825       continue;
3826     }
3827     Parser.Lex(); // Eat the comma.
3828     RegLoc = Parser.getTok().getLoc();
3829     int OldReg = Reg;
3830     const AsmToken RegTok = Parser.getTok();
3831     Reg = tryParseRegister();
3832     if (Reg == -1)
3833       return Error(RegLoc, "register expected");
3834     // Allow Q regs and just interpret them as the two D sub-registers.
3835     bool isQReg = false;
3836     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3837       Reg = getDRegFromQReg(Reg);
3838       isQReg = true;
3839     }
3840     // The register must be in the same register class as the first.
3841     if (!RC->contains(Reg))
3842       return Error(RegLoc, "invalid register in register list");
3843     // List must be monotonically increasing.
3844     if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3845       if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3846         Warning(RegLoc, "register list not in ascending order");
3847       else
3848         return Error(RegLoc, "register list not in ascending order");
3849     }
3850     if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3851       Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3852               ") in register list");
3853       continue;
3854     }
3855     // VFP register lists must also be contiguous.
3856     if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3857         Reg != OldReg + 1)
3858       return Error(RegLoc, "non-contiguous register range");
3859     EReg = MRI->getEncodingValue(Reg);
3860     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3861     if (isQReg) {
3862       EReg = MRI->getEncodingValue(++Reg);
3863       Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3864     }
3865   }
3866
3867   if (Parser.getTok().isNot(AsmToken::RCurly))
3868     return Error(Parser.getTok().getLoc(), "'}' expected");
3869   SMLoc E = Parser.getTok().getEndLoc();
3870   Parser.Lex(); // Eat '}' token.
3871
3872   // Push the register list operand.
3873   Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3874
3875   // The ARM system instruction variants for LDM/STM have a '^' token here.
3876   if (Parser.getTok().is(AsmToken::Caret)) {
3877     Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3878     Parser.Lex(); // Eat '^' token.
3879   }
3880
3881   return false;
3882 }
3883
3884 // Helper function to parse the lane index for vector lists.
3885 OperandMatchResultTy ARMAsmParser::
3886 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3887   MCAsmParser &Parser = getParser();
3888   Index = 0; // Always return a defined index value.
3889   if (Parser.getTok().is(AsmToken::LBrac)) {
3890     Parser.Lex(); // Eat the '['.
3891     if (Parser.getTok().is(AsmToken::RBrac)) {
3892       // "Dn[]" is the 'all lanes' syntax.
3893       LaneKind = AllLanes;
3894       EndLoc = Parser.getTok().getEndLoc();
3895       Parser.Lex(); // Eat the ']'.
3896       return MatchOperand_Success;
3897     }
3898
3899     // There's an optional '#' token here. Normally there wouldn't be, but
3900     // inline assemble puts one in, and it's friendly to accept that.
3901     if (Parser.getTok().is(AsmToken::Hash))
3902       Parser.Lex(); // Eat '#' or '$'.
3903
3904     const MCExpr *LaneIndex;
3905     SMLoc Loc = Parser.getTok().getLoc();
3906     if (getParser().parseExpression(LaneIndex)) {
3907       Error(Loc, "illegal expression");
3908       return MatchOperand_ParseFail;
3909     }
3910     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3911     if (!CE) {
3912       Error(Loc, "lane index must be empty or an integer");
3913       return MatchOperand_ParseFail;
3914     }
3915     if (Parser.getTok().isNot(AsmToken::RBrac)) {
3916       Error(Parser.getTok().getLoc(), "']' expected");
3917       return MatchOperand_ParseFail;
3918     }
3919     EndLoc = Parser.getTok().getEndLoc();
3920     Parser.Lex(); // Eat the ']'.
3921     int64_t Val = CE->getValue();
3922
3923     // FIXME: Make this range check context sensitive for .8, .16, .32.
3924     if (Val < 0 || Val > 7) {
3925       Error(Parser.getTok().getLoc(), "lane index out of range");
3926       return MatchOperand_ParseFail;
3927     }
3928     Index = Val;
3929     LaneKind = IndexedLane;
3930     return MatchOperand_Success;
3931   }
3932   LaneKind = NoLanes;
3933   return MatchOperand_Success;
3934 }
3935
3936 // parse a vector register list
3937 OperandMatchResultTy
3938 ARMAsmParser::parseVectorList(OperandVector &Operands) {
3939   MCAsmParser &Parser = getParser();
3940   VectorLaneTy LaneKind;
3941   unsigned LaneIndex;
3942   SMLoc S = Parser.getTok().getLoc();
3943   // As an extension (to match gas), support a plain D register or Q register
3944   // (without encosing curly braces) as a single or double entry list,
3945   // respectively.
3946   if (Parser.getTok().is(AsmToken::Identifier)) {
3947     SMLoc E = Parser.getTok().getEndLoc();
3948     int Reg = tryParseRegister();
3949     if (Reg == -1)
3950       return MatchOperand_NoMatch;
3951     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3952       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3953       if (Res != MatchOperand_Success)
3954         return Res;
3955       switch (LaneKind) {
3956       case NoLanes:
3957         Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3958         break;
3959       case AllLanes:
3960         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3961                                                                 S, E));
3962         break;
3963       case IndexedLane:
3964         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3965                                                                LaneIndex,
3966                                                                false, S, E));
3967         break;
3968       }
3969       return MatchOperand_Success;
3970     }
3971     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3972       Reg = getDRegFromQReg(Reg);
3973       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3974       if (Res != MatchOperand_Success)
3975         return Res;
3976       switch (LaneKind) {
3977       case NoLanes:
3978         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3979                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3980         Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3981         break;
3982       case AllLanes:
3983         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3984                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3985         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3986                                                                 S, E));
3987         break;
3988       case IndexedLane:
3989         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3990                                                                LaneIndex,
3991                                                                false, S, E));
3992         break;
3993       }
3994       return MatchOperand_Success;
3995     }
3996     Error(S, "vector register expected");
3997     return MatchOperand_ParseFail;
3998   }
3999
4000   if (Parser.getTok().isNot(AsmToken::LCurly))
4001     return MatchOperand_NoMatch;
4002
4003   Parser.Lex(); // Eat '{' token.
4004   SMLoc RegLoc = Parser.getTok().getLoc();
4005
4006   int Reg = tryParseRegister();
4007   if (Reg == -1) {
4008     Error(RegLoc, "register expected");
4009     return MatchOperand_ParseFail;
4010   }
4011   unsigned Count = 1;
4012   int Spacing = 0;
4013   unsigned FirstReg = Reg;
4014   // The list is of D registers, but we also allow Q regs and just interpret
4015   // them as the two D sub-registers.
4016   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4017     FirstReg = Reg = getDRegFromQReg(Reg);
4018     Spacing = 1; // double-spacing requires explicit D registers, otherwise
4019                  // it's ambiguous with four-register single spaced.
4020     ++Reg;
4021     ++Count;
4022   }
4023
4024   SMLoc E;
4025   if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
4026     return MatchOperand_ParseFail;
4027
4028   while (Parser.getTok().is(AsmToken::Comma) ||
4029          Parser.getTok().is(AsmToken::Minus)) {
4030     if (Parser.getTok().is(AsmToken::Minus)) {
4031       if (!Spacing)
4032         Spacing = 1; // Register range implies a single spaced list.
4033       else if (Spacing == 2) {
4034         Error(Parser.getTok().getLoc(),
4035               "sequential registers in double spaced list");
4036         return MatchOperand_ParseFail;
4037       }
4038       Parser.Lex(); // Eat the minus.
4039       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
4040       int EndReg = tryParseRegister();
4041       if (EndReg == -1) {
4042         Error(AfterMinusLoc, "register expected");
4043         return MatchOperand_ParseFail;
4044       }
4045       // Allow Q regs and just interpret them as the two D sub-registers.
4046       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
4047         EndReg = getDRegFromQReg(EndReg) + 1;
4048       // If the register is the same as the start reg, there's nothing
4049       // more to do.
4050       if (Reg == EndReg)
4051         continue;
4052       // The register must be in the same register class as the first.
4053       if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
4054         Error(AfterMinusLoc, "invalid register in register list");
4055         return MatchOperand_ParseFail;
4056       }
4057       // Ranges must go from low to high.
4058       if (Reg > EndReg) {
4059         Error(AfterMinusLoc, "bad range in register list");
4060         return MatchOperand_ParseFail;
4061       }
4062       // Parse the lane specifier if present.
4063       VectorLaneTy NextLaneKind;
4064       unsigned NextLaneIndex;
4065       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
4066           MatchOperand_Success)
4067         return MatchOperand_ParseFail;
4068       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4069         Error(AfterMinusLoc, "mismatched lane index in register list");
4070         return MatchOperand_ParseFail;
4071       }
4072
4073       // Add all the registers in the range to the register list.
4074       Count += EndReg - Reg;
4075       Reg = EndReg;
4076       continue;
4077     }
4078     Parser.Lex(); // Eat the comma.
4079     RegLoc = Parser.getTok().getLoc();
4080     int OldReg = Reg;
4081     Reg = tryParseRegister();
4082     if (Reg == -1) {
4083       Error(RegLoc, "register expected");
4084       return MatchOperand_ParseFail;
4085     }
4086     // vector register lists must be contiguous.
4087     // It's OK to use the enumeration values directly here rather, as the
4088     // VFP register classes have the enum sorted properly.
4089     //
4090     // The list is of D registers, but we also allow Q regs and just interpret
4091     // them as the two D sub-registers.
4092     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4093       if (!Spacing)
4094         Spacing = 1; // Register range implies a single spaced list.
4095       else if (Spacing == 2) {
4096         Error(RegLoc,
4097               "invalid register in double-spaced list (must be 'D' register')");
4098         return MatchOperand_ParseFail;
4099       }
4100       Reg = getDRegFromQReg(Reg);
4101       if (Reg != OldReg + 1) {
4102         Error(RegLoc, "non-contiguous register range");
4103         return MatchOperand_ParseFail;
4104       }
4105       ++Reg;
4106       Count += 2;
4107       // Parse the lane specifier if present.
4108       VectorLaneTy NextLaneKind;
4109       unsigned NextLaneIndex;
4110       SMLoc LaneLoc = Parser.getTok().getLoc();
4111       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
4112           MatchOperand_Success)
4113         return MatchOperand_ParseFail;
4114       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4115         Error(LaneLoc, "mismatched lane index in register list");
4116         return MatchOperand_ParseFail;
4117       }
4118       continue;
4119     }
4120     // Normal D register.
4121     // Figure out the register spacing (single or double) of the list if
4122     // we don't know it already.
4123     if (!Spacing)
4124       Spacing = 1 + (Reg == OldReg + 2);
4125
4126     // Just check that it's contiguous and keep going.
4127     if (Reg != OldReg + Spacing) {
4128       Error(RegLoc, "non-contiguous register range");
4129       return MatchOperand_ParseFail;
4130     }
4131     ++Count;
4132     // Parse the lane specifier if present.
4133     VectorLaneTy NextLaneKind;
4134     unsigned NextLaneIndex;
4135     SMLoc EndLoc = Parser.getTok().getLoc();
4136     if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
4137       return MatchOperand_ParseFail;
4138     if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4139       Error(EndLoc, "mismatched lane index in register list");
4140       return MatchOperand_ParseFail;
4141     }
4142   }
4143
4144   if (Parser.getTok().isNot(AsmToken::RCurly)) {
4145     Error(Parser.getTok().getLoc(), "'}' expected");
4146     return MatchOperand_ParseFail;
4147   }
4148   E = Parser.getTok().getEndLoc();
4149   Parser.Lex(); // Eat '}' token.
4150
4151   switch (LaneKind) {
4152   case NoLanes:
4153     // Two-register operands have been converted to the
4154     // composite register classes.
4155     if (Count == 2) {
4156       const MCRegisterClass *RC = (Spacing == 1) ?
4157         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
4158         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
4159       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
4160     }
4161     Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
4162                                                     (Spacing == 2), S, E));
4163     break;
4164   case AllLanes:
4165     // Two-register operands have been converted to the
4166     // composite register classes.
4167     if (Count == 2) {
4168       const MCRegisterClass *RC = (Spacing == 1) ?
4169         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
4170         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
4171       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
4172     }
4173     Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
4174                                                             (Spacing == 2),
4175                                                             S, E));
4176     break;
4177   case IndexedLane:
4178     Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
4179                                                            LaneIndex,
4180                                                            (Spacing == 2),
4181                                                            S, E));
4182     break;
4183   }
4184   return MatchOperand_Success;
4185 }
4186
4187 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
4188 OperandMatchResultTy
4189 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
4190   MCAsmParser &Parser = getParser();
4191   SMLoc S = Parser.getTok().getLoc();
4192   const AsmToken &Tok = Parser.getTok();
4193   unsigned Opt;
4194
4195   if (Tok.is(AsmToken::Identifier)) {
4196     StringRef OptStr = Tok.getString();
4197
4198     Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
4199       .Case("sy",    ARM_MB::SY)
4200       .Case("st",    ARM_MB::ST)
4201       .Case("ld",    ARM_MB::LD)
4202       .Case("sh",    ARM_MB::ISH)
4203       .Case("ish",   ARM_MB::ISH)
4204       .Case("shst",  ARM_MB::ISHST)
4205       .Case("ishst", ARM_MB::ISHST)
4206       .Case("ishld", ARM_MB::ISHLD)
4207       .Case("nsh",   ARM_MB::NSH)
4208       .Case("un",    ARM_MB::NSH)
4209       .Case("nshst", ARM_MB::NSHST)
4210       .Case("nshld", ARM_MB::NSHLD)
4211       .Case("unst",  ARM_MB::NSHST)
4212       .Case("osh",   ARM_MB::OSH)
4213       .Case("oshst", ARM_MB::OSHST)
4214       .Case("oshld", ARM_MB::OSHLD)
4215       .Default(~0U);
4216
4217     // ishld, oshld, nshld and ld are only available from ARMv8.
4218     if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
4219                         Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
4220       Opt = ~0U;
4221
4222     if (Opt == ~0U)
4223       return MatchOperand_NoMatch;
4224
4225     Parser.Lex(); // Eat identifier token.
4226   } else if (Tok.is(AsmToken::Hash) ||
4227              Tok.is(AsmToken::Dollar) ||
4228              Tok.is(AsmToken::Integer)) {
4229     if (Parser.getTok().isNot(AsmToken::Integer))
4230       Parser.Lex(); // Eat '#' or '$'.
4231     SMLoc Loc = Parser.getTok().getLoc();
4232
4233     const MCExpr *MemBarrierID;
4234     if (getParser().parseExpression(MemBarrierID)) {
4235       Error(Loc, "illegal expression");
4236       return MatchOperand_ParseFail;
4237     }
4238
4239     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
4240     if (!CE) {
4241       Error(Loc, "constant expression expected");
4242       return MatchOperand_ParseFail;
4243     }
4244
4245     int Val = CE->getValue();
4246     if (Val & ~0xf) {
4247       Error(Loc, "immediate value out of range");
4248       return MatchOperand_ParseFail;
4249     }
4250
4251     Opt = ARM_MB::RESERVED_0 + Val;
4252   } else
4253     return MatchOperand_ParseFail;
4254
4255   Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
4256   return MatchOperand_Success;
4257 }
4258
4259 OperandMatchResultTy
4260 ARMAsmParser::parseTraceSyncBarrierOptOperand(OperandVector &Operands) {
4261   MCAsmParser &Parser = getParser();
4262   SMLoc S = Parser.getTok().getLoc();
4263   const AsmToken &Tok = Parser.getTok();
4264
4265   if (Tok.isNot(AsmToken::Identifier))
4266      return MatchOperand_NoMatch;
4267
4268   if (!Tok.getString().equals_lower("csync"))
4269     return MatchOperand_NoMatch;
4270
4271   Parser.Lex(); // Eat identifier token.
4272
4273   Operands.push_back(ARMOperand::CreateTraceSyncBarrierOpt(ARM_TSB::CSYNC, S));
4274   return MatchOperand_Success;
4275 }
4276
4277 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
4278 OperandMatchResultTy
4279 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
4280   MCAsmParser &Parser = getParser();
4281   SMLoc S = Parser.getTok().getLoc();
4282   const AsmToken &Tok = Parser.getTok();
4283   unsigned Opt;
4284
4285   if (Tok.is(AsmToken::Identifier)) {
4286     StringRef OptStr = Tok.getString();
4287
4288     if (OptStr.equals_lower("sy"))
4289       Opt = ARM_ISB::SY;
4290     else
4291       return MatchOperand_NoMatch;
4292
4293     Parser.Lex(); // Eat identifier token.
4294   } else if (Tok.is(AsmToken::Hash) ||
4295              Tok.is(AsmToken::Dollar) ||
4296              Tok.is(AsmToken::Integer)) {
4297     if (Parser.getTok().isNot(AsmToken::Integer))
4298       Parser.Lex(); // Eat '#' or '$'.
4299     SMLoc Loc = Parser.getTok().getLoc();
4300
4301     const MCExpr *ISBarrierID;
4302     if (getParser().parseExpression(ISBarrierID)) {
4303       Error(Loc, "illegal expression");
4304       return MatchOperand_ParseFail;
4305     }
4306
4307     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
4308     if (!CE) {
4309       Error(Loc, "constant expression expected");
4310       return MatchOperand_ParseFail;
4311     }
4312
4313     int Val = CE->getValue();
4314     if (Val & ~0xf) {
4315       Error(Loc, "immediate value out of range");
4316       return MatchOperand_ParseFail;
4317     }
4318
4319     Opt = ARM_ISB::RESERVED_0 + Val;
4320   } else
4321     return MatchOperand_ParseFail;
4322
4323   Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
4324           (ARM_ISB::InstSyncBOpt)Opt, S));
4325   return MatchOperand_Success;
4326 }
4327
4328
4329 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
4330 OperandMatchResultTy
4331 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
4332   MCAsmParser &Parser = getParser();
4333   SMLoc S = Parser.getTok().getLoc();
4334   const AsmToken &Tok = Parser.getTok();
4335   if (!Tok.is(AsmToken::Identifier))
4336     return MatchOperand_NoMatch;
4337   StringRef IFlagsStr = Tok.getString();
4338
4339   // An iflags string of "none" is interpreted to mean that none of the AIF
4340   // bits are set.  Not a terribly useful instruction, but a valid encoding.
4341   unsigned IFlags = 0;
4342   if (IFlagsStr != "none") {
4343         for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
4344       unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1).lower())
4345         .Case("a", ARM_PROC::A)
4346         .Case("i", ARM_PROC::I)
4347         .Case("f", ARM_PROC::F)
4348         .Default(~0U);
4349
4350       // If some specific iflag is already set, it means that some letter is
4351       // present more than once, this is not acceptable.
4352       if (Flag == ~0U || (IFlags & Flag))
4353         return MatchOperand_NoMatch;
4354
4355       IFlags |= Flag;
4356     }
4357   }
4358
4359   Parser.Lex(); // Eat identifier token.
4360   Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
4361   return MatchOperand_Success;
4362 }
4363
4364 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
4365 OperandMatchResultTy
4366 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
4367   MCAsmParser &Parser = getParser();
4368   SMLoc S = Parser.getTok().getLoc();
4369   const AsmToken &Tok = Parser.getTok();
4370
4371   if (Tok.is(AsmToken::Integer)) {
4372     int64_t Val = Tok.getIntVal();
4373     if (Val > 255 || Val < 0) {
4374       return MatchOperand_NoMatch;
4375     }
4376     unsigned SYSmvalue = Val & 0xFF;
4377     Parser.Lex();
4378     Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
4379     return MatchOperand_Success;
4380   }
4381
4382   if (!Tok.is(AsmToken::Identifier))
4383     return MatchOperand_NoMatch;
4384   StringRef Mask = Tok.getString();
4385
4386   if (isMClass()) {
4387     auto TheReg = ARMSysReg::lookupMClassSysRegByName(Mask.lower());
4388     if (!TheReg || !TheReg->hasRequiredFeatures(getSTI().getFeatureBits()))
4389       return MatchOperand_NoMatch;
4390
4391     unsigned SYSmvalue = TheReg->Encoding & 0xFFF;
4392
4393     Parser.Lex(); // Eat identifier token.
4394     Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
4395     return MatchOperand_Success;
4396   }
4397
4398   // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
4399   size_t Start = 0, Next = Mask.find('_');
4400   StringRef Flags = "";
4401   std::string SpecReg = Mask.slice(Start, Next).lower();
4402   if (Next != StringRef::npos)
4403     Flags = Mask.slice(Next+1, Mask.size());
4404
4405   // FlagsVal contains the complete mask:
4406   // 3-0: Mask
4407   // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4408   unsigned FlagsVal = 0;
4409
4410   if (SpecReg == "apsr") {
4411     FlagsVal = StringSwitch<unsigned>(Flags)
4412     .Case("nzcvq",  0x8) // same as CPSR_f
4413     .Case("g",      0x4) // same as CPSR_s
4414     .Case("nzcvqg", 0xc) // same as CPSR_fs
4415     .Default(~0U);
4416
4417     if (FlagsVal == ~0U) {
4418       if (!Flags.empty())
4419         return MatchOperand_NoMatch;
4420       else
4421         FlagsVal = 8; // No flag
4422     }
4423   } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
4424     // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
4425     if (Flags == "all" || Flags == "")
4426       Flags = "fc";
4427     for (int i = 0, e = Flags.size(); i != e; ++i) {
4428       unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
4429       .Case("c", 1)
4430       .Case("x", 2)
4431       .Case("s", 4)
4432       .Case("f", 8)
4433       .Default(~0U);
4434
4435       // If some specific flag is already set, it means that some letter is
4436       // present more than once, this is not acceptable.
4437       if (Flag == ~0U || (FlagsVal & Flag))
4438         return MatchOperand_NoMatch;
4439       FlagsVal |= Flag;
4440     }
4441   } else // No match for special register.
4442     return MatchOperand_NoMatch;
4443
4444   // Special register without flags is NOT equivalent to "fc" flags.
4445   // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
4446   // two lines would enable gas compatibility at the expense of breaking
4447   // round-tripping.
4448   //
4449   // if (!FlagsVal)
4450   //  FlagsVal = 0x9;
4451
4452   // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4453   if (SpecReg == "spsr")
4454     FlagsVal |= 16;
4455
4456   Parser.Lex(); // Eat identifier token.
4457   Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4458   return MatchOperand_Success;
4459 }
4460
4461 /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
4462 /// use in the MRS/MSR instructions added to support virtualization.
4463 OperandMatchResultTy
4464 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
4465   MCAsmParser &Parser = getParser();
4466   SMLoc S = Parser.getTok().getLoc();
4467   const AsmToken &Tok = Parser.getTok();
4468   if (!Tok.is(AsmToken::Identifier))
4469     return MatchOperand_NoMatch;
4470   StringRef RegName = Tok.getString();
4471
4472   auto TheReg = ARMBankedReg::lookupBankedRegByName(RegName.lower());
4473   if (!TheReg)
4474     return MatchOperand_NoMatch;
4475   unsigned Encoding = TheReg->Encoding;
4476
4477   Parser.Lex(); // Eat identifier token.
4478   Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
4479   return MatchOperand_Success;
4480 }
4481
4482 OperandMatchResultTy
4483 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
4484                           int High) {
4485   MCAsmParser &Parser = getParser();
4486   const AsmToken &Tok = Parser.getTok();
4487   if (Tok.isNot(AsmToken::Identifier)) {
4488     Error(Parser.getTok().getLoc(), Op + " operand expected.");
4489     return MatchOperand_ParseFail;
4490   }
4491   StringRef ShiftName = Tok.getString();
4492   std::string LowerOp = Op.lower();
4493   std::string UpperOp = Op.upper();
4494   if (ShiftName != LowerOp && ShiftName != UpperOp) {
4495     Error(Parser.getTok().getLoc(), Op + " operand expected.");
4496     return MatchOperand_ParseFail;
4497   }
4498   Parser.Lex(); // Eat shift type token.
4499
4500   // There must be a '#' and a shift amount.
4501   if (Parser.getTok().isNot(AsmToken::Hash) &&
4502       Parser.getTok().isNot(AsmToken::Dollar)) {
4503     Error(Parser.getTok().getLoc(), "'#' expected");
4504     return MatchOperand_ParseFail;
4505   }
4506   Parser.Lex(); // Eat hash token.
4507
4508   const MCExpr *ShiftAmount;
4509   SMLoc Loc = Parser.getTok().getLoc();
4510   SMLoc EndLoc;
4511   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4512     Error(Loc, "illegal expression");
4513     return MatchOperand_ParseFail;
4514   }
4515   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4516   if (!CE) {
4517     Error(Loc, "constant expression expected");
4518     return MatchOperand_ParseFail;
4519   }
4520   int Val = CE->getValue();
4521   if (Val < Low || Val > High) {
4522     Error(Loc, "immediate value out of range");
4523     return MatchOperand_ParseFail;
4524   }
4525
4526   Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
4527
4528   return MatchOperand_Success;
4529 }
4530
4531 OperandMatchResultTy
4532 ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
4533   MCAsmParser &Parser = getParser();
4534   const AsmToken &Tok = Parser.getTok();
4535   SMLoc S = Tok.getLoc();
4536   if (Tok.isNot(AsmToken::Identifier)) {
4537     Error(S, "'be' or 'le' operand expected");
4538     return MatchOperand_ParseFail;
4539   }
4540   int Val = StringSwitch<int>(Tok.getString().lower())
4541     .Case("be", 1)
4542     .Case("le", 0)
4543     .Default(-1);
4544   Parser.Lex(); // Eat the token.
4545
4546   if (Val == -1) {
4547     Error(S, "'be' or 'le' operand expected");
4548     return MatchOperand_ParseFail;
4549   }
4550   Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val,
4551                                                                   getContext()),
4552                                            S, Tok.getEndLoc()));
4553   return MatchOperand_Success;
4554 }
4555
4556 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
4557 /// instructions. Legal values are:
4558 ///     lsl #n  'n' in [0,31]
4559 ///     asr #n  'n' in [1,32]
4560 ///             n == 32 encoded as n == 0.
4561 OperandMatchResultTy
4562 ARMAsmParser::parseShifterImm(OperandVector &Operands) {
4563   MCAsmParser &Parser = getParser();
4564   const AsmToken &Tok = Parser.getTok();
4565   SMLoc S = Tok.getLoc();
4566   if (Tok.isNot(AsmToken::Identifier)) {
4567     Error(S, "shift operator 'asr' or 'lsl' expected");
4568     return MatchOperand_ParseFail;
4569   }
4570   StringRef ShiftName = Tok.getString();
4571   bool isASR;
4572   if (ShiftName == "lsl" || ShiftName == "LSL")
4573     isASR = false;
4574   else if (ShiftName == "asr" || ShiftName == "ASR")
4575     isASR = true;
4576   else {
4577     Error(S, "shift operator 'asr' or 'lsl' expected");
4578     return MatchOperand_ParseFail;
4579   }
4580   Parser.Lex(); // Eat the operator.
4581
4582   // A '#' and a shift amount.
4583   if (Parser.getTok().isNot(AsmToken::Hash) &&
4584       Parser.getTok().isNot(AsmToken::Dollar)) {
4585     Error(Parser.getTok().getLoc(), "'#' expected");
4586     return MatchOperand_ParseFail;
4587   }
4588   Parser.Lex(); // Eat hash token.
4589   SMLoc ExLoc = Parser.getTok().getLoc();
4590
4591   const MCExpr *ShiftAmount;
4592   SMLoc EndLoc;
4593   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4594     Error(ExLoc, "malformed shift expression");
4595     return MatchOperand_ParseFail;
4596   }
4597   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4598   if (!CE) {
4599     Error(ExLoc, "shift amount must be an immediate");
4600     return MatchOperand_ParseFail;
4601   }
4602
4603   int64_t Val = CE->getValue();
4604   if (isASR) {
4605     // Shift amount must be in [1,32]
4606     if (Val < 1 || Val > 32) {
4607       Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4608       return MatchOperand_ParseFail;
4609     }
4610     // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4611     if (isThumb() && Val == 32) {
4612       Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4613       return MatchOperand_ParseFail;
4614     }
4615     if (Val == 32) Val = 0;
4616   } else {
4617     // Shift amount must be in [1,32]
4618     if (Val < 0 || Val > 31) {
4619       Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4620       return MatchOperand_ParseFail;
4621     }
4622   }
4623
4624   Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4625
4626   return MatchOperand_Success;
4627 }
4628
4629 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4630 /// of instructions. Legal values are:
4631 ///     ror #n  'n' in {0, 8, 16, 24}
4632 OperandMatchResultTy
4633 ARMAsmParser::parseRotImm(OperandVector &Operands) {
4634   MCAsmParser &Parser = getParser();
4635   const AsmToken &Tok = Parser.getTok();
4636   SMLoc S = Tok.getLoc();
4637   if (Tok.isNot(AsmToken::Identifier))
4638     return MatchOperand_NoMatch;
4639   StringRef ShiftName = Tok.getString();
4640   if (ShiftName != "ror" && ShiftName != "ROR")
4641     return MatchOperand_NoMatch;
4642   Parser.Lex(); // Eat the operator.
4643
4644   // A '#' and a rotate amount.
4645   if (Parser.getTok().isNot(AsmToken::Hash) &&
4646       Parser.getTok().isNot(AsmToken::Dollar)) {
4647     Error(Parser.getTok().getLoc(), "'#' expected");
4648     return MatchOperand_ParseFail;
4649   }
4650   Parser.Lex(); // Eat hash token.
4651   SMLoc ExLoc = Parser.getTok().getLoc();
4652
4653   const MCExpr *ShiftAmount;
4654   SMLoc EndLoc;
4655   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4656     Error(ExLoc, "malformed rotate expression");
4657     return MatchOperand_ParseFail;
4658   }
4659   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4660   if (!CE) {
4661     Error(ExLoc, "rotate amount must be an immediate");
4662     return MatchOperand_ParseFail;
4663   }
4664
4665   int64_t Val = CE->getValue();
4666   // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4667   // normally, zero is represented in asm by omitting the rotate operand
4668   // entirely.
4669   if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4670     Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4671     return MatchOperand_ParseFail;
4672   }
4673
4674   Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4675
4676   return MatchOperand_Success;
4677 }
4678
4679 OperandMatchResultTy
4680 ARMAsmParser::parseModImm(OperandVector &Operands) {
4681   MCAsmParser &Parser = getParser();
4682   MCAsmLexer &Lexer = getLexer();
4683   int64_t Imm1, Imm2;
4684
4685   SMLoc S = Parser.getTok().getLoc();
4686
4687   // 1) A mod_imm operand can appear in the place of a register name:
4688   //   add r0, #mod_imm
4689   //   add r0, r0, #mod_imm
4690   // to correctly handle the latter, we bail out as soon as we see an
4691   // identifier.
4692   //
4693   // 2) Similarly, we do not want to parse into complex operands:
4694   //   mov r0, #mod_imm
4695   //   mov r0, :lower16:(_foo)
4696   if (Parser.getTok().is(AsmToken::Identifier) ||
4697       Parser.getTok().is(AsmToken::Colon))
4698     return MatchOperand_NoMatch;
4699
4700   // Hash (dollar) is optional as per the ARMARM
4701   if (Parser.getTok().is(AsmToken::Hash) ||
4702       Parser.getTok().is(AsmToken::Dollar)) {
4703     // Avoid parsing into complex operands (#:)
4704     if (Lexer.peekTok().is(AsmToken::Colon))
4705       return MatchOperand_NoMatch;
4706
4707     // Eat the hash (dollar)
4708     Parser.Lex();
4709   }
4710
4711   SMLoc Sx1, Ex1;
4712   Sx1 = Parser.getTok().getLoc();
4713   const MCExpr *Imm1Exp;
4714   if (getParser().parseExpression(Imm1Exp, Ex1)) {
4715     Error(Sx1, "malformed expression");
4716     return MatchOperand_ParseFail;
4717   }
4718
4719   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp);
4720
4721   if (CE) {
4722     // Immediate must fit within 32-bits
4723     Imm1 = CE->getValue();
4724     int Enc = ARM_AM::getSOImmVal(Imm1);
4725     if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) {
4726       // We have a match!
4727       Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF),
4728                                                   (Enc & 0xF00) >> 7,
4729                                                   Sx1, Ex1));
4730       return MatchOperand_Success;
4731     }
4732
4733     // We have parsed an immediate which is not for us, fallback to a plain
4734     // immediate. This can happen for instruction aliases. For an example,
4735     // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform
4736     // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite
4737     // instruction with a mod_imm operand. The alias is defined such that the
4738     // parser method is shared, that's why we have to do this here.
4739     if (Parser.getTok().is(AsmToken::EndOfStatement)) {
4740       Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4741       return MatchOperand_Success;
4742     }
4743   } else {
4744     // Operands like #(l1 - l2) can only be evaluated at a later stage (via an
4745     // MCFixup). Fallback to a plain immediate.
4746     Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4747     return MatchOperand_Success;
4748   }
4749
4750   // From this point onward, we expect the input to be a (#bits, #rot) pair
4751   if (Parser.getTok().isNot(AsmToken::Comma)) {
4752     Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]");
4753     return MatchOperand_ParseFail;
4754   }
4755
4756   if (Imm1 & ~0xFF) {
4757     Error(Sx1, "immediate operand must a number in the range [0, 255]");
4758     return MatchOperand_ParseFail;
4759   }
4760
4761   // Eat the comma
4762   Parser.Lex();
4763
4764   // Repeat for #rot
4765   SMLoc Sx2, Ex2;
4766   Sx2 = Parser.getTok().getLoc();
4767
4768   // Eat the optional hash (dollar)
4769   if (Parser.getTok().is(AsmToken::Hash) ||
4770       Parser.getTok().is(AsmToken::Dollar))
4771     Parser.Lex();
4772
4773   const MCExpr *Imm2Exp;
4774   if (getParser().parseExpression(Imm2Exp, Ex2)) {
4775     Error(Sx2, "malformed expression");
4776     return MatchOperand_ParseFail;
4777   }
4778
4779   CE = dyn_cast<MCConstantExpr>(Imm2Exp);
4780
4781   if (CE) {
4782     Imm2 = CE->getValue();
4783     if (!(Imm2 & ~0x1E)) {
4784       // We have a match!
4785       Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2));
4786       return MatchOperand_Success;
4787     }
4788     Error(Sx2, "immediate operand must an even number in the range [0, 30]");
4789     return MatchOperand_ParseFail;
4790   } else {
4791     Error(Sx2, "constant expression expected");
4792     return MatchOperand_ParseFail;
4793   }
4794 }
4795
4796 OperandMatchResultTy
4797 ARMAsmParser::parseBitfield(OperandVector &Operands) {
4798   MCAsmParser &Parser = getParser();
4799   SMLoc S = Parser.getTok().getLoc();
4800   // The bitfield descriptor is really two operands, the LSB and the width.
4801   if (Parser.getTok().isNot(AsmToken::Hash) &&
4802       Parser.getTok().isNot(AsmToken::Dollar)) {
4803     Error(Parser.getTok().getLoc(), "'#' expected");
4804     return MatchOperand_ParseFail;
4805   }
4806   Parser.Lex(); // Eat hash token.
4807
4808   const MCExpr *LSBExpr;
4809   SMLoc E = Parser.getTok().getLoc();
4810   if (getParser().parseExpression(LSBExpr)) {
4811     Error(E, "malformed immediate expression");
4812     return MatchOperand_ParseFail;
4813   }
4814   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4815   if (!CE) {
4816     Error(E, "'lsb' operand must be an immediate");
4817     return MatchOperand_ParseFail;
4818   }
4819
4820   int64_t LSB = CE->getValue();
4821   // The LSB must be in the range [0,31]
4822   if (LSB < 0 || LSB > 31) {
4823     Error(E, "'lsb' operand must be in the range [0,31]");
4824     return MatchOperand_ParseFail;
4825   }
4826   E = Parser.getTok().getLoc();
4827
4828   // Expect another immediate operand.
4829   if (Parser.getTok().isNot(AsmToken::Comma)) {
4830     Error(Parser.getTok().getLoc(), "too few operands");
4831     return MatchOperand_ParseFail;
4832   }
4833   Parser.Lex(); // Eat hash token.
4834   if (Parser.getTok().isNot(AsmToken::Hash) &&
4835       Parser.getTok().isNot(AsmToken::Dollar)) {
4836     Error(Parser.getTok().getLoc(), "'#' expected");
4837     return MatchOperand_ParseFail;
4838   }
4839   Parser.Lex(); // Eat hash token.
4840
4841   const MCExpr *WidthExpr;
4842   SMLoc EndLoc;
4843   if (getParser().parseExpression(WidthExpr, EndLoc)) {
4844     Error(E, "malformed immediate expression");
4845     return MatchOperand_ParseFail;
4846   }
4847   CE = dyn_cast<MCConstantExpr>(WidthExpr);
4848   if (!CE) {
4849     Error(E, "'width' operand must be an immediate");
4850     return MatchOperand_ParseFail;
4851   }
4852
4853   int64_t Width = CE->getValue();
4854   // The LSB must be in the range [1,32-lsb]
4855   if (Width < 1 || Width > 32 - LSB) {
4856     Error(E, "'width' operand must be in the range [1,32-lsb]");
4857     return MatchOperand_ParseFail;
4858   }
4859
4860   Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4861
4862   return MatchOperand_Success;
4863 }
4864
4865 OperandMatchResultTy
4866 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
4867   // Check for a post-index addressing register operand. Specifically:
4868   // postidx_reg := '+' register {, shift}
4869   //              | '-' register {, shift}
4870   //              | register {, shift}
4871
4872   // This method must return MatchOperand_NoMatch without consuming any tokens
4873   // in the case where there is no match, as other alternatives take other
4874   // parse methods.
4875   MCAsmParser &Parser = getParser();
4876   AsmToken Tok = Parser.getTok();
4877   SMLoc S = Tok.getLoc();
4878   bool haveEaten = false;
4879   bool isAdd = true;
4880   if (Tok.is(AsmToken::Plus)) {
4881     Parser.Lex(); // Eat the '+' token.
4882     haveEaten = true;
4883   } else if (Tok.is(AsmToken::Minus)) {
4884     Parser.Lex(); // Eat the '-' token.
4885     isAdd = false;
4886     haveEaten = true;
4887   }
4888
4889   SMLoc E = Parser.getTok().getEndLoc();
4890   int Reg = tryParseRegister();
4891   if (Reg == -1) {
4892     if (!haveEaten)
4893       return MatchOperand_NoMatch;
4894     Error(Parser.getTok().getLoc(), "register expected");
4895     return MatchOperand_ParseFail;
4896   }
4897
4898   ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4899   unsigned ShiftImm = 0;
4900   if (Parser.getTok().is(AsmToken::Comma)) {
4901     Parser.Lex(); // Eat the ','.
4902     if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4903       return MatchOperand_ParseFail;
4904
4905     // FIXME: Only approximates end...may include intervening whitespace.
4906     E = Parser.getTok().getLoc();
4907   }
4908
4909   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4910                                                   ShiftImm, S, E));
4911
4912   return MatchOperand_Success;
4913 }
4914
4915 OperandMatchResultTy
4916 ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
4917   // Check for a post-index addressing register operand. Specifically:
4918   // am3offset := '+' register
4919   //              | '-' register
4920   //              | register
4921   //              | # imm
4922   //              | # + imm
4923   //              | # - imm
4924
4925   // This method must return MatchOperand_NoMatch without consuming any tokens
4926   // in the case where there is no match, as other alternatives take other
4927   // parse methods.
4928   MCAsmParser &Parser = getParser();
4929   AsmToken Tok = Parser.getTok();
4930   SMLoc S = Tok.getLoc();
4931
4932   // Do immediates first, as we always parse those if we have a '#'.
4933   if (Parser.getTok().is(AsmToken::Hash) ||
4934       Parser.getTok().is(AsmToken::Dollar)) {
4935     Parser.Lex(); // Eat '#' or '$'.
4936     // Explicitly look for a '-', as we need to encode negative zero
4937     // differently.
4938     bool isNegative = Parser.getTok().is(AsmToken::Minus);
4939     const MCExpr *Offset;
4940     SMLoc E;
4941     if (getParser().parseExpression(Offset, E))
4942       return MatchOperand_ParseFail;
4943     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4944     if (!CE) {
4945       Error(S, "constant expression expected");
4946       return MatchOperand_ParseFail;
4947     }
4948     // Negative zero is encoded as the flag value
4949     // std::numeric_limits<int32_t>::min().
4950     int32_t Val = CE->getValue();
4951     if (isNegative && Val == 0)
4952       Val = std::numeric_limits<int32_t>::min();
4953
4954     Operands.push_back(
4955       ARMOperand::CreateImm(MCConstantExpr::create(Val, getContext()), S, E));
4956
4957     return MatchOperand_Success;
4958   }
4959
4960   bool haveEaten = false;
4961   bool isAdd = true;
4962   if (Tok.is(AsmToken::Plus)) {
4963     Parser.Lex(); // Eat the '+' token.
4964     haveEaten = true;
4965   } else if (Tok.is(AsmToken::Minus)) {
4966     Parser.Lex(); // Eat the '-' token.
4967     isAdd = false;
4968     haveEaten = true;
4969   }
4970
4971   Tok = Parser.getTok();
4972   int Reg = tryParseRegister();
4973   if (Reg == -1) {
4974     if (!haveEaten)
4975       return MatchOperand_NoMatch;
4976     Error(Tok.getLoc(), "register expected");
4977     return MatchOperand_ParseFail;
4978   }
4979
4980   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4981                                                   0, S, Tok.getEndLoc()));
4982
4983   return MatchOperand_Success;
4984 }
4985
4986 /// Convert parsed operands to MCInst.  Needed here because this instruction
4987 /// only has two register operands, but multiplication is commutative so
4988 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4989 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
4990                                     const OperandVector &Operands) {
4991   ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
4992   ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
4993   // If we have a three-operand form, make sure to set Rn to be the operand
4994   // that isn't the same as Rd.
4995   unsigned RegOp = 4;
4996   if (Operands.size() == 6 &&
4997       ((ARMOperand &)*Operands[4]).getReg() ==
4998           ((ARMOperand &)*Operands[3]).getReg())
4999     RegOp = 5;
5000   ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
5001   Inst.addOperand(Inst.getOperand(0));
5002   ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
5003 }
5004
5005 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
5006                                     const OperandVector &Operands) {
5007   int CondOp = -1, ImmOp = -1;
5008   switch(Inst.getOpcode()) {
5009     case ARM::tB:
5010     case ARM::tBcc:  CondOp = 1; ImmOp = 2; break;
5011
5012     case ARM::t2B:
5013     case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
5014
5015     default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
5016   }
5017   // first decide whether or not the branch should be conditional
5018   // by looking at it's location relative to an IT block
5019   if(inITBlock()) {
5020     // inside an IT block we cannot have any conditional branches. any
5021     // such instructions needs to be converted to unconditional form
5022     switch(Inst.getOpcode()) {
5023       case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
5024       case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
5025     }
5026   } else {
5027     // outside IT blocks we can only have unconditional branches with AL
5028     // condition code or conditional branches with non-AL condition code
5029     unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
5030     switch(Inst.getOpcode()) {
5031       case ARM::tB:
5032       case ARM::tBcc:
5033         Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
5034         break;
5035       case ARM::t2B:
5036       case ARM::t2Bcc:
5037         Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
5038         break;
5039     }
5040   }
5041
5042   // now decide on encoding size based on branch target range
5043   switch(Inst.getOpcode()) {
5044     // classify tB as either t2B or t1B based on range of immediate operand
5045     case ARM::tB: {
5046       ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
5047       if (!op.isSignedOffset<11, 1>() && isThumb() && hasV8MBaseline())
5048         Inst.setOpcode(ARM::t2B);
5049       break;
5050     }
5051     // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
5052     case ARM::tBcc: {
5053       ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
5054       if (!op.isSignedOffset<8, 1>() && isThumb() && hasV8MBaseline())
5055         Inst.setOpcode(ARM::t2Bcc);
5056       break;
5057     }
5058   }
5059   ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
5060   ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
5061 }
5062
5063 /// Parse an ARM memory expression, return false if successful else return true
5064 /// or an error.  The first token must be a '[' when called.
5065 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
5066   MCAsmParser &Parser = getParser();
5067   SMLoc S, E;
5068   if (Parser.getTok().isNot(AsmToken::LBrac))
5069     return TokError("Token is not a Left Bracket");
5070   S = Parser.getTok().getLoc();
5071   Parser.Lex(); // Eat left bracket token.
5072
5073   const AsmToken &BaseRegTok = Parser.getTok();
5074   int BaseRegNum = tryParseRegister();
5075   if (BaseRegNum == -1)
5076     return Error(BaseRegTok.getLoc(), "register expected");
5077
5078   // The next token must either be a comma, a colon or a closing bracket.
5079   const AsmToken &Tok = Parser.getTok();
5080   if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
5081       !Tok.is(AsmToken::RBrac))
5082     return Error(Tok.getLoc(), "malformed memory operand");
5083
5084   if (Tok.is(AsmToken::RBrac)) {
5085     E = Tok.getEndLoc();
5086     Parser.Lex(); // Eat right bracket token.
5087
5088     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
5089                                              ARM_AM::no_shift, 0, 0, false,
5090                                              S, E));
5091
5092     // If there's a pre-indexing writeback marker, '!', just add it as a token
5093     // operand. It's rather odd, but syntactically valid.
5094     if (Parser.getTok().is(AsmToken::Exclaim)) {
5095       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5096       Parser.Lex(); // Eat the '!'.
5097     }
5098
5099     return false;
5100   }
5101
5102   assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
5103          "Lost colon or comma in memory operand?!");
5104   if (Tok.is(AsmToken::Comma)) {
5105     Parser.Lex(); // Eat the comma.
5106   }
5107
5108   // If we have a ':', it's an alignment specifier.
5109   if (Parser.getTok().is(AsmToken::Colon)) {
5110     Parser.Lex(); // Eat the ':'.
5111     E = Parser.getTok().getLoc();
5112     SMLoc AlignmentLoc = Tok.getLoc();
5113
5114     const MCExpr *Expr;
5115     if (getParser().parseExpression(Expr))
5116      return true;
5117
5118     // The expression has to be a constant. Memory references with relocations
5119     // don't come through here, as they use the <label> forms of the relevant
5120     // instructions.
5121     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
5122     if (!CE)
5123       return Error (E, "constant expression expected");
5124
5125     unsigned Align = 0;
5126     switch (CE->getValue()) {
5127     default:
5128       return Error(E,
5129                    "alignment specifier must be 16, 32, 64, 128, or 256 bits");
5130     case 16:  Align = 2; break;
5131     case 32:  Align = 4; break;
5132     case 64:  Align = 8; break;
5133     case 128: Align = 16; break;
5134     case 256: Align = 32; break;
5135     }
5136
5137     // Now we should have the closing ']'
5138     if (Parser.getTok().isNot(AsmToken::RBrac))
5139       return Error(Parser.getTok().getLoc(), "']' expected");
5140     E = Parser.getTok().getEndLoc();
5141     Parser.Lex(); // Eat right bracket token.
5142
5143     // Don't worry about range checking the value here. That's handled by
5144     // the is*() predicates.
5145     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
5146                                              ARM_AM::no_shift, 0, Align,
5147                                              false, S, E, AlignmentLoc));
5148
5149     // If there's a pre-indexing writeback marker, '!', just add it as a token
5150     // operand.
5151     if (Parser.getTok().is(AsmToken::Exclaim)) {
5152       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5153       Parser.Lex(); // Eat the '!'.
5154     }
5155
5156     return false;
5157   }
5158
5159   // If we have a '#', it's an immediate offset, else assume it's a register
5160   // offset. Be friendly and also accept a plain integer (without a leading
5161   // hash) for gas compatibility.
5162   if (Parser.getTok().is(AsmToken::Hash) ||
5163       Parser.getTok().is(AsmToken::Dollar) ||
5164       Parser.getTok().is(AsmToken::Integer)) {
5165     if (Parser.getTok().isNot(AsmToken::Integer))
5166       Parser.Lex(); // Eat '#' or '$'.
5167     E = Parser.getTok().getLoc();
5168
5169     bool isNegative = getParser().getTok().is(AsmToken::Minus);
5170     const MCExpr *Offset;
5171     if (getParser().parseExpression(Offset))
5172      return true;
5173
5174     // The expression has to be a constant. Memory references with relocations
5175     // don't come through here, as they use the <label> forms of the relevant
5176     // instructions.
5177     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
5178     if (!CE)
5179       return Error (E, "constant expression expected");
5180
5181     // If the constant was #-0, represent it as
5182     // std::numeric_limits<int32_t>::min().
5183     int32_t Val = CE->getValue();
5184     if (isNegative && Val == 0)
5185       CE = MCConstantExpr::create(std::numeric_limits<int32_t>::min(),
5186                                   getContext());
5187
5188     // Now we should have the closing ']'
5189     if (Parser.getTok().isNot(AsmToken::RBrac))
5190       return Error(Parser.getTok().getLoc(), "']' expected");
5191     E = Parser.getTok().getEndLoc();
5192     Parser.Lex(); // Eat right bracket token.
5193
5194     // Don't worry about range checking the value here. That's handled by
5195     // the is*() predicates.
5196     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
5197                                              ARM_AM::no_shift, 0, 0,
5198                                              false, S, E));
5199
5200     // If there's a pre-indexing writeback marker, '!', just add it as a token
5201     // operand.
5202     if (Parser.getTok().is(AsmToken::Exclaim)) {
5203       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5204       Parser.Lex(); // Eat the '!'.
5205     }
5206
5207     return false;
5208   }
5209
5210   // The register offset is optionally preceded by a '+' or '-'
5211   bool isNegative = false;
5212   if (Parser.getTok().is(AsmToken::Minus)) {
5213     isNegative = true;
5214     Parser.Lex(); // Eat the '-'.
5215   } else if (Parser.getTok().is(AsmToken::Plus)) {
5216     // Nothing to do.
5217     Parser.Lex(); // Eat the '+'.
5218   }
5219
5220   E = Parser.getTok().getLoc();
5221   int OffsetRegNum = tryParseRegister();
5222   if (OffsetRegNum == -1)
5223     return Error(E, "register expected");
5224
5225   // If there's a shift operator, handle it.
5226   ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
5227   unsigned ShiftImm = 0;
5228   if (Parser.getTok().is(AsmToken::Comma)) {
5229     Parser.Lex(); // Eat the ','.
5230     if (parseMemRegOffsetShift(ShiftType, ShiftImm))
5231       return true;
5232   }
5233
5234   // Now we should have the closing ']'
5235   if (Parser.getTok().isNot(AsmToken::RBrac))
5236     return Error(Parser.getTok().getLoc(), "']' expected");
5237   E = Parser.getTok().getEndLoc();
5238   Parser.Lex(); // Eat right bracket token.
5239
5240   Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
5241                                            ShiftType, ShiftImm, 0, isNegative,
5242                                            S, E));
5243
5244   // If there's a pre-indexing writeback marker, '!', just add it as a token
5245   // operand.
5246   if (Parser.getTok().is(AsmToken::Exclaim)) {
5247     Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5248     Parser.Lex(); // Eat the '!'.
5249   }
5250
5251   return false;
5252 }
5253
5254 /// parseMemRegOffsetShift - one of these two:
5255 ///   ( lsl | lsr | asr | ror ) , # shift_amount
5256 ///   rrx
5257 /// return true if it parses a shift otherwise it returns false.
5258 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
5259                                           unsigned &Amount) {
5260   MCAsmParser &Parser = getParser();
5261   SMLoc Loc = Parser.getTok().getLoc();
5262   const AsmToken &Tok = Parser.getTok();
5263   if (Tok.isNot(AsmToken::Identifier))
5264     return Error(Loc, "illegal shift operator");
5265   StringRef ShiftName = Tok.getString();
5266   if (ShiftName == "lsl" || ShiftName == "LSL" ||
5267       ShiftName == "asl" || ShiftName == "ASL")
5268     St = ARM_AM::lsl;
5269   else if (ShiftName == "lsr" || ShiftName == "LSR")
5270     St = ARM_AM::lsr;
5271   else if (ShiftName == "asr" || ShiftName == "ASR")
5272     St = ARM_AM::asr;
5273   else if (ShiftName == "ror" || ShiftName == "ROR")
5274     St = ARM_AM::ror;
5275   else if (ShiftName == "rrx" || ShiftName == "RRX")
5276     St = ARM_AM::rrx;
5277   else
5278     return Error(Loc, "illegal shift operator");
5279   Parser.Lex(); // Eat shift type token.
5280
5281   // rrx stands alone.
5282   Amount = 0;
5283   if (St != ARM_AM::rrx) {
5284     Loc = Parser.getTok().getLoc();
5285     // A '#' and a shift amount.
5286     const AsmToken &HashTok = Parser.getTok();
5287     if (HashTok.isNot(AsmToken::Hash) &&
5288         HashTok.isNot(AsmToken::Dollar))
5289       return Error(HashTok.getLoc(), "'#' expected");
5290     Parser.Lex(); // Eat hash token.
5291
5292     const MCExpr *Expr;
5293     if (getParser().parseExpression(Expr))
5294       return true;
5295     // Range check the immediate.
5296     // lsl, ror: 0 <= imm <= 31
5297     // lsr, asr: 0 <= imm <= 32
5298     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
5299     if (!CE)
5300       return Error(Loc, "shift amount must be an immediate");
5301     int64_t Imm = CE->getValue();
5302     if (Imm < 0 ||
5303         ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
5304         ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
5305       return Error(Loc, "immediate shift value out of range");
5306     // If <ShiftTy> #0, turn it into a no_shift.
5307     if (Imm == 0)
5308       St = ARM_AM::lsl;
5309     // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
5310     if (Imm == 32)
5311       Imm = 0;
5312     Amount = Imm;
5313   }
5314
5315   return false;
5316 }
5317
5318 /// parseFPImm - A floating point immediate expression operand.
5319 OperandMatchResultTy
5320 ARMAsmParser::parseFPImm(OperandVector &Operands) {
5321   MCAsmParser &Parser = getParser();
5322   // Anything that can accept a floating point constant as an operand
5323   // needs to go through here, as the regular parseExpression is
5324   // integer only.
5325   //
5326   // This routine still creates a generic Immediate operand, containing
5327   // a bitcast of the 64-bit floating point value. The various operands
5328   // that accept floats can check whether the value is valid for them
5329   // via the standard is*() predicates.
5330
5331   SMLoc S = Parser.getTok().getLoc();
5332
5333   if (Parser.getTok().isNot(AsmToken::Hash) &&
5334       Parser.getTok().isNot(AsmToken::Dollar))
5335     return MatchOperand_NoMatch;
5336
5337   // Disambiguate the VMOV forms that can accept an FP immediate.
5338   // vmov.f32 <sreg>, #imm
5339   // vmov.f64 <dreg>, #imm
5340   // vmov.f32 <dreg>, #imm  @ vector f32x2
5341   // vmov.f32 <qreg>, #imm  @ vector f32x4
5342   //
5343   // There are also the NEON VMOV instructions which expect an
5344   // integer constant. Make sure we don't try to parse an FPImm
5345   // for these:
5346   // vmov.i{8|16|32|64} <dreg|qreg>, #imm
5347   ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
5348   bool isVmovf = TyOp.isToken() &&
5349                  (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64" ||
5350                   TyOp.getToken() == ".f16");
5351   ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
5352   bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
5353                                          Mnemonic.getToken() == "fconsts");
5354   if (!(isVmovf || isFconst))
5355     return MatchOperand_NoMatch;
5356
5357   Parser.Lex(); // Eat '#' or '$'.
5358
5359   // Handle negation, as that still comes through as a separate token.
5360   bool isNegative = false;
5361   if (Parser.getTok().is(AsmToken::Minus)) {
5362     isNegative = true;
5363     Parser.Lex();
5364   }
5365   const AsmToken &Tok = Parser.getTok();
5366   SMLoc Loc = Tok.getLoc();
5367   if (Tok.is(AsmToken::Real) && isVmovf) {
5368     APFloat RealVal(APFloat::IEEEsingle(), Tok.getString());
5369     uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
5370     // If we had a '-' in front, toggle the sign bit.
5371     IntVal ^= (uint64_t)isNegative << 31;
5372     Parser.Lex(); // Eat the token.
5373     Operands.push_back(ARMOperand::CreateImm(
5374           MCConstantExpr::create(IntVal, getContext()),
5375           S, Parser.getTok().getLoc()));
5376     return MatchOperand_Success;
5377   }
5378   // Also handle plain integers. Instructions which allow floating point
5379   // immediates also allow a raw encoded 8-bit value.
5380   if (Tok.is(AsmToken::Integer) && isFconst) {
5381     int64_t Val = Tok.getIntVal();
5382     Parser.Lex(); // Eat the token.
5383     if (Val > 255 || Val < 0) {
5384       Error(Loc, "encoded floating point value out of range");
5385       return MatchOperand_ParseFail;
5386     }
5387     float RealVal = ARM_AM::getFPImmFloat(Val);
5388     Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
5389
5390     Operands.push_back(ARMOperand::CreateImm(
5391         MCConstantExpr::create(Val, getContext()), S,
5392         Parser.getTok().getLoc()));
5393     return MatchOperand_Success;
5394   }
5395
5396   Error(Loc, "invalid floating point immediate");
5397   return MatchOperand_ParseFail;
5398 }
5399
5400 /// Parse a arm instruction operand.  For now this parses the operand regardless
5401 /// of the mnemonic.
5402 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
5403   MCAsmParser &Parser = getParser();
5404   SMLoc S, E;
5405
5406   // Check if the current operand has a custom associated parser, if so, try to
5407   // custom parse the operand, or fallback to the general approach.
5408   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
5409   if (ResTy == MatchOperand_Success)
5410     return false;
5411   // If there wasn't a custom match, try the generic matcher below. Otherwise,
5412   // there was a match, but an error occurred, in which case, just return that
5413   // the operand parsing failed.
5414   if (ResTy == MatchOperand_ParseFail)
5415     return true;
5416
5417   switch (getLexer().getKind()) {
5418   default:
5419     Error(Parser.getTok().getLoc(), "unexpected token in operand");
5420     return true;
5421   case AsmToken::Identifier: {
5422     // If we've seen a branch mnemonic, the next operand must be a label.  This
5423     // is true even if the label is a register name.  So "br r1" means branch to
5424     // label "r1".
5425     bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
5426     if (!ExpectLabel) {
5427       if (!tryParseRegisterWithWriteBack(Operands))
5428         return false;
5429       int Res = tryParseShiftRegister(Operands);
5430       if (Res == 0) // success
5431         return false;
5432       else if (Res == -1) // irrecoverable error
5433         return true;
5434       // If this is VMRS, check for the apsr_nzcv operand.
5435       if (Mnemonic == "vmrs" &&
5436           Parser.getTok().getString().equals_lower("apsr_nzcv")) {
5437         S = Parser.getTok().getLoc();
5438         Parser.Lex();
5439         Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
5440         return false;
5441       }
5442     }
5443
5444     // Fall though for the Identifier case that is not a register or a
5445     // special name.
5446     LLVM_FALLTHROUGH;
5447   }
5448   case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
5449   case AsmToken::Integer: // things like 1f and 2b as a branch targets
5450   case AsmToken::String:  // quoted label names.
5451   case AsmToken::Dot: {   // . as a branch target
5452     // This was not a register so parse other operands that start with an
5453     // identifier (like labels) as expressions and create them as immediates.
5454     const MCExpr *IdVal;
5455     S = Parser.getTok().getLoc();
5456     if (getParser().parseExpression(IdVal))
5457       return true;
5458     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5459     Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
5460     return false;
5461   }
5462   case AsmToken::LBrac:
5463     return parseMemory(Operands);
5464   case AsmToken::LCurly:
5465     return parseRegisterList(Operands);
5466   case AsmToken::Dollar:
5467   case AsmToken::Hash:
5468     // #42 -> immediate.
5469     S = Parser.getTok().getLoc();
5470     Parser.Lex();
5471
5472     if (Parser.getTok().isNot(AsmToken::Colon)) {
5473       bool isNegative = Parser.getTok().is(AsmToken::Minus);
5474       const MCExpr *ImmVal;
5475       if (getParser().parseExpression(ImmVal))
5476         return true;
5477       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
5478       if (CE) {
5479         int32_t Val = CE->getValue();
5480         if (isNegative && Val == 0)
5481           ImmVal = MCConstantExpr::create(std::numeric_limits<int32_t>::min(),
5482                                           getContext());
5483       }
5484       E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5485       Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
5486
5487       // There can be a trailing '!' on operands that we want as a separate
5488       // '!' Token operand. Handle that here. For example, the compatibility
5489       // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
5490       if (Parser.getTok().is(AsmToken::Exclaim)) {
5491         Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
5492                                                    Parser.getTok().getLoc()));
5493         Parser.Lex(); // Eat exclaim token
5494       }
5495       return false;
5496     }
5497     // w/ a ':' after the '#', it's just like a plain ':'.
5498     LLVM_FALLTHROUGH;
5499
5500   case AsmToken::Colon: {
5501     S = Parser.getTok().getLoc();
5502     // ":lower16:" and ":upper16:" expression prefixes
5503     // FIXME: Check it's an expression prefix,
5504     // e.g. (FOO - :lower16:BAR) isn't legal.
5505     ARMMCExpr::VariantKind RefKind;
5506     if (parsePrefix(RefKind))
5507       return true;
5508
5509     const MCExpr *SubExprVal;
5510     if (getParser().parseExpression(SubExprVal))
5511       return true;
5512
5513     const MCExpr *ExprVal = ARMMCExpr::create(RefKind, SubExprVal,
5514                                               getContext());
5515     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5516     Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
5517     return false;
5518   }
5519   case AsmToken::Equal: {
5520     S = Parser.getTok().getLoc();
5521     if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
5522       return Error(S, "unexpected token in operand");
5523     Parser.Lex(); // Eat '='
5524     const MCExpr *SubExprVal;
5525     if (getParser().parseExpression(SubExprVal))
5526       return true;
5527     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5528
5529     // execute-only: we assume that assembly programmers know what they are
5530     // doing and allow literal pool creation here
5531     Operands.push_back(ARMOperand::CreateConstantPoolImm(SubExprVal, S, E));
5532     return false;
5533   }
5534   }
5535 }
5536
5537 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
5538 //  :lower16: and :upper16:.
5539 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
5540   MCAsmParser &Parser = getParser();
5541   RefKind = ARMMCExpr::VK_ARM_None;
5542
5543   // consume an optional '#' (GNU compatibility)
5544   if (getLexer().is(AsmToken::Hash))
5545     Parser.Lex();
5546
5547   // :lower16: and :upper16: modifiers
5548   assert(getLexer().is(AsmToken::Colon) && "expected a :");
5549   Parser.Lex(); // Eat ':'
5550
5551   if (getLexer().isNot(AsmToken::Identifier)) {
5552     Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
5553     return true;
5554   }
5555
5556   enum {
5557     COFF = (1 << MCObjectFileInfo::IsCOFF),
5558     ELF = (1 << MCObjectFileInfo::IsELF),
5559     MACHO = (1 << MCObjectFileInfo::IsMachO),
5560     WASM = (1 << MCObjectFileInfo::IsWasm),
5561   };
5562   static const struct PrefixEntry {
5563     const char *Spelling;
5564     ARMMCExpr::VariantKind VariantKind;
5565     uint8_t SupportedFormats;
5566   } PrefixEntries[] = {
5567     { "lower16", ARMMCExpr::VK_ARM_LO16, COFF | ELF | MACHO },
5568     { "upper16", ARMMCExpr::VK_ARM_HI16, COFF | ELF | MACHO },
5569   };
5570
5571   StringRef IDVal = Parser.getTok().getIdentifier();
5572
5573   const auto &Prefix =
5574       std::find_if(std::begin(PrefixEntries), std::end(PrefixEntries),
5575                    [&IDVal](const PrefixEntry &PE) {
5576                       return PE.Spelling == IDVal;
5577                    });
5578   if (Prefix == std::end(PrefixEntries)) {
5579     Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
5580     return true;
5581   }
5582
5583   uint8_t CurrentFormat;
5584   switch (getContext().getObjectFileInfo()->getObjectFileType()) {
5585   case MCObjectFileInfo::IsMachO:
5586     CurrentFormat = MACHO;
5587     break;
5588   case MCObjectFileInfo::IsELF:
5589     CurrentFormat = ELF;
5590     break;
5591   case MCObjectFileInfo::IsCOFF:
5592     CurrentFormat = COFF;
5593     break;
5594   case MCObjectFileInfo::IsWasm:
5595     CurrentFormat = WASM;
5596     break;
5597   }
5598
5599   if (~Prefix->SupportedFormats & CurrentFormat) {
5600     Error(Parser.getTok().getLoc(),
5601           "cannot represent relocation in the current file format");
5602     return true;
5603   }
5604
5605   RefKind = Prefix->VariantKind;
5606   Parser.Lex();
5607
5608   if (getLexer().isNot(AsmToken::Colon)) {
5609     Error(Parser.getTok().getLoc(), "unexpected token after prefix");
5610     return true;
5611   }
5612   Parser.Lex(); // Eat the last ':'
5613
5614   return false;
5615 }
5616
5617 /// Given a mnemonic, split out possible predication code and carry
5618 /// setting letters to form a canonical mnemonic and flags.
5619 //
5620 // FIXME: Would be nice to autogen this.
5621 // FIXME: This is a bit of a maze of special cases.
5622 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
5623                                       unsigned &PredicationCode,
5624                                       bool &CarrySetting,
5625                                       unsigned &ProcessorIMod,
5626                                       StringRef &ITMask) {
5627   PredicationCode = ARMCC::AL;
5628   CarrySetting = false;
5629   ProcessorIMod = 0;
5630
5631   // Ignore some mnemonics we know aren't predicated forms.
5632   //
5633   // FIXME: Would be nice to autogen this.
5634   if ((Mnemonic == "movs" && isThumb()) ||
5635       Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
5636       Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
5637       Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
5638       Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
5639       Mnemonic == "vaclt" || Mnemonic == "vacle"  || Mnemonic == "hlt" ||
5640       Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
5641       Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
5642       Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
5643       Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
5644       Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||
5645       Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
5646       Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
5647       Mnemonic.startswith("vsel") || Mnemonic == "vins" || Mnemonic == "vmovx" ||
5648       Mnemonic == "bxns"  || Mnemonic == "blxns" ||
5649       Mnemonic == "vudot" || Mnemonic == "vsdot" ||
5650       Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
5651       Mnemonic == "vfmal" || Mnemonic == "vfmsl")
5652     return Mnemonic;
5653
5654   // First, split out any predication code. Ignore mnemonics we know aren't
5655   // predicated but do have a carry-set and so weren't caught above.
5656   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
5657       Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
5658       Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
5659       Mnemonic != "sbcs" && Mnemonic != "rscs") {
5660     unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
5661     if (CC != ~0U) {
5662       Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
5663       PredicationCode = CC;
5664     }
5665   }
5666
5667   // Next, determine if we have a carry setting bit. We explicitly ignore all
5668   // the instructions we know end in 's'.
5669   if (Mnemonic.endswith("s") &&
5670       !(Mnemonic == "cps" || Mnemonic == "mls" ||
5671         Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
5672         Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
5673         Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
5674         Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
5675         Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
5676         Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
5677         Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
5678         Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
5679         Mnemonic == "bxns" || Mnemonic == "blxns" ||
5680         (Mnemonic == "movs" && isThumb()))) {
5681     Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
5682     CarrySetting = true;
5683   }
5684
5685   // The "cps" instruction can have a interrupt mode operand which is glued into
5686   // the mnemonic. Check if this is the case, split it and parse the imod op
5687   if (Mnemonic.startswith("cps")) {
5688     // Split out any imod code.
5689     unsigned IMod =
5690       StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
5691       .Case("ie", ARM_PROC::IE)
5692       .Case("id", ARM_PROC::ID)
5693       .Default(~0U);
5694     if (IMod != ~0U) {
5695       Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
5696       ProcessorIMod = IMod;
5697     }
5698   }
5699
5700   // The "it" instruction has the condition mask on the end of the mnemonic.
5701   if (Mnemonic.startswith("it")) {
5702     ITMask = Mnemonic.slice(2, Mnemonic.size());
5703     Mnemonic = Mnemonic.slice(0, 2);
5704   }
5705
5706   return Mnemonic;
5707 }
5708
5709 /// Given a canonical mnemonic, determine if the instruction ever allows
5710 /// inclusion of carry set or predication code operands.
5711 //
5712 // FIXME: It would be nice to autogen this.
5713 void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
5714                                          bool &CanAcceptCarrySet,
5715                                          bool &CanAcceptPredicationCode) {
5716   CanAcceptCarrySet =
5717       Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5718       Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
5719       Mnemonic == "add" || Mnemonic == "adc" || Mnemonic == "mul" ||
5720       Mnemonic == "bic" || Mnemonic == "asr" || Mnemonic == "orr" ||
5721       Mnemonic == "mvn" || Mnemonic == "rsb" || Mnemonic == "rsc" ||
5722       Mnemonic == "orn" || Mnemonic == "sbc" || Mnemonic == "eor" ||
5723       Mnemonic == "neg" || Mnemonic == "vfm" || Mnemonic == "vfnm" ||
5724       (!isThumb() &&
5725        (Mnemonic == "smull" || Mnemonic == "mov" || Mnemonic == "mla" ||
5726         Mnemonic == "smlal" || Mnemonic == "umlal" || Mnemonic == "umull"));
5727
5728   if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
5729       Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
5730       Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
5731       Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
5732       Mnemonic.startswith("vsel") || Mnemonic == "vmaxnm" ||
5733       Mnemonic == "vminnm" || Mnemonic == "vcvta" || Mnemonic == "vcvtn" ||
5734       Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || Mnemonic == "vrinta" ||
5735       Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" ||
5736       Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" ||
5737       Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
5738       (FullInst.startswith("vmull") && FullInst.endswith(".p64")) ||
5739       Mnemonic == "vmovx" || Mnemonic == "vins" ||
5740       Mnemonic == "vudot" || Mnemonic == "vsdot" ||
5741       Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
5742       Mnemonic == "vfmal" || Mnemonic == "vfmsl" ||
5743       Mnemonic == "sb"    || Mnemonic == "ssbb"  ||
5744       Mnemonic == "pssbb") {
5745     // These mnemonics are never predicable
5746     CanAcceptPredicationCode = false;
5747   } else if (!isThumb()) {
5748     // Some instructions are only predicable in Thumb mode
5749     CanAcceptPredicationCode =
5750         Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
5751         Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5752         Mnemonic != "dmb" && Mnemonic != "dfb" && Mnemonic != "dsb" &&
5753         Mnemonic != "isb" && Mnemonic != "pld" && Mnemonic != "pli" &&
5754         Mnemonic != "pldw" && Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
5755         Mnemonic != "stc2" && Mnemonic != "stc2l" &&
5756         Mnemonic != "tsb" &&
5757         !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
5758   } else if (isThumbOne()) {
5759     if (hasV6MOps())
5760       CanAcceptPredicationCode = Mnemonic != "movs";
5761     else
5762       CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
5763   } else
5764     CanAcceptPredicationCode = true;
5765 }
5766
5767 // Some Thumb instructions have two operand forms that are not
5768 // available as three operand, convert to two operand form if possible.
5769 //
5770 // FIXME: We would really like to be able to tablegen'erate this.
5771 void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic,
5772                                                  bool CarrySetting,
5773                                                  OperandVector &Operands) {
5774   if (Operands.size() != 6)
5775     return;
5776
5777   const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5778         auto &Op4 = static_cast<ARMOperand &>(*Operands[4]);
5779   if (!Op3.isReg() || !Op4.isReg())
5780     return;
5781
5782   auto Op3Reg = Op3.getReg();
5783   auto Op4Reg = Op4.getReg();
5784
5785   // For most Thumb2 cases we just generate the 3 operand form and reduce
5786   // it in processInstruction(), but the 3 operand form of ADD (t2ADDrr)
5787   // won't accept SP or PC so we do the transformation here taking care
5788   // with immediate range in the 'add sp, sp #imm' case.
5789   auto &Op5 = static_cast<ARMOperand &>(*Operands[5]);
5790   if (isThumbTwo()) {
5791     if (Mnemonic != "add")
5792       return;
5793     bool TryTransform = Op3Reg == ARM::PC || Op4Reg == ARM::PC ||
5794                         (Op5.isReg() && Op5.getReg() == ARM::PC);
5795     if (!TryTransform) {
5796       TryTransform = (Op3Reg == ARM::SP || Op4Reg == ARM::SP ||
5797                       (Op5.isReg() && Op5.getReg() == ARM::SP)) &&
5798                      !(Op3Reg == ARM::SP && Op4Reg == ARM::SP &&
5799                        Op5.isImm() && !Op5.isImm0_508s4());
5800     }
5801     if (!TryTransform)
5802       return;
5803   } else if (!isThumbOne())
5804     return;
5805
5806   if (!(Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" ||
5807         Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5808         Mnemonic == "asr" || Mnemonic == "adc" || Mnemonic == "sbc" ||
5809         Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic"))
5810     return;
5811
5812   // If first 2 operands of a 3 operand instruction are the same
5813   // then transform to 2 operand version of the same instruction
5814   // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1'
5815   bool Transform = Op3Reg == Op4Reg;
5816
5817   // For communtative operations, we might be able to transform if we swap
5818   // Op4 and Op5.  The 'ADD Rdm, SP, Rdm' form is already handled specially
5819   // as tADDrsp.
5820   const ARMOperand *LastOp = &Op5;
5821   bool Swap = false;
5822   if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() &&
5823       ((Mnemonic == "add" && Op4Reg != ARM::SP) ||
5824        Mnemonic == "and" || Mnemonic == "eor" ||
5825        Mnemonic == "adc" || Mnemonic == "orr")) {
5826     Swap = true;
5827     LastOp = &Op4;
5828     Transform = true;
5829   }
5830
5831   // If both registers are the same then remove one of them from
5832   // the operand list, with certain exceptions.
5833   if (Transform) {
5834     // Don't transform 'adds Rd, Rd, Rm' or 'sub{s} Rd, Rd, Rm' because the
5835     // 2 operand forms don't exist.
5836     if (((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub") &&
5837         LastOp->isReg())
5838       Transform = false;
5839
5840     // Don't transform 'add/sub{s} Rd, Rd, #imm' if the immediate fits into
5841     // 3-bits because the ARMARM says not to.
5842     if ((Mnemonic == "add" || Mnemonic == "sub") && LastOp->isImm0_7())
5843       Transform = false;
5844   }
5845
5846   if (Transform) {
5847     if (Swap)
5848       std::swap(Op4, Op5);
5849     Operands.erase(Operands.begin() + 3);
5850   }
5851 }
5852
5853 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5854                                           OperandVector &Operands) {
5855   // FIXME: This is all horribly hacky. We really need a better way to deal
5856   // with optional operands like this in the matcher table.
5857
5858   // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5859   // another does not. Specifically, the MOVW instruction does not. So we
5860   // special case it here and remove the defaulted (non-setting) cc_out
5861   // operand if that's the instruction we're trying to match.
5862   //
5863   // We do this as post-processing of the explicit operands rather than just
5864   // conditionally adding the cc_out in the first place because we need
5865   // to check the type of the parsed immediate operand.
5866   if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5867       !static_cast<ARMOperand &>(*Operands[4]).isModImm() &&
5868       static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() &&
5869       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5870     return true;
5871
5872   // Register-register 'add' for thumb does not have a cc_out operand
5873   // when there are only two register operands.
5874   if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5875       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5876       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5877       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5878     return true;
5879   // Register-register 'add' for thumb does not have a cc_out operand
5880   // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5881   // have to check the immediate range here since Thumb2 has a variant
5882   // that can handle a different range and has a cc_out operand.
5883   if (((isThumb() && Mnemonic == "add") ||
5884        (isThumbTwo() && Mnemonic == "sub")) &&
5885       Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5886       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5887       static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP &&
5888       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5889       ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) ||
5890        static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4()))
5891     return true;
5892   // For Thumb2, add/sub immediate does not have a cc_out operand for the
5893   // imm0_4095 variant. That's the least-preferred variant when
5894   // selecting via the generic "add" mnemonic, so to know that we
5895   // should remove the cc_out operand, we have to explicitly check that
5896   // it's not one of the other variants. Ugh.
5897   if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5898       Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5899       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5900       static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5901     // Nest conditions rather than one big 'if' statement for readability.
5902     //
5903     // If both registers are low, we're in an IT block, and the immediate is
5904     // in range, we should use encoding T1 instead, which has a cc_out.
5905     if (inITBlock() &&
5906         isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) &&
5907         isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) &&
5908         static_cast<ARMOperand &>(*Operands[5]).isImm0_7())
5909       return false;
5910     // Check against T3. If the second register is the PC, this is an
5911     // alternate form of ADR, which uses encoding T4, so check for that too.
5912     if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
5913         static_cast<ARMOperand &>(*Operands[5]).isT2SOImm())
5914       return false;
5915
5916     // Otherwise, we use encoding T4, which does not have a cc_out
5917     // operand.
5918     return true;
5919   }
5920
5921   // The thumb2 multiply instruction doesn't have a CCOut register, so
5922   // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5923   // use the 16-bit encoding or not.
5924   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5925       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5926       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5927       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5928       static_cast<ARMOperand &>(*Operands[5]).isReg() &&
5929       // If the registers aren't low regs, the destination reg isn't the
5930       // same as one of the source regs, or the cc_out operand is zero
5931       // outside of an IT block, we have to use the 32-bit encoding, so
5932       // remove the cc_out operand.
5933       (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5934        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5935        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) ||
5936        !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5937                             static_cast<ARMOperand &>(*Operands[5]).getReg() &&
5938                         static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5939                             static_cast<ARMOperand &>(*Operands[4]).getReg())))
5940     return true;
5941
5942   // Also check the 'mul' syntax variant that doesn't specify an explicit
5943   // destination register.
5944   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5945       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5946       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5947       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5948       // If the registers aren't low regs  or the cc_out operand is zero
5949       // outside of an IT block, we have to use the 32-bit encoding, so
5950       // remove the cc_out operand.
5951       (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5952        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5953        !inITBlock()))
5954     return true;
5955
5956   // Register-register 'add/sub' for thumb does not have a cc_out operand
5957   // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5958   // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5959   // right, this will result in better diagnostics (which operand is off)
5960   // anyway.
5961   if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5962       (Operands.size() == 5 || Operands.size() == 6) &&
5963       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5964       static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
5965       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5966       (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
5967        (Operands.size() == 6 &&
5968         static_cast<ARMOperand &>(*Operands[5]).isImm())))
5969     return true;
5970
5971   return false;
5972 }
5973
5974 bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
5975                                               OperandVector &Operands) {
5976   // VRINT{Z, X} have a predicate operand in VFP, but not in NEON
5977   unsigned RegIdx = 3;
5978   if ((Mnemonic == "vrintz" || Mnemonic == "vrintx") &&
5979       (static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32" ||
5980        static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f16")) {
5981     if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
5982         (static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32" ||
5983          static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f16"))
5984       RegIdx = 4;
5985
5986     if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
5987         (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
5988              static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
5989          ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
5990              static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
5991       return true;
5992   }
5993   return false;
5994 }
5995
5996 static bool isDataTypeToken(StringRef Tok) {
5997   return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5998     Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5999     Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
6000     Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
6001     Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
6002     Tok == ".f" || Tok == ".d";
6003 }
6004
6005 // FIXME: This bit should probably be handled via an explicit match class
6006 // in the .td files that matches the suffix instead of having it be
6007 // a literal string token the way it is now.
6008 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
6009   return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
6010 }
6011
6012 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
6013                                  unsigned VariantID);
6014
6015 // The GNU assembler has aliases of ldrd and strd with the second register
6016 // omitted. We don't have a way to do that in tablegen, so fix it up here.
6017 //
6018 // We have to be careful to not emit an invalid Rt2 here, because the rest of
6019 // the assmebly parser could then generate confusing diagnostics refering to
6020 // it. If we do find anything that prevents us from doing the transformation we
6021 // bail out, and let the assembly parser report an error on the instruction as
6022 // it is written.
6023 void ARMAsmParser::fixupGNULDRDAlias(StringRef Mnemonic,
6024                                      OperandVector &Operands) {
6025   if (Mnemonic != "ldrd" && Mnemonic != "strd")
6026     return;
6027   if (Operands.size() < 4)
6028     return;
6029
6030   ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
6031   ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
6032
6033   if (!Op2.isReg())
6034     return;
6035   if (!Op3.isMem())
6036     return;
6037
6038   const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID);
6039   if (!GPR.contains(Op2.getReg()))
6040     return;
6041
6042   unsigned RtEncoding = MRI->getEncodingValue(Op2.getReg());
6043   if (!isThumb() && (RtEncoding & 1)) {
6044     // In ARM mode, the registers must be from an aligned pair, this
6045     // restriction does not apply in Thumb mode.
6046     return;
6047   }
6048   if (Op2.getReg() == ARM::PC)
6049     return;
6050   unsigned PairedReg = GPR.getRegister(RtEncoding + 1);
6051   if (!PairedReg || PairedReg == ARM::PC ||
6052       (PairedReg == ARM::SP && !hasV8Ops()))
6053     return;
6054
6055   Operands.insert(
6056       Operands.begin() + 3,
6057       ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
6058 }
6059
6060 /// Parse an arm instruction mnemonic followed by its operands.
6061 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
6062                                     SMLoc NameLoc, OperandVector &Operands) {
6063   MCAsmParser &Parser = getParser();
6064
6065   // Apply mnemonic aliases before doing anything else, as the destination
6066   // mnemonic may include suffices and we want to handle them normally.
6067   // The generic tblgen'erated code does this later, at the start of
6068   // MatchInstructionImpl(), but that's too late for aliases that include
6069   // any sort of suffix.
6070   uint64_t AvailableFeatures = getAvailableFeatures();
6071   unsigned AssemblerDialect = getParser().getAssemblerDialect();
6072   applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
6073
6074   // First check for the ARM-specific .req directive.
6075   if (Parser.getTok().is(AsmToken::Identifier) &&
6076       Parser.getTok().getIdentifier() == ".req") {
6077     parseDirectiveReq(Name, NameLoc);
6078     // We always return 'error' for this, as we're done with this
6079     // statement and don't need to match the 'instruction."
6080     return true;
6081   }
6082
6083   // Create the leading tokens for the mnemonic, split by '.' characters.
6084   size_t Start = 0, Next = Name.find('.');
6085   StringRef Mnemonic = Name.slice(Start, Next);
6086
6087   // Split out the predication code and carry setting flag from the mnemonic.
6088   unsigned PredicationCode;
6089   unsigned ProcessorIMod;
6090   bool CarrySetting;
6091   StringRef ITMask;
6092   Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
6093                            ProcessorIMod, ITMask);
6094
6095   // In Thumb1, only the branch (B) instruction can be predicated.
6096   if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
6097     return Error(NameLoc, "conditional execution not supported in Thumb1");
6098   }
6099
6100   Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
6101
6102   // Handle the IT instruction ITMask. Convert it to a bitmask. This
6103   // is the mask as it will be for the IT encoding if the conditional
6104   // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
6105   // where the conditional bit0 is zero, the instruction post-processing
6106   // will adjust the mask accordingly.
6107   if (Mnemonic == "it") {
6108     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
6109     if (ITMask.size() > 3) {
6110       return Error(Loc, "too many conditions on IT instruction");
6111     }
6112     unsigned Mask = 8;
6113     for (unsigned i = ITMask.size(); i != 0; --i) {
6114       char pos = ITMask[i - 1];
6115       if (pos != 't' && pos != 'e') {
6116         return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
6117       }
6118       Mask >>= 1;
6119       if (ITMask[i - 1] == 't')
6120         Mask |= 8;
6121     }
6122     Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
6123   }
6124
6125   // FIXME: This is all a pretty gross hack. We should automatically handle
6126   // optional operands like this via tblgen.
6127
6128   // Next, add the CCOut and ConditionCode operands, if needed.
6129   //
6130   // For mnemonics which can ever incorporate a carry setting bit or predication
6131   // code, our matching model involves us always generating CCOut and
6132   // ConditionCode operands to match the mnemonic "as written" and then we let
6133   // the matcher deal with finding the right instruction or generating an
6134   // appropriate error.
6135   bool CanAcceptCarrySet, CanAcceptPredicationCode;
6136   getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
6137
6138   // If we had a carry-set on an instruction that can't do that, issue an
6139   // error.
6140   if (!CanAcceptCarrySet && CarrySetting) {
6141     return Error(NameLoc, "instruction '" + Mnemonic +
6142                  "' can not set flags, but 's' suffix specified");
6143   }
6144   // If we had a predication code on an instruction that can't do that, issue an
6145   // error.
6146   if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
6147     return Error(NameLoc, "instruction '" + Mnemonic +
6148                  "' is not predicable, but condition code specified");
6149   }
6150
6151   // Add the carry setting operand, if necessary.
6152   if (CanAcceptCarrySet) {
6153     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
6154     Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
6155                                                Loc));
6156   }
6157
6158   // Add the predication code operand, if necessary.
6159   if (CanAcceptPredicationCode) {
6160     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
6161                                       CarrySetting);
6162     Operands.push_back(ARMOperand::CreateCondCode(
6163                          ARMCC::CondCodes(PredicationCode), Loc));
6164   }
6165
6166   // Add the processor imod operand, if necessary.
6167   if (ProcessorIMod) {
6168     Operands.push_back(ARMOperand::CreateImm(
6169           MCConstantExpr::create(ProcessorIMod, getContext()),
6170                                  NameLoc, NameLoc));
6171   } else if (Mnemonic == "cps" && isMClass()) {
6172     return Error(NameLoc, "instruction 'cps' requires effect for M-class");
6173   }
6174
6175   // Add the remaining tokens in the mnemonic.
6176   while (Next != StringRef::npos) {
6177     Start = Next;
6178     Next = Name.find('.', Start + 1);
6179     StringRef ExtraToken = Name.slice(Start, Next);
6180
6181     // Some NEON instructions have an optional datatype suffix that is
6182     // completely ignored. Check for that.
6183     if (isDataTypeToken(ExtraToken) &&
6184         doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
6185       continue;
6186
6187     // For for ARM mode generate an error if the .n qualifier is used.
6188     if (ExtraToken == ".n" && !isThumb()) {
6189       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
6190       return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
6191                    "arm mode");
6192     }
6193
6194     // The .n qualifier is always discarded as that is what the tables
6195     // and matcher expect.  In ARM mode the .w qualifier has no effect,
6196     // so discard it to avoid errors that can be caused by the matcher.
6197     if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
6198       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
6199       Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
6200     }
6201   }
6202
6203   // Read the remaining operands.
6204   if (getLexer().isNot(AsmToken::EndOfStatement)) {
6205     // Read the first operand.
6206     if (parseOperand(Operands, Mnemonic)) {
6207       return true;
6208     }
6209
6210     while (parseOptionalToken(AsmToken::Comma)) {
6211       // Parse and remember the operand.
6212       if (parseOperand(Operands, Mnemonic)) {
6213         return true;
6214       }
6215     }
6216   }
6217
6218   if (parseToken(AsmToken::EndOfStatement, "unexpected token in argument list"))
6219     return true;
6220
6221   tryConvertingToTwoOperandForm(Mnemonic, CarrySetting, Operands);
6222
6223   // Some instructions, mostly Thumb, have forms for the same mnemonic that
6224   // do and don't have a cc_out optional-def operand. With some spot-checks
6225   // of the operand list, we can figure out which variant we're trying to
6226   // parse and adjust accordingly before actually matching. We shouldn't ever
6227   // try to remove a cc_out operand that was explicitly set on the
6228   // mnemonic, of course (CarrySetting == true). Reason number #317 the
6229   // table driven matcher doesn't fit well with the ARM instruction set.
6230   if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
6231     Operands.erase(Operands.begin() + 1);
6232
6233   // Some instructions have the same mnemonic, but don't always
6234   // have a predicate. Distinguish them here and delete the
6235   // predicate if needed.
6236   if (PredicationCode == ARMCC::AL &&
6237       shouldOmitPredicateOperand(Mnemonic, Operands))
6238     Operands.erase(Operands.begin() + 1);
6239
6240   // ARM mode 'blx' need special handling, as the register operand version
6241   // is predicable, but the label operand version is not. So, we can't rely
6242   // on the Mnemonic based checking to correctly figure out when to put
6243   // a k_CondCode operand in the list. If we're trying to match the label
6244   // version, remove the k_CondCode operand here.
6245   if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
6246       static_cast<ARMOperand &>(*Operands[2]).isImm())
6247     Operands.erase(Operands.begin() + 1);
6248
6249   // Adjust operands of ldrexd/strexd to MCK_GPRPair.
6250   // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
6251   // a single GPRPair reg operand is used in the .td file to replace the two
6252   // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
6253   // expressed as a GPRPair, so we have to manually merge them.
6254   // FIXME: We would really like to be able to tablegen'erate this.
6255   if (!isThumb() && Operands.size() > 4 &&
6256       (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
6257        Mnemonic == "stlexd")) {
6258     bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
6259     unsigned Idx = isLoad ? 2 : 3;
6260     ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
6261     ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
6262
6263     const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
6264     // Adjust only if Op1 and Op2 are GPRs.
6265     if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
6266         MRC.contains(Op2.getReg())) {
6267       unsigned Reg1 = Op1.getReg();
6268       unsigned Reg2 = Op2.getReg();
6269       unsigned Rt = MRI->getEncodingValue(Reg1);
6270       unsigned Rt2 = MRI->getEncodingValue(Reg2);
6271
6272       // Rt2 must be Rt + 1 and Rt must be even.
6273       if (Rt + 1 != Rt2 || (Rt & 1)) {
6274         return Error(Op2.getStartLoc(),
6275                      isLoad ? "destination operands must be sequential"
6276                             : "source operands must be sequential");
6277       }
6278       unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
6279           &(MRI->getRegClass(ARM::GPRPairRegClassID)));
6280       Operands[Idx] =
6281           ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
6282       Operands.erase(Operands.begin() + Idx + 1);
6283     }
6284   }
6285
6286   // GNU Assembler extension (compatibility).
6287   fixupGNULDRDAlias(Mnemonic, Operands);
6288
6289   // FIXME: As said above, this is all a pretty gross hack.  This instruction
6290   // does not fit with other "subs" and tblgen.
6291   // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
6292   // so the Mnemonic is the original name "subs" and delete the predicate
6293   // operand so it will match the table entry.
6294   if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
6295       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6296       static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC &&
6297       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6298       static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
6299       static_cast<ARMOperand &>(*Operands[5]).isImm()) {
6300     Operands.front() = ARMOperand::CreateToken(Name, NameLoc);
6301     Operands.erase(Operands.begin() + 1);
6302   }
6303   return false;
6304 }
6305
6306 // Validate context-sensitive operand constraints.
6307
6308 // return 'true' if register list contains non-low GPR registers,
6309 // 'false' otherwise. If Reg is in the register list or is HiReg, set
6310 // 'containsReg' to true.
6311 static bool checkLowRegisterList(const MCInst &Inst, unsigned OpNo,
6312                                  unsigned Reg, unsigned HiReg,
6313                                  bool &containsReg) {
6314   containsReg = false;
6315   for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
6316     unsigned OpReg = Inst.getOperand(i).getReg();
6317     if (OpReg == Reg)
6318       containsReg = true;
6319     // Anything other than a low register isn't legal here.
6320     if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
6321       return true;
6322   }
6323   return false;
6324 }
6325
6326 // Check if the specified regisgter is in the register list of the inst,
6327 // starting at the indicated operand number.
6328 static bool listContainsReg(const MCInst &Inst, unsigned OpNo, unsigned Reg) {
6329   for (unsigned i = OpNo, e = Inst.getNumOperands(); i < e; ++i) {
6330     unsigned OpReg = Inst.getOperand(i).getReg();
6331     if (OpReg == Reg)
6332       return true;
6333   }
6334   return false;
6335 }
6336
6337 // Return true if instruction has the interesting property of being
6338 // allowed in IT blocks, but not being predicable.
6339 static bool instIsBreakpoint(const MCInst &Inst) {
6340     return Inst.getOpcode() == ARM::tBKPT ||
6341            Inst.getOpcode() == ARM::BKPT ||
6342            Inst.getOpcode() == ARM::tHLT ||
6343            Inst.getOpcode() == ARM::HLT;
6344 }
6345
6346 bool ARMAsmParser::validatetLDMRegList(const MCInst &Inst,
6347                                        const OperandVector &Operands,
6348                                        unsigned ListNo, bool IsARPop) {
6349   const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
6350   bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
6351
6352   bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
6353   bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR);
6354   bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
6355
6356   if (!IsARPop && ListContainsSP)
6357     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6358                  "SP may not be in the register list");
6359   else if (ListContainsPC && ListContainsLR)
6360     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6361                  "PC and LR may not be in the register list simultaneously");
6362   return false;
6363 }
6364
6365 bool ARMAsmParser::validatetSTMRegList(const MCInst &Inst,
6366                                        const OperandVector &Operands,
6367                                        unsigned ListNo) {
6368   const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
6369   bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
6370
6371   bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
6372   bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
6373
6374   if (ListContainsSP && ListContainsPC)
6375     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6376                  "SP and PC may not be in the register list");
6377   else if (ListContainsSP)
6378     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6379                  "SP may not be in the register list");
6380   else if (ListContainsPC)
6381     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6382                  "PC may not be in the register list");
6383   return false;
6384 }
6385
6386 bool ARMAsmParser::validateLDRDSTRD(MCInst &Inst,
6387                                     const OperandVector &Operands,
6388                                     bool Load, bool ARMMode, bool Writeback) {
6389   unsigned RtIndex = Load || !Writeback ? 0 : 1;
6390   unsigned Rt = MRI->getEncodingValue(Inst.getOperand(RtIndex).getReg());
6391   unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(RtIndex + 1).getReg());
6392
6393   if (ARMMode) {
6394     // Rt can't be R14.
6395     if (Rt == 14)
6396       return Error(Operands[3]->getStartLoc(),
6397                   "Rt can't be R14");
6398
6399     // Rt must be even-numbered.
6400     if ((Rt & 1) == 1)
6401       return Error(Operands[3]->getStartLoc(),
6402                    "Rt must be even-numbered");
6403
6404     // Rt2 must be Rt + 1.
6405     if (Rt2 != Rt + 1) {
6406       if (Load)
6407         return Error(Operands[3]->getStartLoc(),
6408                      "destination operands must be sequential");
6409       else
6410         return Error(Operands[3]->getStartLoc(),
6411                      "source operands must be sequential");
6412     }
6413
6414     // FIXME: Diagnose m == 15
6415     // FIXME: Diagnose ldrd with m == t || m == t2.
6416   }
6417
6418   if (!ARMMode && Load) {
6419     if (Rt2 == Rt)
6420       return Error(Operands[3]->getStartLoc(),
6421                    "destination operands can't be identical");
6422   }
6423
6424   if (Writeback) {
6425     unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
6426
6427     if (Rn == Rt || Rn == Rt2) {
6428       if (Load)
6429         return Error(Operands[3]->getStartLoc(),
6430                      "base register needs to be different from destination "
6431                      "registers");
6432       else
6433         return Error(Operands[3]->getStartLoc(),
6434                      "source register and base register can't be identical");
6435     }
6436
6437     // FIXME: Diagnose ldrd/strd with writeback and n == 15.
6438     // (Except the immediate form of ldrd?)
6439   }
6440
6441   return false;
6442 }
6443
6444
6445 // FIXME: We would really like to be able to tablegen'erate this.
6446 bool ARMAsmParser::validateInstruction(MCInst &Inst,
6447                                        const OperandVector &Operands) {
6448   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
6449   SMLoc Loc = Operands[0]->getStartLoc();
6450
6451   // Check the IT block state first.
6452   // NOTE: BKPT and HLT instructions have the interesting property of being
6453   // allowed in IT blocks, but not being predicable. They just always execute.
6454   if (inITBlock() && !instIsBreakpoint(Inst)) {
6455     // The instruction must be predicable.
6456     if (!MCID.isPredicable())
6457       return Error(Loc, "instructions in IT block must be predicable");
6458     ARMCC::CondCodes Cond = ARMCC::CondCodes(
6459         Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm());
6460     if (Cond != currentITCond()) {
6461       // Find the condition code Operand to get its SMLoc information.
6462       SMLoc CondLoc;
6463       for (unsigned I = 1; I < Operands.size(); ++I)
6464         if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
6465           CondLoc = Operands[I]->getStartLoc();
6466       return Error(CondLoc, "incorrect condition in IT block; got '" +
6467                                 StringRef(ARMCondCodeToString(Cond)) +
6468                                 "', but expected '" +
6469                                 ARMCondCodeToString(currentITCond()) + "'");
6470     }
6471   // Check for non-'al' condition codes outside of the IT block.
6472   } else if (isThumbTwo() && MCID.isPredicable() &&
6473              Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
6474              ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
6475              Inst.getOpcode() != ARM::t2Bcc) {
6476     return Error(Loc, "predicated instructions must be in IT block");
6477   } else if (!isThumb() && !useImplicitITARM() && MCID.isPredicable() &&
6478              Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
6479                  ARMCC::AL) {
6480     return Warning(Loc, "predicated instructions should be in IT block");
6481   }
6482
6483   // PC-setting instructions in an IT block, but not the last instruction of
6484   // the block, are UNPREDICTABLE.
6485   if (inExplicitITBlock() && !lastInITBlock() && isITBlockTerminator(Inst)) {
6486     return Error(Loc, "instruction must be outside of IT block or the last instruction in an IT block");
6487   }
6488
6489   const unsigned Opcode = Inst.getOpcode();
6490   switch (Opcode) {
6491   case ARM::t2IT: {
6492     // Encoding is unpredictable if it ever results in a notional 'NV'
6493     // predicate. Since we don't parse 'NV' directly this means an 'AL'
6494     // predicate with an "else" mask bit.
6495     unsigned Cond = Inst.getOperand(0).getImm();
6496     unsigned Mask = Inst.getOperand(1).getImm();
6497
6498     // Mask hasn't been modified to the IT instruction encoding yet so
6499     // conditions only allowing a 't' are a block of 1s starting at bit 3
6500     // followed by all 0s. Easiest way is to just list the 4 possibilities.
6501     if (Cond == ARMCC::AL && Mask != 8 && Mask != 12 && Mask != 14 &&
6502         Mask != 15)
6503       return Error(Loc, "unpredictable IT predicate sequence");
6504     break;
6505   }
6506   case ARM::LDRD:
6507     if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true,
6508                          /*Writeback*/false))
6509       return true;
6510     break;
6511   case ARM::LDRD_PRE:
6512   case ARM::LDRD_POST:
6513     if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true,
6514                          /*Writeback*/true))
6515       return true;
6516     break;
6517   case ARM::t2LDRDi8:
6518     if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false,
6519                          /*Writeback*/false))
6520       return true;
6521     break;
6522   case ARM::t2LDRD_PRE:
6523   case ARM::t2LDRD_POST:
6524     if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false,
6525                          /*Writeback*/true))
6526       return true;
6527     break;
6528   case ARM::t2BXJ: {
6529     const unsigned RmReg = Inst.getOperand(0).getReg();
6530     // Rm = SP is no longer unpredictable in v8-A
6531     if (RmReg == ARM::SP && !hasV8Ops())
6532       return Error(Operands[2]->getStartLoc(),
6533                    "r13 (SP) is an unpredictable operand to BXJ");
6534     return false;
6535   }
6536   case ARM::STRD:
6537     if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true,
6538                          /*Writeback*/false))
6539       return true;
6540     break;
6541   case ARM::STRD_PRE:
6542   case ARM::STRD_POST:
6543     if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true,
6544                          /*Writeback*/true))
6545       return true;
6546     break;
6547   case ARM::t2STRD_PRE:
6548   case ARM::t2STRD_POST:
6549     if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/false,
6550                          /*Writeback*/true))
6551       return true;
6552     break;
6553   case ARM::STR_PRE_IMM:
6554   case ARM::STR_PRE_REG:
6555   case ARM::t2STR_PRE:
6556   case ARM::STR_POST_IMM:
6557   case ARM::STR_POST_REG:
6558   case ARM::t2STR_POST:
6559   case ARM::STRH_PRE:
6560   case ARM::t2STRH_PRE:
6561   case ARM::STRH_POST:
6562   case ARM::t2STRH_POST:
6563   case ARM::STRB_PRE_IMM:
6564   case ARM::STRB_PRE_REG:
6565   case ARM::t2STRB_PRE:
6566   case ARM::STRB_POST_IMM:
6567   case ARM::STRB_POST_REG:
6568   case ARM::t2STRB_POST: {
6569     // Rt must be different from Rn.
6570     const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6571     const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6572
6573     if (Rt == Rn)
6574       return Error(Operands[3]->getStartLoc(),
6575                    "source register and base register can't be identical");
6576     return false;
6577   }
6578   case ARM::LDR_PRE_IMM:
6579   case ARM::LDR_PRE_REG:
6580   case ARM::t2LDR_PRE:
6581   case ARM::LDR_POST_IMM:
6582   case ARM::LDR_POST_REG:
6583   case ARM::t2LDR_POST:
6584   case ARM::LDRH_PRE:
6585   case ARM::t2LDRH_PRE:
6586   case ARM::LDRH_POST:
6587   case ARM::t2LDRH_POST:
6588   case ARM::LDRSH_PRE:
6589   case ARM::t2LDRSH_PRE:
6590   case ARM::LDRSH_POST:
6591   case ARM::t2LDRSH_POST:
6592   case ARM::LDRB_PRE_IMM:
6593   case ARM::LDRB_PRE_REG:
6594   case ARM::t2LDRB_PRE:
6595   case ARM::LDRB_POST_IMM:
6596   case ARM::LDRB_POST_REG:
6597   case ARM::t2LDRB_POST:
6598   case ARM::LDRSB_PRE:
6599   case ARM::t2LDRSB_PRE:
6600   case ARM::LDRSB_POST:
6601   case ARM::t2LDRSB_POST: {
6602     // Rt must be different from Rn.
6603     const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6604     const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6605
6606     if (Rt == Rn)
6607       return Error(Operands[3]->getStartLoc(),
6608                    "destination register and base register can't be identical");
6609     return false;
6610   }
6611   case ARM::SBFX:
6612   case ARM::t2SBFX:
6613   case ARM::UBFX:
6614   case ARM::t2UBFX: {
6615     // Width must be in range [1, 32-lsb].
6616     unsigned LSB = Inst.getOperand(2).getImm();
6617     unsigned Widthm1 = Inst.getOperand(3).getImm();
6618     if (Widthm1 >= 32 - LSB)
6619       return Error(Operands[5]->getStartLoc(),
6620                    "bitfield width must be in range [1,32-lsb]");
6621     return false;
6622   }
6623   // Notionally handles ARM::tLDMIA_UPD too.
6624   case ARM::tLDMIA: {
6625     // If we're parsing Thumb2, the .w variant is available and handles
6626     // most cases that are normally illegal for a Thumb1 LDM instruction.
6627     // We'll make the transformation in processInstruction() if necessary.
6628     //
6629     // Thumb LDM instructions are writeback iff the base register is not
6630     // in the register list.
6631     unsigned Rn = Inst.getOperand(0).getReg();
6632     bool HasWritebackToken =
6633         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
6634          static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
6635     bool ListContainsBase;
6636     if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
6637       return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
6638                    "registers must be in range r0-r7");
6639     // If we should have writeback, then there should be a '!' token.
6640     if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
6641       return Error(Operands[2]->getStartLoc(),
6642                    "writeback operator '!' expected");
6643     // If we should not have writeback, there must not be a '!'. This is
6644     // true even for the 32-bit wide encodings.
6645     if (ListContainsBase && HasWritebackToken)
6646       return Error(Operands[3]->getStartLoc(),
6647                    "writeback operator '!' not allowed when base register "
6648                    "in register list");
6649
6650     if (validatetLDMRegList(Inst, Operands, 3))
6651       return true;
6652     break;
6653   }
6654   case ARM::LDMIA_UPD:
6655   case ARM::LDMDB_UPD:
6656   case ARM::LDMIB_UPD:
6657   case ARM::LDMDA_UPD:
6658     // ARM variants loading and updating the same register are only officially
6659     // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
6660     if (!hasV7Ops())
6661       break;
6662     if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6663       return Error(Operands.back()->getStartLoc(),
6664                    "writeback register not allowed in register list");
6665     break;
6666   case ARM::t2LDMIA:
6667   case ARM::t2LDMDB:
6668     if (validatetLDMRegList(Inst, Operands, 3))
6669       return true;
6670     break;
6671   case ARM::t2STMIA:
6672   case ARM::t2STMDB:
6673     if (validatetSTMRegList(Inst, Operands, 3))
6674       return true;
6675     break;
6676   case ARM::t2LDMIA_UPD:
6677   case ARM::t2LDMDB_UPD:
6678   case ARM::t2STMIA_UPD:
6679   case ARM::t2STMDB_UPD:
6680     if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6681       return Error(Operands.back()->getStartLoc(),
6682                    "writeback register not allowed in register list");
6683
6684     if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {
6685       if (validatetLDMRegList(Inst, Operands, 3))
6686         return true;
6687     } else {
6688       if (validatetSTMRegList(Inst, Operands, 3))
6689         return true;
6690     }
6691     break;
6692
6693   case ARM::sysLDMIA_UPD:
6694   case ARM::sysLDMDA_UPD:
6695   case ARM::sysLDMDB_UPD:
6696   case ARM::sysLDMIB_UPD:
6697     if (!listContainsReg(Inst, 3, ARM::PC))
6698       return Error(Operands[4]->getStartLoc(),
6699                    "writeback register only allowed on system LDM "
6700                    "if PC in register-list");
6701     break;
6702   case ARM::sysSTMIA_UPD:
6703   case ARM::sysSTMDA_UPD:
6704   case ARM::sysSTMDB_UPD:
6705   case ARM::sysSTMIB_UPD:
6706     return Error(Operands[2]->getStartLoc(),
6707                  "system STM cannot have writeback register");
6708   case ARM::tMUL:
6709     // The second source operand must be the same register as the destination
6710     // operand.
6711     //
6712     // In this case, we must directly check the parsed operands because the
6713     // cvtThumbMultiply() function is written in such a way that it guarantees
6714     // this first statement is always true for the new Inst.  Essentially, the
6715     // destination is unconditionally copied into the second source operand
6716     // without checking to see if it matches what we actually parsed.
6717     if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() !=
6718                                  ((ARMOperand &)*Operands[5]).getReg()) &&
6719         (((ARMOperand &)*Operands[3]).getReg() !=
6720          ((ARMOperand &)*Operands[4]).getReg())) {
6721       return Error(Operands[3]->getStartLoc(),
6722                    "destination register must match source register");
6723     }
6724     break;
6725
6726   // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
6727   // so only issue a diagnostic for thumb1. The instructions will be
6728   // switched to the t2 encodings in processInstruction() if necessary.
6729   case ARM::tPOP: {
6730     bool ListContainsBase;
6731     if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
6732         !isThumbTwo())
6733       return Error(Operands[2]->getStartLoc(),
6734                    "registers must be in range r0-r7 or pc");
6735     if (validatetLDMRegList(Inst, Operands, 2, !isMClass()))
6736       return true;
6737     break;
6738   }
6739   case ARM::tPUSH: {
6740     bool ListContainsBase;
6741     if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
6742         !isThumbTwo())
6743       return Error(Operands[2]->getStartLoc(),
6744                    "registers must be in range r0-r7 or lr");
6745     if (validatetSTMRegList(Inst, Operands, 2))
6746       return true;
6747     break;
6748   }
6749   case ARM::tSTMIA_UPD: {
6750     bool ListContainsBase, InvalidLowList;
6751     InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
6752                                           0, ListContainsBase);
6753     if (InvalidLowList && !isThumbTwo())
6754       return Error(Operands[4]->getStartLoc(),
6755                    "registers must be in range r0-r7");
6756
6757     // This would be converted to a 32-bit stm, but that's not valid if the
6758     // writeback register is in the list.
6759     if (InvalidLowList && ListContainsBase)
6760       return Error(Operands[4]->getStartLoc(),
6761                    "writeback operator '!' not allowed when base register "
6762                    "in register list");
6763
6764     if (validatetSTMRegList(Inst, Operands, 4))
6765       return true;
6766     break;
6767   }
6768   case ARM::tADDrSP:
6769     // If the non-SP source operand and the destination operand are not the
6770     // same, we need thumb2 (for the wide encoding), or we have an error.
6771     if (!isThumbTwo() &&
6772         Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
6773       return Error(Operands[4]->getStartLoc(),
6774                    "source register must be the same as destination");
6775     }
6776     break;
6777
6778   // Final range checking for Thumb unconditional branch instructions.
6779   case ARM::tB:
6780     if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
6781       return Error(Operands[2]->getStartLoc(), "branch target out of range");
6782     break;
6783   case ARM::t2B: {
6784     int op = (Operands[2]->isImm()) ? 2 : 3;
6785     if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>())
6786       return Error(Operands[op]->getStartLoc(), "branch target out of range");
6787     break;
6788   }
6789   // Final range checking for Thumb conditional branch instructions.
6790   case ARM::tBcc:
6791     if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>())
6792       return Error(Operands[2]->getStartLoc(), "branch target out of range");
6793     break;
6794   case ARM::t2Bcc: {
6795     int Op = (Operands[2]->isImm()) ? 2 : 3;
6796     if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
6797       return Error(Operands[Op]->getStartLoc(), "branch target out of range");
6798     break;
6799   }
6800   case ARM::tCBZ:
6801   case ARM::tCBNZ: {
6802     if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<6, 1>())
6803       return Error(Operands[2]->getStartLoc(), "branch target out of range");
6804     break;
6805   }
6806   case ARM::MOVi16:
6807   case ARM::MOVTi16:
6808   case ARM::t2MOVi16:
6809   case ARM::t2MOVTi16:
6810     {
6811     // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
6812     // especially when we turn it into a movw and the expression <symbol> does
6813     // not have a :lower16: or :upper16 as part of the expression.  We don't
6814     // want the behavior of silently truncating, which can be unexpected and
6815     // lead to bugs that are difficult to find since this is an easy mistake
6816     // to make.
6817     int i = (Operands[3]->isImm()) ? 3 : 4;
6818     ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
6819     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
6820     if (CE) break;
6821     const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
6822     if (!E) break;
6823     const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
6824     if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
6825                        ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
6826       return Error(
6827           Op.getStartLoc(),
6828           "immediate expression for mov requires :lower16: or :upper16");
6829     break;
6830   }
6831   case ARM::HINT:
6832   case ARM::t2HINT: {
6833     unsigned Imm8 = Inst.getOperand(0).getImm();
6834     unsigned Pred = Inst.getOperand(1).getImm();
6835     // ESB is not predicable (pred must be AL). Without the RAS extension, this
6836     // behaves as any other unallocated hint.
6837     if (Imm8 == 0x10 && Pred != ARMCC::AL && hasRAS())
6838       return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not "
6839                                                "predicable, but condition "
6840                                                "code specified");
6841     if (Imm8 == 0x14 && Pred != ARMCC::AL)
6842       return Error(Operands[1]->getStartLoc(), "instruction 'csdb' is not "
6843                                                "predicable, but condition "
6844                                                "code specified");
6845     break;
6846   }
6847   case ARM::DSB:
6848   case ARM::t2DSB: {
6849
6850     if (Inst.getNumOperands() < 2)
6851       break;
6852
6853     unsigned Option = Inst.getOperand(0).getImm();
6854     unsigned Pred = Inst.getOperand(1).getImm();
6855
6856     // SSBB and PSSBB (DSB #0|#4) are not predicable (pred must be AL).
6857     if (Option == 0 && Pred != ARMCC::AL)
6858       return Error(Operands[1]->getStartLoc(),
6859                    "instruction 'ssbb' is not predicable, but condition code "
6860                    "specified");
6861     if (Option == 4 && Pred != ARMCC::AL)
6862       return Error(Operands[1]->getStartLoc(),
6863                    "instruction 'pssbb' is not predicable, but condition code "
6864                    "specified");
6865     break;
6866   }
6867   case ARM::VMOVRRS: {
6868     // Source registers must be sequential.
6869     const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6870     const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(3).getReg());
6871     if (Sm1 != Sm + 1)
6872       return Error(Operands[5]->getStartLoc(),
6873                    "source operands must be sequential");
6874     break;
6875   }
6876   case ARM::VMOVSRR: {
6877     // Destination registers must be sequential.
6878     const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6879     const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6880     if (Sm1 != Sm + 1)
6881       return Error(Operands[3]->getStartLoc(),
6882                    "destination operands must be sequential");
6883     break;
6884   }
6885   case ARM::VLDMDIA:
6886   case ARM::VSTMDIA: {
6887     ARMOperand &Op = static_cast<ARMOperand&>(*Operands[3]);
6888     auto &RegList = Op.getRegList();
6889     if (RegList.size() < 1 || RegList.size() > 16)
6890       return Error(Operands[3]->getStartLoc(),
6891                    "list of registers must be at least 1 and at most 16");
6892     break;
6893   }
6894   }
6895
6896   return false;
6897 }
6898
6899 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
6900   switch(Opc) {
6901   default: llvm_unreachable("unexpected opcode!");
6902   // VST1LN
6903   case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
6904   case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6905   case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6906   case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
6907   case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6908   case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6909   case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
6910   case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
6911   case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
6912
6913   // VST2LN
6914   case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
6915   case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6916   case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6917   case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6918   case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6919
6920   case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
6921   case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6922   case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6923   case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6924   case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6925
6926   case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
6927   case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
6928   case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
6929   case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
6930   case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
6931
6932   // VST3LN
6933   case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
6934   case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6935   case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6936   case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
6937   case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6938   case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
6939   case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6940   case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6941   case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
6942   case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6943   case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
6944   case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
6945   case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
6946   case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
6947   case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
6948
6949   // VST3
6950   case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
6951   case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6952   case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6953   case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
6954   case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6955   case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6956   case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
6957   case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6958   case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6959   case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
6960   case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6961   case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6962   case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
6963   case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
6964   case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
6965   case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
6966   case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
6967   case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
6968
6969   // VST4LN
6970   case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
6971   case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6972   case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6973   case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
6974   case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6975   case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
6976   case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6977   case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6978   case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
6979   case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6980   case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
6981   case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
6982   case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
6983   case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
6984   case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
6985
6986   // VST4
6987   case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
6988   case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6989   case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6990   case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
6991   case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6992   case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6993   case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
6994   case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6995   case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6996   case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
6997   case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6998   case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6999   case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
7000   case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
7001   case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
7002   case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
7003   case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
7004   case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
7005   }
7006 }
7007
7008 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
7009   switch(Opc) {
7010   default: llvm_unreachable("unexpected opcode!");
7011   // VLD1LN
7012   case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
7013   case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
7014   case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
7015   case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
7016   case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
7017   case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
7018   case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
7019   case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
7020   case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
7021
7022   // VLD2LN
7023   case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
7024   case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
7025   case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
7026   case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
7027   case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
7028   case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
7029   case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
7030   case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
7031   case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
7032   case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
7033   case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
7034   case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
7035   case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
7036   case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
7037   case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
7038
7039   // VLD3DUP
7040   case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
7041   case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
7042   case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
7043   case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
7044   case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
7045   case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
7046   case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
7047   case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
7048   case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
7049   case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
7050   case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
7051   case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
7052   case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
7053   case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
7054   case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
7055   case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
7056   case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
7057   case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
7058
7059   // VLD3LN
7060   case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
7061   case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
7062   case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
7063   case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
7064   case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
7065   case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
7066   case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
7067   case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
7068   case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
7069   case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
7070   case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
7071   case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
7072   case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
7073   case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
7074   case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
7075
7076   // VLD3
7077   case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
7078   case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
7079   case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
7080   case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
7081   case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
7082   case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
7083   case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
7084   case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
7085   case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
7086   case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
7087   case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
7088   case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
7089   case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
7090   case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
7091   case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
7092   case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
7093   case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
7094   case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
7095
7096   // VLD4LN
7097   case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
7098   case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
7099   case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
7100   case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
7101   case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
7102   case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
7103   case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
7104   case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
7105   case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
7106   case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
7107   case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
7108   case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
7109   case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
7110   case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
7111   case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
7112
7113   // VLD4DUP
7114   case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
7115   case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
7116   case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
7117   case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
7118   case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
7119   case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
7120   case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
7121   case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
7122   case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
7123   case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
7124   case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
7125   case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
7126   case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
7127   case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
7128   case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
7129   case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
7130   case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
7131   case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
7132
7133   // VLD4
7134   case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
7135   case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
7136   case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
7137   case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
7138   case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
7139   case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
7140   case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
7141   case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
7142   case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
7143   case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
7144   case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
7145   case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
7146   case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
7147   case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
7148   case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
7149   case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
7150   case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
7151   case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
7152   }
7153 }
7154
7155 bool ARMAsmParser::processInstruction(MCInst &Inst,
7156                                       const OperandVector &Operands,
7157                                       MCStreamer &Out) {
7158   // Check if we have the wide qualifier, because if it's present we
7159   // must avoid selecting a 16-bit thumb instruction.
7160   bool HasWideQualifier = false;
7161   for (auto &Op : Operands) {
7162     ARMOperand &ARMOp = static_cast<ARMOperand&>(*Op);
7163     if (ARMOp.isToken() && ARMOp.getToken() == ".w") {
7164       HasWideQualifier = true;
7165       break;
7166     }
7167   }
7168
7169   switch (Inst.getOpcode()) {
7170   // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
7171   case ARM::LDRT_POST:
7172   case ARM::LDRBT_POST: {
7173     const unsigned Opcode =
7174       (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
7175                                            : ARM::LDRBT_POST_IMM;
7176     MCInst TmpInst;
7177     TmpInst.setOpcode(Opcode);
7178     TmpInst.addOperand(Inst.getOperand(0));
7179     TmpInst.addOperand(Inst.getOperand(1));
7180     TmpInst.addOperand(Inst.getOperand(1));
7181     TmpInst.addOperand(MCOperand::createReg(0));
7182     TmpInst.addOperand(MCOperand::createImm(0));
7183     TmpInst.addOperand(Inst.getOperand(2));
7184     TmpInst.addOperand(Inst.getOperand(3));
7185     Inst = TmpInst;
7186     return true;
7187   }
7188   // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
7189   case ARM::STRT_POST:
7190   case ARM::STRBT_POST: {
7191     const unsigned Opcode =
7192       (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
7193                                            : ARM::STRBT_POST_IMM;
7194     MCInst TmpInst;
7195     TmpInst.setOpcode(Opcode);
7196     TmpInst.addOperand(Inst.getOperand(1));
7197     TmpInst.addOperand(Inst.getOperand(0));
7198     TmpInst.addOperand(Inst.getOperand(1));
7199     TmpInst.addOperand(MCOperand::createReg(0));
7200     TmpInst.addOperand(MCOperand::createImm(0));
7201     TmpInst.addOperand(Inst.getOperand(2));
7202     TmpInst.addOperand(Inst.getOperand(3));
7203     Inst = TmpInst;
7204     return true;
7205   }
7206   // Alias for alternate form of 'ADR Rd, #imm' instruction.
7207   case ARM::ADDri: {
7208     if (Inst.getOperand(1).getReg() != ARM::PC ||
7209         Inst.getOperand(5).getReg() != 0 ||
7210         !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm()))
7211       return false;
7212     MCInst TmpInst;
7213     TmpInst.setOpcode(ARM::ADR);
7214     TmpInst.addOperand(Inst.getOperand(0));
7215     if (Inst.getOperand(2).isImm()) {
7216       // Immediate (mod_imm) will be in its encoded form, we must unencode it
7217       // before passing it to the ADR instruction.
7218       unsigned Enc = Inst.getOperand(2).getImm();
7219       TmpInst.addOperand(MCOperand::createImm(
7220         ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7)));
7221     } else {
7222       // Turn PC-relative expression into absolute expression.
7223       // Reading PC provides the start of the current instruction + 8 and
7224       // the transform to adr is biased by that.
7225       MCSymbol *Dot = getContext().createTempSymbol();
7226       Out.EmitLabel(Dot);
7227       const MCExpr *OpExpr = Inst.getOperand(2).getExpr();
7228       const MCExpr *InstPC = MCSymbolRefExpr::create(Dot,
7229                                                      MCSymbolRefExpr::VK_None,
7230                                                      getContext());
7231       const MCExpr *Const8 = MCConstantExpr::create(8, getContext());
7232       const MCExpr *ReadPC = MCBinaryExpr::createAdd(InstPC, Const8,
7233                                                      getContext());
7234       const MCExpr *FixupAddr = MCBinaryExpr::createAdd(ReadPC, OpExpr,
7235                                                         getContext());
7236       TmpInst.addOperand(MCOperand::createExpr(FixupAddr));
7237     }
7238     TmpInst.addOperand(Inst.getOperand(3));
7239     TmpInst.addOperand(Inst.getOperand(4));
7240     Inst = TmpInst;
7241     return true;
7242   }
7243   // Aliases for alternate PC+imm syntax of LDR instructions.
7244   case ARM::t2LDRpcrel:
7245     // Select the narrow version if the immediate will fit.
7246     if (Inst.getOperand(1).getImm() > 0 &&
7247         Inst.getOperand(1).getImm() <= 0xff &&
7248         !HasWideQualifier)
7249       Inst.setOpcode(ARM::tLDRpci);
7250     else
7251       Inst.setOpcode(ARM::t2LDRpci);
7252     return true;
7253   case ARM::t2LDRBpcrel:
7254     Inst.setOpcode(ARM::t2LDRBpci);
7255     return true;
7256   case ARM::t2LDRHpcrel:
7257     Inst.setOpcode(ARM::t2LDRHpci);
7258     return true;
7259   case ARM::t2LDRSBpcrel:
7260     Inst.setOpcode(ARM::t2LDRSBpci);
7261     return true;
7262   case ARM::t2LDRSHpcrel:
7263     Inst.setOpcode(ARM::t2LDRSHpci);
7264     return true;
7265   case ARM::LDRConstPool:
7266   case ARM::tLDRConstPool:
7267   case ARM::t2LDRConstPool: {
7268     // Pseudo instruction ldr rt, =immediate is converted to a
7269     // MOV rt, immediate if immediate is known and representable
7270     // otherwise we create a constant pool entry that we load from.
7271     MCInst TmpInst;
7272     if (Inst.getOpcode() == ARM::LDRConstPool)
7273       TmpInst.setOpcode(ARM::LDRi12);
7274     else if (Inst.getOpcode() == ARM::tLDRConstPool)
7275       TmpInst.setOpcode(ARM::tLDRpci);
7276     else if (Inst.getOpcode() == ARM::t2LDRConstPool)
7277       TmpInst.setOpcode(ARM::t2LDRpci);
7278     const ARMOperand &PoolOperand =
7279       (HasWideQualifier ?
7280        static_cast<ARMOperand &>(*Operands[4]) :
7281        static_cast<ARMOperand &>(*Operands[3]));
7282     const MCExpr *SubExprVal = PoolOperand.getConstantPoolImm();
7283     // If SubExprVal is a constant we may be able to use a MOV
7284     if (isa<MCConstantExpr>(SubExprVal) &&
7285         Inst.getOperand(0).getReg() != ARM::PC &&
7286         Inst.getOperand(0).getReg() != ARM::SP) {
7287       int64_t Value =
7288         (int64_t) (cast<MCConstantExpr>(SubExprVal))->getValue();
7289       bool UseMov  = true;
7290       bool MovHasS = true;
7291       if (Inst.getOpcode() == ARM::LDRConstPool) {
7292         // ARM Constant
7293         if (ARM_AM::getSOImmVal(Value) != -1) {
7294           Value = ARM_AM::getSOImmVal(Value);
7295           TmpInst.setOpcode(ARM::MOVi);
7296         }
7297         else if (ARM_AM::getSOImmVal(~Value) != -1) {
7298           Value = ARM_AM::getSOImmVal(~Value);
7299           TmpInst.setOpcode(ARM::MVNi);
7300         }
7301         else if (hasV6T2Ops() &&
7302                  Value >=0 && Value < 65536) {
7303           TmpInst.setOpcode(ARM::MOVi16);
7304           MovHasS = false;
7305         }
7306         else
7307           UseMov = false;
7308       }
7309       else {
7310         // Thumb/Thumb2 Constant
7311         if (hasThumb2() &&
7312             ARM_AM::getT2SOImmVal(Value) != -1)
7313           TmpInst.setOpcode(ARM::t2MOVi);
7314         else if (hasThumb2() &&
7315                  ARM_AM::getT2SOImmVal(~Value) != -1) {
7316           TmpInst.setOpcode(ARM::t2MVNi);
7317           Value = ~Value;
7318         }
7319         else if (hasV8MBaseline() &&
7320                  Value >=0 && Value < 65536) {
7321           TmpInst.setOpcode(ARM::t2MOVi16);
7322           MovHasS = false;
7323         }
7324         else
7325           UseMov = false;
7326       }
7327       if (UseMov) {
7328         TmpInst.addOperand(Inst.getOperand(0));           // Rt
7329         TmpInst.addOperand(MCOperand::createImm(Value));  // Immediate
7330         TmpInst.addOperand(Inst.getOperand(2));           // CondCode
7331         TmpInst.addOperand(Inst.getOperand(3));           // CondCode
7332         if (MovHasS)
7333           TmpInst.addOperand(MCOperand::createReg(0));    // S
7334         Inst = TmpInst;
7335         return true;
7336       }
7337     }
7338     // No opportunity to use MOV/MVN create constant pool
7339     const MCExpr *CPLoc =
7340       getTargetStreamer().addConstantPoolEntry(SubExprVal,
7341                                                PoolOperand.getStartLoc());
7342     TmpInst.addOperand(Inst.getOperand(0));           // Rt
7343     TmpInst.addOperand(MCOperand::createExpr(CPLoc)); // offset to constpool
7344     if (TmpInst.getOpcode() == ARM::LDRi12)
7345       TmpInst.addOperand(MCOperand::createImm(0));    // unused offset
7346     TmpInst.addOperand(Inst.getOperand(2));           // CondCode
7347     TmpInst.addOperand(Inst.getOperand(3));           // CondCode
7348     Inst = TmpInst;
7349     return true;
7350   }
7351   // Handle NEON VST complex aliases.
7352   case ARM::VST1LNdWB_register_Asm_8:
7353   case ARM::VST1LNdWB_register_Asm_16:
7354   case ARM::VST1LNdWB_register_Asm_32: {
7355     MCInst TmpInst;
7356     // Shuffle the operands around so the lane index operand is in the
7357     // right place.
7358     unsigned Spacing;
7359     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7360     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7361     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7362     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7363     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7364     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7365     TmpInst.addOperand(Inst.getOperand(1)); // lane
7366     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7367     TmpInst.addOperand(Inst.getOperand(6));
7368     Inst = TmpInst;
7369     return true;
7370   }
7371
7372   case ARM::VST2LNdWB_register_Asm_8:
7373   case ARM::VST2LNdWB_register_Asm_16:
7374   case ARM::VST2LNdWB_register_Asm_32:
7375   case ARM::VST2LNqWB_register_Asm_16:
7376   case ARM::VST2LNqWB_register_Asm_32: {
7377     MCInst TmpInst;
7378     // Shuffle the operands around so the lane index operand is in the
7379     // right place.
7380     unsigned Spacing;
7381     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7382     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7383     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7384     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7385     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7386     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7387     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7388                                             Spacing));
7389     TmpInst.addOperand(Inst.getOperand(1)); // lane
7390     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7391     TmpInst.addOperand(Inst.getOperand(6));
7392     Inst = TmpInst;
7393     return true;
7394   }
7395
7396   case ARM::VST3LNdWB_register_Asm_8:
7397   case ARM::VST3LNdWB_register_Asm_16:
7398   case ARM::VST3LNdWB_register_Asm_32:
7399   case ARM::VST3LNqWB_register_Asm_16:
7400   case ARM::VST3LNqWB_register_Asm_32: {
7401     MCInst TmpInst;
7402     // Shuffle the operands around so the lane index operand is in the
7403     // right place.
7404     unsigned Spacing;
7405     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7406     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7407     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7408     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7409     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7410     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7411     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7412                                             Spacing));
7413     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7414                                             Spacing * 2));
7415     TmpInst.addOperand(Inst.getOperand(1)); // lane
7416     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7417     TmpInst.addOperand(Inst.getOperand(6));
7418     Inst = TmpInst;
7419     return true;
7420   }
7421
7422   case ARM::VST4LNdWB_register_Asm_8:
7423   case ARM::VST4LNdWB_register_Asm_16:
7424   case ARM::VST4LNdWB_register_Asm_32:
7425   case ARM::VST4LNqWB_register_Asm_16:
7426   case ARM::VST4LNqWB_register_Asm_32: {
7427     MCInst TmpInst;
7428     // Shuffle the operands around so the lane index operand is in the
7429     // right place.
7430     unsigned Spacing;
7431     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7432     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7433     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7434     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7435     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7436     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7437     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7438                                             Spacing));
7439     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7440                                             Spacing * 2));
7441     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7442                                             Spacing * 3));
7443     TmpInst.addOperand(Inst.getOperand(1)); // lane
7444     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7445     TmpInst.addOperand(Inst.getOperand(6));
7446     Inst = TmpInst;
7447     return true;
7448   }
7449
7450   case ARM::VST1LNdWB_fixed_Asm_8:
7451   case ARM::VST1LNdWB_fixed_Asm_16:
7452   case ARM::VST1LNdWB_fixed_Asm_32: {
7453     MCInst TmpInst;
7454     // Shuffle the operands around so the lane index operand is in the
7455     // right place.
7456     unsigned Spacing;
7457     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7458     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7459     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7460     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7461     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7462     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7463     TmpInst.addOperand(Inst.getOperand(1)); // lane
7464     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7465     TmpInst.addOperand(Inst.getOperand(5));
7466     Inst = TmpInst;
7467     return true;
7468   }
7469
7470   case ARM::VST2LNdWB_fixed_Asm_8:
7471   case ARM::VST2LNdWB_fixed_Asm_16:
7472   case ARM::VST2LNdWB_fixed_Asm_32:
7473   case ARM::VST2LNqWB_fixed_Asm_16:
7474   case ARM::VST2LNqWB_fixed_Asm_32: {
7475     MCInst TmpInst;
7476     // Shuffle the operands around so the lane index operand is in the
7477     // right place.
7478     unsigned Spacing;
7479     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7480     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7481     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7482     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7483     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7484     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7485     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7486                                             Spacing));
7487     TmpInst.addOperand(Inst.getOperand(1)); // lane
7488     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7489     TmpInst.addOperand(Inst.getOperand(5));
7490     Inst = TmpInst;
7491     return true;
7492   }
7493
7494   case ARM::VST3LNdWB_fixed_Asm_8:
7495   case ARM::VST3LNdWB_fixed_Asm_16:
7496   case ARM::VST3LNdWB_fixed_Asm_32:
7497   case ARM::VST3LNqWB_fixed_Asm_16:
7498   case ARM::VST3LNqWB_fixed_Asm_32: {
7499     MCInst TmpInst;
7500     // Shuffle the operands around so the lane index operand is in the
7501     // right place.
7502     unsigned Spacing;
7503     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7504     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7505     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7506     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7507     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7508     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7509     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7510                                             Spacing));
7511     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7512                                             Spacing * 2));
7513     TmpInst.addOperand(Inst.getOperand(1)); // lane
7514     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7515     TmpInst.addOperand(Inst.getOperand(5));
7516     Inst = TmpInst;
7517     return true;
7518   }
7519
7520   case ARM::VST4LNdWB_fixed_Asm_8:
7521   case ARM::VST4LNdWB_fixed_Asm_16:
7522   case ARM::VST4LNdWB_fixed_Asm_32:
7523   case ARM::VST4LNqWB_fixed_Asm_16:
7524   case ARM::VST4LNqWB_fixed_Asm_32: {
7525     MCInst TmpInst;
7526     // Shuffle the operands around so the lane index operand is in the
7527     // right place.
7528     unsigned Spacing;
7529     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7530     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7531     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7532     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7533     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7534     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7535     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7536                                             Spacing));
7537     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7538                                             Spacing * 2));
7539     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7540                                             Spacing * 3));
7541     TmpInst.addOperand(Inst.getOperand(1)); // lane
7542     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7543     TmpInst.addOperand(Inst.getOperand(5));
7544     Inst = TmpInst;
7545     return true;
7546   }
7547
7548   case ARM::VST1LNdAsm_8:
7549   case ARM::VST1LNdAsm_16:
7550   case ARM::VST1LNdAsm_32: {
7551     MCInst TmpInst;
7552     // Shuffle the operands around so the lane index operand is in the
7553     // right place.
7554     unsigned Spacing;
7555     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7556     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7557     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7558     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7559     TmpInst.addOperand(Inst.getOperand(1)); // lane
7560     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7561     TmpInst.addOperand(Inst.getOperand(5));
7562     Inst = TmpInst;
7563     return true;
7564   }
7565
7566   case ARM::VST2LNdAsm_8:
7567   case ARM::VST2LNdAsm_16:
7568   case ARM::VST2LNdAsm_32:
7569   case ARM::VST2LNqAsm_16:
7570   case ARM::VST2LNqAsm_32: {
7571     MCInst TmpInst;
7572     // Shuffle the operands around so the lane index operand is in the
7573     // right place.
7574     unsigned Spacing;
7575     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7576     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7577     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7578     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7579     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7580                                             Spacing));
7581     TmpInst.addOperand(Inst.getOperand(1)); // lane
7582     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7583     TmpInst.addOperand(Inst.getOperand(5));
7584     Inst = TmpInst;
7585     return true;
7586   }
7587
7588   case ARM::VST3LNdAsm_8:
7589   case ARM::VST3LNdAsm_16:
7590   case ARM::VST3LNdAsm_32:
7591   case ARM::VST3LNqAsm_16:
7592   case ARM::VST3LNqAsm_32: {
7593     MCInst TmpInst;
7594     // Shuffle the operands around so the lane index operand is in the
7595     // right place.
7596     unsigned Spacing;
7597     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7598     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7599     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7600     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7601     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7602                                             Spacing));
7603     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7604                                             Spacing * 2));
7605     TmpInst.addOperand(Inst.getOperand(1)); // lane
7606     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7607     TmpInst.addOperand(Inst.getOperand(5));
7608     Inst = TmpInst;
7609     return true;
7610   }
7611
7612   case ARM::VST4LNdAsm_8:
7613   case ARM::VST4LNdAsm_16:
7614   case ARM::VST4LNdAsm_32:
7615   case ARM::VST4LNqAsm_16:
7616   case ARM::VST4LNqAsm_32: {
7617     MCInst TmpInst;
7618     // Shuffle the operands around so the lane index operand is in the
7619     // right place.
7620     unsigned Spacing;
7621     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7622     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7623     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7624     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7625     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7626                                             Spacing));
7627     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7628                                             Spacing * 2));
7629     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7630                                             Spacing * 3));
7631     TmpInst.addOperand(Inst.getOperand(1)); // lane
7632     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7633     TmpInst.addOperand(Inst.getOperand(5));
7634     Inst = TmpInst;
7635     return true;
7636   }
7637
7638   // Handle NEON VLD complex aliases.
7639   case ARM::VLD1LNdWB_register_Asm_8:
7640   case ARM::VLD1LNdWB_register_Asm_16:
7641   case ARM::VLD1LNdWB_register_Asm_32: {
7642     MCInst TmpInst;
7643     // Shuffle the operands around so the lane index operand is in the
7644     // right place.
7645     unsigned Spacing;
7646     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7647     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7648     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7649     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7650     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7651     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7652     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7653     TmpInst.addOperand(Inst.getOperand(1)); // lane
7654     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7655     TmpInst.addOperand(Inst.getOperand(6));
7656     Inst = TmpInst;
7657     return true;
7658   }
7659
7660   case ARM::VLD2LNdWB_register_Asm_8:
7661   case ARM::VLD2LNdWB_register_Asm_16:
7662   case ARM::VLD2LNdWB_register_Asm_32:
7663   case ARM::VLD2LNqWB_register_Asm_16:
7664   case ARM::VLD2LNqWB_register_Asm_32: {
7665     MCInst TmpInst;
7666     // Shuffle the operands around so the lane index operand is in the
7667     // right place.
7668     unsigned Spacing;
7669     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7670     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7671     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7672                                             Spacing));
7673     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7674     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7675     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7676     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7677     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7678     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7679                                             Spacing));
7680     TmpInst.addOperand(Inst.getOperand(1)); // lane
7681     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7682     TmpInst.addOperand(Inst.getOperand(6));
7683     Inst = TmpInst;
7684     return true;
7685   }
7686
7687   case ARM::VLD3LNdWB_register_Asm_8:
7688   case ARM::VLD3LNdWB_register_Asm_16:
7689   case ARM::VLD3LNdWB_register_Asm_32:
7690   case ARM::VLD3LNqWB_register_Asm_16:
7691   case ARM::VLD3LNqWB_register_Asm_32: {
7692     MCInst TmpInst;
7693     // Shuffle the operands around so the lane index operand is in the
7694     // right place.
7695     unsigned Spacing;
7696     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7697     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7698     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7699                                             Spacing));
7700     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7701                                             Spacing * 2));
7702     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7703     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7704     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7705     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7706     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7707     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7708                                             Spacing));
7709     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7710                                             Spacing * 2));
7711     TmpInst.addOperand(Inst.getOperand(1)); // lane
7712     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7713     TmpInst.addOperand(Inst.getOperand(6));
7714     Inst = TmpInst;
7715     return true;
7716   }
7717
7718   case ARM::VLD4LNdWB_register_Asm_8:
7719   case ARM::VLD4LNdWB_register_Asm_16:
7720   case ARM::VLD4LNdWB_register_Asm_32:
7721   case ARM::VLD4LNqWB_register_Asm_16:
7722   case ARM::VLD4LNqWB_register_Asm_32: {
7723     MCInst TmpInst;
7724     // Shuffle the operands around so the lane index operand is in the
7725     // right place.
7726     unsigned Spacing;
7727     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7728     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7729     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7730                                             Spacing));
7731     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7732                                             Spacing * 2));
7733     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7734                                             Spacing * 3));
7735     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7736     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7737     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7738     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7739     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7740     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7741                                             Spacing));
7742     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7743                                             Spacing * 2));
7744     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7745                                             Spacing * 3));
7746     TmpInst.addOperand(Inst.getOperand(1)); // lane
7747     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7748     TmpInst.addOperand(Inst.getOperand(6));
7749     Inst = TmpInst;
7750     return true;
7751   }
7752
7753   case ARM::VLD1LNdWB_fixed_Asm_8:
7754   case ARM::VLD1LNdWB_fixed_Asm_16:
7755   case ARM::VLD1LNdWB_fixed_Asm_32: {
7756     MCInst TmpInst;
7757     // Shuffle the operands around so the lane index operand is in the
7758     // right place.
7759     unsigned Spacing;
7760     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7761     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7762     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7763     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7764     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7765     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7766     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7767     TmpInst.addOperand(Inst.getOperand(1)); // lane
7768     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7769     TmpInst.addOperand(Inst.getOperand(5));
7770     Inst = TmpInst;
7771     return true;
7772   }
7773
7774   case ARM::VLD2LNdWB_fixed_Asm_8:
7775   case ARM::VLD2LNdWB_fixed_Asm_16:
7776   case ARM::VLD2LNdWB_fixed_Asm_32:
7777   case ARM::VLD2LNqWB_fixed_Asm_16:
7778   case ARM::VLD2LNqWB_fixed_Asm_32: {
7779     MCInst TmpInst;
7780     // Shuffle the operands around so the lane index operand is in the
7781     // right place.
7782     unsigned Spacing;
7783     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7784     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7785     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7786                                             Spacing));
7787     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7788     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7789     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7790     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7791     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7792     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7793                                             Spacing));
7794     TmpInst.addOperand(Inst.getOperand(1)); // lane
7795     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7796     TmpInst.addOperand(Inst.getOperand(5));
7797     Inst = TmpInst;
7798     return true;
7799   }
7800
7801   case ARM::VLD3LNdWB_fixed_Asm_8:
7802   case ARM::VLD3LNdWB_fixed_Asm_16:
7803   case ARM::VLD3LNdWB_fixed_Asm_32:
7804   case ARM::VLD3LNqWB_fixed_Asm_16:
7805   case ARM::VLD3LNqWB_fixed_Asm_32: {
7806     MCInst TmpInst;
7807     // Shuffle the operands around so the lane index operand is in the
7808     // right place.
7809     unsigned Spacing;
7810     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7811     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7812     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7813                                             Spacing));
7814     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7815                                             Spacing * 2));
7816     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7817     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7818     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7819     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7820     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7821     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7822                                             Spacing));
7823     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7824                                             Spacing * 2));
7825     TmpInst.addOperand(Inst.getOperand(1)); // lane
7826     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7827     TmpInst.addOperand(Inst.getOperand(5));
7828     Inst = TmpInst;
7829     return true;
7830   }
7831
7832   case ARM::VLD4LNdWB_fixed_Asm_8:
7833   case ARM::VLD4LNdWB_fixed_Asm_16:
7834   case ARM::VLD4LNdWB_fixed_Asm_32:
7835   case ARM::VLD4LNqWB_fixed_Asm_16:
7836   case ARM::VLD4LNqWB_fixed_Asm_32: {
7837     MCInst TmpInst;
7838     // Shuffle the operands around so the lane index operand is in the
7839     // right place.
7840     unsigned Spacing;
7841     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7842     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7843     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7844                                             Spacing));
7845     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7846                                             Spacing * 2));
7847     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7848                                             Spacing * 3));
7849     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7850     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7851     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7852     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7853     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7854     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7855                                             Spacing));
7856     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7857                                             Spacing * 2));
7858     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7859                                             Spacing * 3));
7860     TmpInst.addOperand(Inst.getOperand(1)); // lane
7861     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7862     TmpInst.addOperand(Inst.getOperand(5));
7863     Inst = TmpInst;
7864     return true;
7865   }
7866
7867   case ARM::VLD1LNdAsm_8:
7868   case ARM::VLD1LNdAsm_16:
7869   case ARM::VLD1LNdAsm_32: {
7870     MCInst TmpInst;
7871     // Shuffle the operands around so the lane index operand is in the
7872     // right place.
7873     unsigned Spacing;
7874     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7875     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7876     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7877     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7878     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7879     TmpInst.addOperand(Inst.getOperand(1)); // lane
7880     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7881     TmpInst.addOperand(Inst.getOperand(5));
7882     Inst = TmpInst;
7883     return true;
7884   }
7885
7886   case ARM::VLD2LNdAsm_8:
7887   case ARM::VLD2LNdAsm_16:
7888   case ARM::VLD2LNdAsm_32:
7889   case ARM::VLD2LNqAsm_16:
7890   case ARM::VLD2LNqAsm_32: {
7891     MCInst TmpInst;
7892     // Shuffle the operands around so the lane index operand is in the
7893     // right place.
7894     unsigned Spacing;
7895     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7896     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7897     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7898                                             Spacing));
7899     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7900     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7901     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7902     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7903                                             Spacing));
7904     TmpInst.addOperand(Inst.getOperand(1)); // lane
7905     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7906     TmpInst.addOperand(Inst.getOperand(5));
7907     Inst = TmpInst;
7908     return true;
7909   }
7910
7911   case ARM::VLD3LNdAsm_8:
7912   case ARM::VLD3LNdAsm_16:
7913   case ARM::VLD3LNdAsm_32:
7914   case ARM::VLD3LNqAsm_16:
7915   case ARM::VLD3LNqAsm_32: {
7916     MCInst TmpInst;
7917     // Shuffle the operands around so the lane index operand is in the
7918     // right place.
7919     unsigned Spacing;
7920     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7921     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7922     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7923                                             Spacing));
7924     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7925                                             Spacing * 2));
7926     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7927     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7928     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7929     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7930                                             Spacing));
7931     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7932                                             Spacing * 2));
7933     TmpInst.addOperand(Inst.getOperand(1)); // lane
7934     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7935     TmpInst.addOperand(Inst.getOperand(5));
7936     Inst = TmpInst;
7937     return true;
7938   }
7939
7940   case ARM::VLD4LNdAsm_8:
7941   case ARM::VLD4LNdAsm_16:
7942   case ARM::VLD4LNdAsm_32:
7943   case ARM::VLD4LNqAsm_16:
7944   case ARM::VLD4LNqAsm_32: {
7945     MCInst TmpInst;
7946     // Shuffle the operands around so the lane index operand is in the
7947     // right place.
7948     unsigned Spacing;
7949     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7950     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7951     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7952                                             Spacing));
7953     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7954                                             Spacing * 2));
7955     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7956                                             Spacing * 3));
7957     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7958     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7959     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7960     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7961                                             Spacing));
7962     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7963                                             Spacing * 2));
7964     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7965                                             Spacing * 3));
7966     TmpInst.addOperand(Inst.getOperand(1)); // lane
7967     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7968     TmpInst.addOperand(Inst.getOperand(5));
7969     Inst = TmpInst;
7970     return true;
7971   }
7972
7973   // VLD3DUP single 3-element structure to all lanes instructions.
7974   case ARM::VLD3DUPdAsm_8:
7975   case ARM::VLD3DUPdAsm_16:
7976   case ARM::VLD3DUPdAsm_32:
7977   case ARM::VLD3DUPqAsm_8:
7978   case ARM::VLD3DUPqAsm_16:
7979   case ARM::VLD3DUPqAsm_32: {
7980     MCInst TmpInst;
7981     unsigned Spacing;
7982     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7983     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7984     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7985                                             Spacing));
7986     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7987                                             Spacing * 2));
7988     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7989     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7990     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7991     TmpInst.addOperand(Inst.getOperand(4));
7992     Inst = TmpInst;
7993     return true;
7994   }
7995
7996   case ARM::VLD3DUPdWB_fixed_Asm_8:
7997   case ARM::VLD3DUPdWB_fixed_Asm_16:
7998   case ARM::VLD3DUPdWB_fixed_Asm_32:
7999   case ARM::VLD3DUPqWB_fixed_Asm_8:
8000   case ARM::VLD3DUPqWB_fixed_Asm_16:
8001   case ARM::VLD3DUPqWB_fixed_Asm_32: {
8002     MCInst TmpInst;
8003     unsigned Spacing;
8004     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8005     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8006     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8007                                             Spacing));
8008     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8009                                             Spacing * 2));
8010     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8011     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8012     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8013     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8014     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8015     TmpInst.addOperand(Inst.getOperand(4));
8016     Inst = TmpInst;
8017     return true;
8018   }
8019
8020   case ARM::VLD3DUPdWB_register_Asm_8:
8021   case ARM::VLD3DUPdWB_register_Asm_16:
8022   case ARM::VLD3DUPdWB_register_Asm_32:
8023   case ARM::VLD3DUPqWB_register_Asm_8:
8024   case ARM::VLD3DUPqWB_register_Asm_16:
8025   case ARM::VLD3DUPqWB_register_Asm_32: {
8026     MCInst TmpInst;
8027     unsigned Spacing;
8028     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8029     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8030     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8031                                             Spacing));
8032     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8033                                             Spacing * 2));
8034     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8035     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8036     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8037     TmpInst.addOperand(Inst.getOperand(3)); // Rm
8038     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8039     TmpInst.addOperand(Inst.getOperand(5));
8040     Inst = TmpInst;
8041     return true;
8042   }
8043
8044   // VLD3 multiple 3-element structure instructions.
8045   case ARM::VLD3dAsm_8:
8046   case ARM::VLD3dAsm_16:
8047   case ARM::VLD3dAsm_32:
8048   case ARM::VLD3qAsm_8:
8049   case ARM::VLD3qAsm_16:
8050   case ARM::VLD3qAsm_32: {
8051     MCInst TmpInst;
8052     unsigned Spacing;
8053     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8054     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8055     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8056                                             Spacing));
8057     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8058                                             Spacing * 2));
8059     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8060     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8061     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8062     TmpInst.addOperand(Inst.getOperand(4));
8063     Inst = TmpInst;
8064     return true;
8065   }
8066
8067   case ARM::VLD3dWB_fixed_Asm_8:
8068   case ARM::VLD3dWB_fixed_Asm_16:
8069   case ARM::VLD3dWB_fixed_Asm_32:
8070   case ARM::VLD3qWB_fixed_Asm_8:
8071   case ARM::VLD3qWB_fixed_Asm_16:
8072   case ARM::VLD3qWB_fixed_Asm_32: {
8073     MCInst TmpInst;
8074     unsigned Spacing;
8075     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8076     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8077     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8078                                             Spacing));
8079     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8080                                             Spacing * 2));
8081     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8082     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8083     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8084     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8085     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8086     TmpInst.addOperand(Inst.getOperand(4));
8087     Inst = TmpInst;
8088     return true;
8089   }
8090
8091   case ARM::VLD3dWB_register_Asm_8:
8092   case ARM::VLD3dWB_register_Asm_16:
8093   case ARM::VLD3dWB_register_Asm_32:
8094   case ARM::VLD3qWB_register_Asm_8:
8095   case ARM::VLD3qWB_register_Asm_16:
8096   case ARM::VLD3qWB_register_Asm_32: {
8097     MCInst TmpInst;
8098     unsigned Spacing;
8099     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8100     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8101     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8102                                             Spacing));
8103     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8104                                             Spacing * 2));
8105     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8106     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8107     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8108     TmpInst.addOperand(Inst.getOperand(3)); // Rm
8109     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8110     TmpInst.addOperand(Inst.getOperand(5));
8111     Inst = TmpInst;
8112     return true;
8113   }
8114
8115   // VLD4DUP single 3-element structure to all lanes instructions.
8116   case ARM::VLD4DUPdAsm_8:
8117   case ARM::VLD4DUPdAsm_16:
8118   case ARM::VLD4DUPdAsm_32:
8119   case ARM::VLD4DUPqAsm_8:
8120   case ARM::VLD4DUPqAsm_16:
8121   case ARM::VLD4DUPqAsm_32: {
8122     MCInst TmpInst;
8123     unsigned Spacing;
8124     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8125     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8126     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8127                                             Spacing));
8128     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8129                                             Spacing * 2));
8130     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8131                                             Spacing * 3));
8132     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8133     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8134     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8135     TmpInst.addOperand(Inst.getOperand(4));
8136     Inst = TmpInst;
8137     return true;
8138   }
8139
8140   case ARM::VLD4DUPdWB_fixed_Asm_8:
8141   case ARM::VLD4DUPdWB_fixed_Asm_16:
8142   case ARM::VLD4DUPdWB_fixed_Asm_32:
8143   case ARM::VLD4DUPqWB_fixed_Asm_8:
8144   case ARM::VLD4DUPqWB_fixed_Asm_16:
8145   case ARM::VLD4DUPqWB_fixed_Asm_32: {
8146     MCInst TmpInst;
8147     unsigned Spacing;
8148     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8149     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8150     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8151                                             Spacing));
8152     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8153                                             Spacing * 2));
8154     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8155                                             Spacing * 3));
8156     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8157     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8158     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8159     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8160     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8161     TmpInst.addOperand(Inst.getOperand(4));
8162     Inst = TmpInst;
8163     return true;
8164   }
8165
8166   case ARM::VLD4DUPdWB_register_Asm_8:
8167   case ARM::VLD4DUPdWB_register_Asm_16:
8168   case ARM::VLD4DUPdWB_register_Asm_32:
8169   case ARM::VLD4DUPqWB_register_Asm_8:
8170   case ARM::VLD4DUPqWB_register_Asm_16:
8171   case ARM::VLD4DUPqWB_register_Asm_32: {
8172     MCInst TmpInst;
8173     unsigned Spacing;
8174     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8175     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8176     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8177                                             Spacing));
8178     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8179                                             Spacing * 2));
8180     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8181                                             Spacing * 3));
8182     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8183     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8184     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8185     TmpInst.addOperand(Inst.getOperand(3)); // Rm
8186     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8187     TmpInst.addOperand(Inst.getOperand(5));
8188     Inst = TmpInst;
8189     return true;
8190   }
8191
8192   // VLD4 multiple 4-element structure instructions.
8193   case ARM::VLD4dAsm_8:
8194   case ARM::VLD4dAsm_16:
8195   case ARM::VLD4dAsm_32:
8196   case ARM::VLD4qAsm_8:
8197   case ARM::VLD4qAsm_16:
8198   case ARM::VLD4qAsm_32: {
8199     MCInst TmpInst;
8200     unsigned Spacing;
8201     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8202     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8203     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8204                                             Spacing));
8205     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8206                                             Spacing * 2));
8207     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8208                                             Spacing * 3));
8209     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8210     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8211     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8212     TmpInst.addOperand(Inst.getOperand(4));
8213     Inst = TmpInst;
8214     return true;
8215   }
8216
8217   case ARM::VLD4dWB_fixed_Asm_8:
8218   case ARM::VLD4dWB_fixed_Asm_16:
8219   case ARM::VLD4dWB_fixed_Asm_32:
8220   case ARM::VLD4qWB_fixed_Asm_8:
8221   case ARM::VLD4qWB_fixed_Asm_16:
8222   case ARM::VLD4qWB_fixed_Asm_32: {
8223     MCInst TmpInst;
8224     unsigned Spacing;
8225     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8226     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8227     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8228                                             Spacing));
8229     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8230                                             Spacing * 2));
8231     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8232                                             Spacing * 3));
8233     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8234     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8235     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8236     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8237     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8238     TmpInst.addOperand(Inst.getOperand(4));
8239     Inst = TmpInst;
8240     return true;
8241   }
8242
8243   case ARM::VLD4dWB_register_Asm_8:
8244   case ARM::VLD4dWB_register_Asm_16:
8245   case ARM::VLD4dWB_register_Asm_32:
8246   case ARM::VLD4qWB_register_Asm_8:
8247   case ARM::VLD4qWB_register_Asm_16:
8248   case ARM::VLD4qWB_register_Asm_32: {
8249     MCInst TmpInst;
8250     unsigned Spacing;
8251     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8252     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8253     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8254                                             Spacing));
8255     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8256                                             Spacing * 2));
8257     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8258                                             Spacing * 3));
8259     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8260     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8261     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8262     TmpInst.addOperand(Inst.getOperand(3)); // Rm
8263     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8264     TmpInst.addOperand(Inst.getOperand(5));
8265     Inst = TmpInst;
8266     return true;
8267   }
8268
8269   // VST3 multiple 3-element structure instructions.
8270   case ARM::VST3dAsm_8:
8271   case ARM::VST3dAsm_16:
8272   case ARM::VST3dAsm_32:
8273   case ARM::VST3qAsm_8:
8274   case ARM::VST3qAsm_16:
8275   case ARM::VST3qAsm_32: {
8276     MCInst TmpInst;
8277     unsigned Spacing;
8278     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8279     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8280     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8281     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8282     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8283                                             Spacing));
8284     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8285                                             Spacing * 2));
8286     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8287     TmpInst.addOperand(Inst.getOperand(4));
8288     Inst = TmpInst;
8289     return true;
8290   }
8291
8292   case ARM::VST3dWB_fixed_Asm_8:
8293   case ARM::VST3dWB_fixed_Asm_16:
8294   case ARM::VST3dWB_fixed_Asm_32:
8295   case ARM::VST3qWB_fixed_Asm_8:
8296   case ARM::VST3qWB_fixed_Asm_16:
8297   case ARM::VST3qWB_fixed_Asm_32: {
8298     MCInst TmpInst;
8299     unsigned Spacing;
8300     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8301     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8302     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8303     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8304     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8305     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8306     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8307                                             Spacing));
8308     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8309                                             Spacing * 2));
8310     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8311     TmpInst.addOperand(Inst.getOperand(4));
8312     Inst = TmpInst;
8313     return true;
8314   }
8315
8316   case ARM::VST3dWB_register_Asm_8:
8317   case ARM::VST3dWB_register_Asm_16:
8318   case ARM::VST3dWB_register_Asm_32:
8319   case ARM::VST3qWB_register_Asm_8:
8320   case ARM::VST3qWB_register_Asm_16:
8321   case ARM::VST3qWB_register_Asm_32: {
8322     MCInst TmpInst;
8323     unsigned Spacing;
8324     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8325     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8326     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8327     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8328     TmpInst.addOperand(Inst.getOperand(3)); // Rm
8329     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8330     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8331                                             Spacing));
8332     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8333                                             Spacing * 2));
8334     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8335     TmpInst.addOperand(Inst.getOperand(5));
8336     Inst = TmpInst;
8337     return true;
8338   }
8339
8340   // VST4 multiple 3-element structure instructions.
8341   case ARM::VST4dAsm_8:
8342   case ARM::VST4dAsm_16:
8343   case ARM::VST4dAsm_32:
8344   case ARM::VST4qAsm_8:
8345   case ARM::VST4qAsm_16:
8346   case ARM::VST4qAsm_32: {
8347     MCInst TmpInst;
8348     unsigned Spacing;
8349     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8350     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8351     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8352     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8353     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8354                                             Spacing));
8355     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8356                                             Spacing * 2));
8357     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8358                                             Spacing * 3));
8359     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8360     TmpInst.addOperand(Inst.getOperand(4));
8361     Inst = TmpInst;
8362     return true;
8363   }
8364
8365   case ARM::VST4dWB_fixed_Asm_8:
8366   case ARM::VST4dWB_fixed_Asm_16:
8367   case ARM::VST4dWB_fixed_Asm_32:
8368   case ARM::VST4qWB_fixed_Asm_8:
8369   case ARM::VST4qWB_fixed_Asm_16:
8370   case ARM::VST4qWB_fixed_Asm_32: {
8371     MCInst TmpInst;
8372     unsigned Spacing;
8373     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8374     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8375     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8376     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8377     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8378     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8379     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8380                                             Spacing));
8381     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8382                                             Spacing * 2));
8383     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8384                                             Spacing * 3));
8385     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8386     TmpInst.addOperand(Inst.getOperand(4));
8387     Inst = TmpInst;
8388     return true;
8389   }
8390
8391   case ARM::VST4dWB_register_Asm_8:
8392   case ARM::VST4dWB_register_Asm_16:
8393   case ARM::VST4dWB_register_Asm_32:
8394   case ARM::VST4qWB_register_Asm_8:
8395   case ARM::VST4qWB_register_Asm_16:
8396   case ARM::VST4qWB_register_Asm_32: {
8397     MCInst TmpInst;
8398     unsigned Spacing;
8399     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8400     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8401     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8402     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8403     TmpInst.addOperand(Inst.getOperand(3)); // Rm
8404     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8405     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8406                                             Spacing));
8407     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8408                                             Spacing * 2));
8409     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8410                                             Spacing * 3));
8411     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8412     TmpInst.addOperand(Inst.getOperand(5));
8413     Inst = TmpInst;
8414     return true;
8415   }
8416
8417   // Handle encoding choice for the shift-immediate instructions.
8418   case ARM::t2LSLri:
8419   case ARM::t2LSRri:
8420   case ARM::t2ASRri:
8421     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8422         isARMLowRegister(Inst.getOperand(1).getReg()) &&
8423         Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
8424         !HasWideQualifier) {
8425       unsigned NewOpc;
8426       switch (Inst.getOpcode()) {
8427       default: llvm_unreachable("unexpected opcode");
8428       case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
8429       case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
8430       case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
8431       }
8432       // The Thumb1 operands aren't in the same order. Awesome, eh?
8433       MCInst TmpInst;
8434       TmpInst.setOpcode(NewOpc);
8435       TmpInst.addOperand(Inst.getOperand(0));
8436       TmpInst.addOperand(Inst.getOperand(5));
8437       TmpInst.addOperand(Inst.getOperand(1));
8438       TmpInst.addOperand(Inst.getOperand(2));
8439       TmpInst.addOperand(Inst.getOperand(3));
8440       TmpInst.addOperand(Inst.getOperand(4));
8441       Inst = TmpInst;
8442       return true;
8443     }
8444     return false;
8445
8446   // Handle the Thumb2 mode MOV complex aliases.
8447   case ARM::t2MOVsr:
8448   case ARM::t2MOVSsr: {
8449     // Which instruction to expand to depends on the CCOut operand and
8450     // whether we're in an IT block if the register operands are low
8451     // registers.
8452     bool isNarrow = false;
8453     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8454         isARMLowRegister(Inst.getOperand(1).getReg()) &&
8455         isARMLowRegister(Inst.getOperand(2).getReg()) &&
8456         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
8457         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr) &&
8458         !HasWideQualifier)
8459       isNarrow = true;
8460     MCInst TmpInst;
8461     unsigned newOpc;
8462     switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
8463     default: llvm_unreachable("unexpected opcode!");
8464     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
8465     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
8466     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
8467     case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
8468     }
8469     TmpInst.setOpcode(newOpc);
8470     TmpInst.addOperand(Inst.getOperand(0)); // Rd
8471     if (isNarrow)
8472       TmpInst.addOperand(MCOperand::createReg(
8473           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
8474     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8475     TmpInst.addOperand(Inst.getOperand(2)); // Rm
8476     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8477     TmpInst.addOperand(Inst.getOperand(5));
8478     if (!isNarrow)
8479       TmpInst.addOperand(MCOperand::createReg(
8480           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
8481     Inst = TmpInst;
8482     return true;
8483   }
8484   case ARM::t2MOVsi:
8485   case ARM::t2MOVSsi: {
8486     // Which instruction to expand to depends on the CCOut operand and
8487     // whether we're in an IT block if the register operands are low
8488     // registers.
8489     bool isNarrow = false;
8490     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8491         isARMLowRegister(Inst.getOperand(1).getReg()) &&
8492         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi) &&
8493         !HasWideQualifier)
8494       isNarrow = true;
8495     MCInst TmpInst;
8496     unsigned newOpc;
8497     unsigned Shift = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
8498     unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
8499     bool isMov = false;
8500     // MOV rd, rm, LSL #0 is actually a MOV instruction
8501     if (Shift == ARM_AM::lsl && Amount == 0) {
8502       isMov = true;
8503       // The 16-bit encoding of MOV rd, rm, LSL #N is explicitly encoding T2 of
8504       // MOV (register) in the ARMv8-A and ARMv8-M manuals, and immediate 0 is
8505       // unpredictable in an IT block so the 32-bit encoding T3 has to be used
8506       // instead.
8507       if (inITBlock()) {
8508         isNarrow = false;
8509       }
8510       newOpc = isNarrow ? ARM::tMOVSr : ARM::t2MOVr;
8511     } else {
8512       switch(Shift) {
8513       default: llvm_unreachable("unexpected opcode!");
8514       case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
8515       case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
8516       case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
8517       case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
8518       case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
8519       }
8520     }
8521     if (Amount == 32) Amount = 0;
8522     TmpInst.setOpcode(newOpc);
8523     TmpInst.addOperand(Inst.getOperand(0)); // Rd
8524     if (isNarrow && !isMov)
8525       TmpInst.addOperand(MCOperand::createReg(
8526           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
8527     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8528     if (newOpc != ARM::t2RRX && !isMov)
8529       TmpInst.addOperand(MCOperand::createImm(Amount));
8530     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8531     TmpInst.addOperand(Inst.getOperand(4));
8532     if (!isNarrow)
8533       TmpInst.addOperand(MCOperand::createReg(
8534           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
8535     Inst = TmpInst;
8536     return true;
8537   }
8538   // Handle the ARM mode MOV complex aliases.
8539   case ARM::ASRr:
8540   case ARM::LSRr:
8541   case ARM::LSLr:
8542   case ARM::RORr: {
8543     ARM_AM::ShiftOpc ShiftTy;
8544     switch(Inst.getOpcode()) {
8545     default: llvm_unreachable("unexpected opcode!");
8546     case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
8547     case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
8548     case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
8549     case ARM::RORr: ShiftTy = ARM_AM::ror; break;
8550     }
8551     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
8552     MCInst TmpInst;
8553     TmpInst.setOpcode(ARM::MOVsr);
8554     TmpInst.addOperand(Inst.getOperand(0)); // Rd
8555     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8556     TmpInst.addOperand(Inst.getOperand(2)); // Rm
8557     TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
8558     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8559     TmpInst.addOperand(Inst.getOperand(4));
8560     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
8561     Inst = TmpInst;
8562     return true;
8563   }
8564   case ARM::ASRi:
8565   case ARM::LSRi:
8566   case ARM::LSLi:
8567   case ARM::RORi: {
8568     ARM_AM::ShiftOpc ShiftTy;
8569     switch(Inst.getOpcode()) {
8570     default: llvm_unreachable("unexpected opcode!");
8571     case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
8572     case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
8573     case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
8574     case ARM::RORi: ShiftTy = ARM_AM::ror; break;
8575     }
8576     // A shift by zero is a plain MOVr, not a MOVsi.
8577     unsigned Amt = Inst.getOperand(2).getImm();
8578     unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
8579     // A shift by 32 should be encoded as 0 when permitted
8580     if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
8581       Amt = 0;
8582     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
8583     MCInst TmpInst;
8584     TmpInst.setOpcode(Opc);
8585     TmpInst.addOperand(Inst.getOperand(0)); // Rd
8586     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8587     if (Opc == ARM::MOVsi)
8588       TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
8589     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8590     TmpInst.addOperand(Inst.getOperand(4));
8591     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
8592     Inst = TmpInst;
8593     return true;
8594   }
8595   case ARM::RRXi: {
8596     unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
8597     MCInst TmpInst;
8598     TmpInst.setOpcode(ARM::MOVsi);
8599     TmpInst.addOperand(Inst.getOperand(0)); // Rd
8600     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8601     TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
8602     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8603     TmpInst.addOperand(Inst.getOperand(3));
8604     TmpInst.addOperand(Inst.getOperand(4)); // cc_out
8605     Inst = TmpInst;
8606     return true;
8607   }
8608   case ARM::t2LDMIA_UPD: {
8609     // If this is a load of a single register, then we should use
8610     // a post-indexed LDR instruction instead, per the ARM ARM.
8611     if (Inst.getNumOperands() != 5)
8612       return false;
8613     MCInst TmpInst;
8614     TmpInst.setOpcode(ARM::t2LDR_POST);
8615     TmpInst.addOperand(Inst.getOperand(4)); // Rt
8616     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8617     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8618     TmpInst.addOperand(MCOperand::createImm(4));
8619     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8620     TmpInst.addOperand(Inst.getOperand(3));
8621     Inst = TmpInst;
8622     return true;
8623   }
8624   case ARM::t2STMDB_UPD: {
8625     // If this is a store of a single register, then we should use
8626     // a pre-indexed STR instruction instead, per the ARM ARM.
8627     if (Inst.getNumOperands() != 5)
8628       return false;
8629     MCInst TmpInst;
8630     TmpInst.setOpcode(ARM::t2STR_PRE);
8631     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8632     TmpInst.addOperand(Inst.getOperand(4)); // Rt
8633     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8634     TmpInst.addOperand(MCOperand::createImm(-4));
8635     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8636     TmpInst.addOperand(Inst.getOperand(3));
8637     Inst = TmpInst;
8638     return true;
8639   }
8640   case ARM::LDMIA_UPD:
8641     // If this is a load of a single register via a 'pop', then we should use
8642     // a post-indexed LDR instruction instead, per the ARM ARM.
8643     if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
8644         Inst.getNumOperands() == 5) {
8645       MCInst TmpInst;
8646       TmpInst.setOpcode(ARM::LDR_POST_IMM);
8647       TmpInst.addOperand(Inst.getOperand(4)); // Rt
8648       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8649       TmpInst.addOperand(Inst.getOperand(1)); // Rn
8650       TmpInst.addOperand(MCOperand::createReg(0));  // am2offset
8651       TmpInst.addOperand(MCOperand::createImm(4));
8652       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8653       TmpInst.addOperand(Inst.getOperand(3));
8654       Inst = TmpInst;
8655       return true;
8656     }
8657     break;
8658   case ARM::STMDB_UPD:
8659     // If this is a store of a single register via a 'push', then we should use
8660     // a pre-indexed STR instruction instead, per the ARM ARM.
8661     if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
8662         Inst.getNumOperands() == 5) {
8663       MCInst TmpInst;
8664       TmpInst.setOpcode(ARM::STR_PRE_IMM);
8665       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8666       TmpInst.addOperand(Inst.getOperand(4)); // Rt
8667       TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
8668       TmpInst.addOperand(MCOperand::createImm(-4));
8669       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8670       TmpInst.addOperand(Inst.getOperand(3));
8671       Inst = TmpInst;
8672     }
8673     break;
8674   case ARM::t2ADDri12:
8675     // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
8676     // mnemonic was used (not "addw"), encoding T3 is preferred.
8677     if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" ||
8678         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8679       break;
8680     Inst.setOpcode(ARM::t2ADDri);
8681     Inst.addOperand(MCOperand::createReg(0)); // cc_out
8682     break;
8683   case ARM::t2SUBri12:
8684     // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
8685     // mnemonic was used (not "subw"), encoding T3 is preferred.
8686     if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" ||
8687         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8688       break;
8689     Inst.setOpcode(ARM::t2SUBri);
8690     Inst.addOperand(MCOperand::createReg(0)); // cc_out
8691     break;
8692   case ARM::tADDi8:
8693     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
8694     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
8695     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
8696     // to encoding T1 if <Rd> is omitted."
8697     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
8698       Inst.setOpcode(ARM::tADDi3);
8699       return true;
8700     }
8701     break;
8702   case ARM::tSUBi8:
8703     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
8704     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
8705     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
8706     // to encoding T1 if <Rd> is omitted."
8707     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
8708       Inst.setOpcode(ARM::tSUBi3);
8709       return true;
8710     }
8711     break;
8712   case ARM::t2ADDri:
8713   case ARM::t2SUBri: {
8714     // If the destination and first source operand are the same, and
8715     // the flags are compatible with the current IT status, use encoding T2
8716     // instead of T3. For compatibility with the system 'as'. Make sure the
8717     // wide encoding wasn't explicit.
8718     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
8719         !isARMLowRegister(Inst.getOperand(0).getReg()) ||
8720         (Inst.getOperand(2).isImm() &&
8721          (unsigned)Inst.getOperand(2).getImm() > 255) ||
8722         Inst.getOperand(5).getReg() != (inITBlock() ? 0 : ARM::CPSR) ||
8723         HasWideQualifier)
8724       break;
8725     MCInst TmpInst;
8726     TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
8727                       ARM::tADDi8 : ARM::tSUBi8);
8728     TmpInst.addOperand(Inst.getOperand(0));
8729     TmpInst.addOperand(Inst.getOperand(5));
8730     TmpInst.addOperand(Inst.getOperand(0));
8731     TmpInst.addOperand(Inst.getOperand(2));
8732     TmpInst.addOperand(Inst.getOperand(3));
8733     TmpInst.addOperand(Inst.getOperand(4));
8734     Inst = TmpInst;
8735     return true;
8736   }
8737   case ARM::t2ADDrr: {
8738     // If the destination and first source operand are the same, and
8739     // there's no setting of the flags, use encoding T2 instead of T3.
8740     // Note that this is only for ADD, not SUB. This mirrors the system
8741     // 'as' behaviour.  Also take advantage of ADD being commutative.
8742     // Make sure the wide encoding wasn't explicit.
8743     bool Swap = false;
8744     auto DestReg = Inst.getOperand(0).getReg();
8745     bool Transform = DestReg == Inst.getOperand(1).getReg();
8746     if (!Transform && DestReg == Inst.getOperand(2).getReg()) {
8747       Transform = true;
8748       Swap = true;
8749     }
8750     if (!Transform ||
8751         Inst.getOperand(5).getReg() != 0 ||
8752         HasWideQualifier)
8753       break;
8754     MCInst TmpInst;
8755     TmpInst.setOpcode(ARM::tADDhirr);
8756     TmpInst.addOperand(Inst.getOperand(0));
8757     TmpInst.addOperand(Inst.getOperand(0));
8758     TmpInst.addOperand(Inst.getOperand(Swap ? 1 : 2));
8759     TmpInst.addOperand(Inst.getOperand(3));
8760     TmpInst.addOperand(Inst.getOperand(4));
8761     Inst = TmpInst;
8762     return true;
8763   }
8764   case ARM::tADDrSP:
8765     // If the non-SP source operand and the destination operand are not the
8766     // same, we need to use the 32-bit encoding if it's available.
8767     if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
8768       Inst.setOpcode(ARM::t2ADDrr);
8769       Inst.addOperand(MCOperand::createReg(0)); // cc_out
8770       return true;
8771     }
8772     break;
8773   case ARM::tB:
8774     // A Thumb conditional branch outside of an IT block is a tBcc.
8775     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
8776       Inst.setOpcode(ARM::tBcc);
8777       return true;
8778     }
8779     break;
8780   case ARM::t2B:
8781     // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
8782     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
8783       Inst.setOpcode(ARM::t2Bcc);
8784       return true;
8785     }
8786     break;
8787   case ARM::t2Bcc:
8788     // If the conditional is AL or we're in an IT block, we really want t2B.
8789     if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
8790       Inst.setOpcode(ARM::t2B);
8791       return true;
8792     }
8793     break;
8794   case ARM::tBcc:
8795     // If the conditional is AL, we really want tB.
8796     if (Inst.getOperand(1).getImm() == ARMCC::AL) {
8797       Inst.setOpcode(ARM::tB);
8798       return true;
8799     }
8800     break;
8801   case ARM::tLDMIA: {
8802     // If the register list contains any high registers, or if the writeback
8803     // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
8804     // instead if we're in Thumb2. Otherwise, this should have generated
8805     // an error in validateInstruction().
8806     unsigned Rn = Inst.getOperand(0).getReg();
8807     bool hasWritebackToken =
8808         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8809          static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
8810     bool listContainsBase;
8811     if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
8812         (!listContainsBase && !hasWritebackToken) ||
8813         (listContainsBase && hasWritebackToken)) {
8814       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
8815       assert(isThumbTwo());
8816       Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
8817       // If we're switching to the updating version, we need to insert
8818       // the writeback tied operand.
8819       if (hasWritebackToken)
8820         Inst.insert(Inst.begin(),
8821                     MCOperand::createReg(Inst.getOperand(0).getReg()));
8822       return true;
8823     }
8824     break;
8825   }
8826   case ARM::tSTMIA_UPD: {
8827     // If the register list contains any high registers, we need to use
8828     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
8829     // should have generated an error in validateInstruction().
8830     unsigned Rn = Inst.getOperand(0).getReg();
8831     bool listContainsBase;
8832     if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
8833       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
8834       assert(isThumbTwo());
8835       Inst.setOpcode(ARM::t2STMIA_UPD);
8836       return true;
8837     }
8838     break;
8839   }
8840   case ARM::tPOP: {
8841     bool listContainsBase;
8842     // If the register list contains any high registers, we need to use
8843     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
8844     // should have generated an error in validateInstruction().
8845     if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
8846       return false;
8847     assert(isThumbTwo());
8848     Inst.setOpcode(ARM::t2LDMIA_UPD);
8849     // Add the base register and writeback operands.
8850     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8851     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8852     return true;
8853   }
8854   case ARM::tPUSH: {
8855     bool listContainsBase;
8856     if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
8857       return false;
8858     assert(isThumbTwo());
8859     Inst.setOpcode(ARM::t2STMDB_UPD);
8860     // Add the base register and writeback operands.
8861     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8862     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8863     return true;
8864   }
8865   case ARM::t2MOVi:
8866     // If we can use the 16-bit encoding and the user didn't explicitly
8867     // request the 32-bit variant, transform it here.
8868     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8869         (Inst.getOperand(1).isImm() &&
8870          (unsigned)Inst.getOperand(1).getImm() <= 255) &&
8871         Inst.getOperand(4).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
8872         !HasWideQualifier) {
8873       // The operands aren't in the same order for tMOVi8...
8874       MCInst TmpInst;
8875       TmpInst.setOpcode(ARM::tMOVi8);
8876       TmpInst.addOperand(Inst.getOperand(0));
8877       TmpInst.addOperand(Inst.getOperand(4));
8878       TmpInst.addOperand(Inst.getOperand(1));
8879       TmpInst.addOperand(Inst.getOperand(2));
8880       TmpInst.addOperand(Inst.getOperand(3));
8881       Inst = TmpInst;
8882       return true;
8883     }
8884     break;
8885
8886   case ARM::t2MOVr:
8887     // If we can use the 16-bit encoding and the user didn't explicitly
8888     // request the 32-bit variant, transform it here.
8889     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8890         isARMLowRegister(Inst.getOperand(1).getReg()) &&
8891         Inst.getOperand(2).getImm() == ARMCC::AL &&
8892         Inst.getOperand(4).getReg() == ARM::CPSR &&
8893         !HasWideQualifier) {
8894       // The operands aren't the same for tMOV[S]r... (no cc_out)
8895       MCInst TmpInst;
8896       TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
8897       TmpInst.addOperand(Inst.getOperand(0));
8898       TmpInst.addOperand(Inst.getOperand(1));
8899       TmpInst.addOperand(Inst.getOperand(2));
8900       TmpInst.addOperand(Inst.getOperand(3));
8901       Inst = TmpInst;
8902       return true;
8903     }
8904     break;
8905
8906   case ARM::t2SXTH:
8907   case ARM::t2SXTB:
8908   case ARM::t2UXTH:
8909   case ARM::t2UXTB:
8910     // If we can use the 16-bit encoding and the user didn't explicitly
8911     // request the 32-bit variant, transform it here.
8912     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8913         isARMLowRegister(Inst.getOperand(1).getReg()) &&
8914         Inst.getOperand(2).getImm() == 0 &&
8915         !HasWideQualifier) {
8916       unsigned NewOpc;
8917       switch (Inst.getOpcode()) {
8918       default: llvm_unreachable("Illegal opcode!");
8919       case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
8920       case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
8921       case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
8922       case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
8923       }
8924       // The operands aren't the same for thumb1 (no rotate operand).
8925       MCInst TmpInst;
8926       TmpInst.setOpcode(NewOpc);
8927       TmpInst.addOperand(Inst.getOperand(0));
8928       TmpInst.addOperand(Inst.getOperand(1));
8929       TmpInst.addOperand(Inst.getOperand(3));
8930       TmpInst.addOperand(Inst.getOperand(4));
8931       Inst = TmpInst;
8932       return true;
8933     }
8934     break;
8935
8936   case ARM::MOVsi: {
8937     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
8938     // rrx shifts and asr/lsr of #32 is encoded as 0
8939     if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
8940       return false;
8941     if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
8942       // Shifting by zero is accepted as a vanilla 'MOVr'
8943       MCInst TmpInst;
8944       TmpInst.setOpcode(ARM::MOVr);
8945       TmpInst.addOperand(Inst.getOperand(0));
8946       TmpInst.addOperand(Inst.getOperand(1));
8947       TmpInst.addOperand(Inst.getOperand(3));
8948       TmpInst.addOperand(Inst.getOperand(4));
8949       TmpInst.addOperand(Inst.getOperand(5));
8950       Inst = TmpInst;
8951       return true;
8952     }
8953     return false;
8954   }
8955   case ARM::ANDrsi:
8956   case ARM::ORRrsi:
8957   case ARM::EORrsi:
8958   case ARM::BICrsi:
8959   case ARM::SUBrsi:
8960   case ARM::ADDrsi: {
8961     unsigned newOpc;
8962     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
8963     if (SOpc == ARM_AM::rrx) return false;
8964     switch (Inst.getOpcode()) {
8965     default: llvm_unreachable("unexpected opcode!");
8966     case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
8967     case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
8968     case ARM::EORrsi: newOpc = ARM::EORrr; break;
8969     case ARM::BICrsi: newOpc = ARM::BICrr; break;
8970     case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
8971     case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
8972     }
8973     // If the shift is by zero, use the non-shifted instruction definition.
8974     // The exception is for right shifts, where 0 == 32
8975     if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
8976         !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
8977       MCInst TmpInst;
8978       TmpInst.setOpcode(newOpc);
8979       TmpInst.addOperand(Inst.getOperand(0));
8980       TmpInst.addOperand(Inst.getOperand(1));
8981       TmpInst.addOperand(Inst.getOperand(2));
8982       TmpInst.addOperand(Inst.getOperand(4));
8983       TmpInst.addOperand(Inst.getOperand(5));
8984       TmpInst.addOperand(Inst.getOperand(6));
8985       Inst = TmpInst;
8986       return true;
8987     }
8988     return false;
8989   }
8990   case ARM::ITasm:
8991   case ARM::t2IT: {
8992     MCOperand &MO = Inst.getOperand(1);
8993     unsigned Mask = MO.getImm();
8994     ARMCC::CondCodes Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
8995
8996     // Set up the IT block state according to the IT instruction we just
8997     // matched.
8998     assert(!inITBlock() && "nested IT blocks?!");
8999     startExplicitITBlock(Cond, Mask);
9000     MO.setImm(getITMaskEncoding());
9001     break;
9002   }
9003   case ARM::t2LSLrr:
9004   case ARM::t2LSRrr:
9005   case ARM::t2ASRrr:
9006   case ARM::t2SBCrr:
9007   case ARM::t2RORrr:
9008   case ARM::t2BICrr:
9009     // Assemblers should use the narrow encodings of these instructions when permissible.
9010     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
9011          isARMLowRegister(Inst.getOperand(2).getReg())) &&
9012         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
9013         Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
9014         !HasWideQualifier) {
9015       unsigned NewOpc;
9016       switch (Inst.getOpcode()) {
9017         default: llvm_unreachable("unexpected opcode");
9018         case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
9019         case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
9020         case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
9021         case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
9022         case ARM::t2RORrr: NewOpc = ARM::tROR; break;
9023         case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
9024       }
9025       MCInst TmpInst;
9026       TmpInst.setOpcode(NewOpc);
9027       TmpInst.addOperand(Inst.getOperand(0));
9028       TmpInst.addOperand(Inst.getOperand(5));
9029       TmpInst.addOperand(Inst.getOperand(1));
9030       TmpInst.addOperand(Inst.getOperand(2));
9031       TmpInst.addOperand(Inst.getOperand(3));
9032       TmpInst.addOperand(Inst.getOperand(4));
9033       Inst = TmpInst;
9034       return true;
9035     }
9036     return false;
9037
9038   case ARM::t2ANDrr:
9039   case ARM::t2EORrr:
9040   case ARM::t2ADCrr:
9041   case ARM::t2ORRrr:
9042     // Assemblers should use the narrow encodings of these instructions when permissible.
9043     // These instructions are special in that they are commutable, so shorter encodings
9044     // are available more often.
9045     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
9046          isARMLowRegister(Inst.getOperand(2).getReg())) &&
9047         (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
9048          Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
9049         Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
9050         !HasWideQualifier) {
9051       unsigned NewOpc;
9052       switch (Inst.getOpcode()) {
9053         default: llvm_unreachable("unexpected opcode");
9054         case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
9055         case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
9056         case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
9057         case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
9058       }
9059       MCInst TmpInst;
9060       TmpInst.setOpcode(NewOpc);
9061       TmpInst.addOperand(Inst.getOperand(0));
9062       TmpInst.addOperand(Inst.getOperand(5));
9063       if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
9064         TmpInst.addOperand(Inst.getOperand(1));
9065         TmpInst.addOperand(Inst.getOperand(2));
9066       } else {
9067         TmpInst.addOperand(Inst.getOperand(2));
9068         TmpInst.addOperand(Inst.getOperand(1));
9069       }
9070       TmpInst.addOperand(Inst.getOperand(3));
9071       TmpInst.addOperand(Inst.getOperand(4));
9072       Inst = TmpInst;
9073       return true;
9074     }
9075     return false;
9076   }
9077   return false;
9078 }
9079
9080 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
9081   // 16-bit thumb arithmetic instructions either require or preclude the 'S'
9082   // suffix depending on whether they're in an IT block or not.
9083   unsigned Opc = Inst.getOpcode();
9084   const MCInstrDesc &MCID = MII.get(Opc);
9085   if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
9086     assert(MCID.hasOptionalDef() &&
9087            "optionally flag setting instruction missing optional def operand");
9088     assert(MCID.NumOperands == Inst.getNumOperands() &&
9089            "operand count mismatch!");
9090     // Find the optional-def operand (cc_out).
9091     unsigned OpNo;
9092     for (OpNo = 0;
9093          !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
9094          ++OpNo)
9095       ;
9096     // If we're parsing Thumb1, reject it completely.
9097     if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
9098       return Match_RequiresFlagSetting;
9099     // If we're parsing Thumb2, which form is legal depends on whether we're
9100     // in an IT block.
9101     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
9102         !inITBlock())
9103       return Match_RequiresITBlock;
9104     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
9105         inITBlock())
9106       return Match_RequiresNotITBlock;
9107     // LSL with zero immediate is not allowed in an IT block
9108     if (Opc == ARM::tLSLri && Inst.getOperand(3).getImm() == 0 && inITBlock())
9109       return Match_RequiresNotITBlock;
9110   } else if (isThumbOne()) {
9111     // Some high-register supporting Thumb1 encodings only allow both registers
9112     // to be from r0-r7 when in Thumb2.
9113     if (Opc == ARM::tADDhirr && !hasV6MOps() &&
9114         isARMLowRegister(Inst.getOperand(1).getReg()) &&
9115         isARMLowRegister(Inst.getOperand(2).getReg()))
9116       return Match_RequiresThumb2;
9117     // Others only require ARMv6 or later.
9118     else if (Opc == ARM::tMOVr && !hasV6Ops() &&
9119              isARMLowRegister(Inst.getOperand(0).getReg()) &&
9120              isARMLowRegister(Inst.getOperand(1).getReg()))
9121       return Match_RequiresV6;
9122   }
9123
9124   // Before ARMv8 the rules for when SP is allowed in t2MOVr are more complex
9125   // than the loop below can handle, so it uses the GPRnopc register class and
9126   // we do SP handling here.
9127   if (Opc == ARM::t2MOVr && !hasV8Ops())
9128   {
9129     // SP as both source and destination is not allowed
9130     if (Inst.getOperand(0).getReg() == ARM::SP &&
9131         Inst.getOperand(1).getReg() == ARM::SP)
9132       return Match_RequiresV8;
9133     // When flags-setting SP as either source or destination is not allowed
9134     if (Inst.getOperand(4).getReg() == ARM::CPSR &&
9135         (Inst.getOperand(0).getReg() == ARM::SP ||
9136          Inst.getOperand(1).getReg() == ARM::SP))
9137       return Match_RequiresV8;
9138   }
9139
9140   // Use of SP for VMRS/VMSR is only allowed in ARM mode with the exception of
9141   // ARMv8-A.
9142   if ((Inst.getOpcode() == ARM::VMRS || Inst.getOpcode() == ARM::VMSR) &&
9143       Inst.getOperand(0).getReg() == ARM::SP && (isThumb() && !hasV8Ops()))
9144     return Match_InvalidOperand;
9145
9146   for (unsigned I = 0; I < MCID.NumOperands; ++I)
9147     if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) {
9148       // rGPRRegClass excludes PC, and also excluded SP before ARMv8
9149       if ((Inst.getOperand(I).getReg() == ARM::SP) && !hasV8Ops())
9150         return Match_RequiresV8;
9151       else if (Inst.getOperand(I).getReg() == ARM::PC)
9152         return Match_InvalidOperand;
9153     }
9154
9155   return Match_Success;
9156 }
9157
9158 namespace llvm {
9159
9160 template <> inline bool IsCPSRDead<MCInst>(const MCInst *Instr) {
9161   return true; // In an assembly source, no need to second-guess
9162 }
9163
9164 } // end namespace llvm
9165
9166 // Returns true if Inst is unpredictable if it is in and IT block, but is not
9167 // the last instruction in the block.
9168 bool ARMAsmParser::isITBlockTerminator(MCInst &Inst) const {
9169   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
9170
9171   // All branch & call instructions terminate IT blocks with the exception of
9172   // SVC.
9173   if (MCID.isTerminator() || (MCID.isCall() && Inst.getOpcode() != ARM::tSVC) ||
9174       MCID.isReturn() || MCID.isBranch() || MCID.isIndirectBranch())
9175     return true;
9176
9177   // Any arithmetic instruction which writes to the PC also terminates the IT
9178   // block.
9179   if (MCID.hasDefOfPhysReg(Inst, ARM::PC, *MRI))
9180     return true;
9181
9182   return false;
9183 }
9184
9185 unsigned ARMAsmParser::MatchInstruction(OperandVector &Operands, MCInst &Inst,
9186                                           SmallVectorImpl<NearMissInfo> &NearMisses,
9187                                           bool MatchingInlineAsm,
9188                                           bool &EmitInITBlock,
9189                                           MCStreamer &Out) {
9190   // If we can't use an implicit IT block here, just match as normal.
9191   if (inExplicitITBlock() || !isThumbTwo() || !useImplicitITThumb())
9192     return MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm);
9193
9194   // Try to match the instruction in an extension of the current IT block (if
9195   // there is one).
9196   if (inImplicitITBlock()) {
9197     extendImplicitITBlock(ITState.Cond);
9198     if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) ==
9199             Match_Success) {
9200       // The match succeded, but we still have to check that the instruction is
9201       // valid in this implicit IT block.
9202       const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
9203       if (MCID.isPredicable()) {
9204         ARMCC::CondCodes InstCond =
9205             (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
9206                 .getImm();
9207         ARMCC::CondCodes ITCond = currentITCond();
9208         if (InstCond == ITCond) {
9209           EmitInITBlock = true;
9210           return Match_Success;
9211         } else if (InstCond == ARMCC::getOppositeCondition(ITCond)) {
9212           invertCurrentITCondition();
9213           EmitInITBlock = true;
9214           return Match_Success;
9215         }
9216       }
9217     }
9218     rewindImplicitITPosition();
9219   }
9220
9221   // Finish the current IT block, and try to match outside any IT block.
9222   flushPendingInstructions(Out);
9223   unsigned PlainMatchResult =
9224       MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm);
9225   if (PlainMatchResult == Match_Success) {
9226     const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
9227     if (MCID.isPredicable()) {
9228       ARMCC::CondCodes InstCond =
9229           (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
9230               .getImm();
9231       // Some forms of the branch instruction have their own condition code
9232       // fields, so can be conditionally executed without an IT block.
9233       if (Inst.getOpcode() == ARM::tBcc || Inst.getOpcode() == ARM::t2Bcc) {
9234         EmitInITBlock = false;
9235         return Match_Success;
9236       }
9237       if (InstCond == ARMCC::AL) {
9238         EmitInITBlock = false;
9239         return Match_Success;
9240       }
9241     } else {
9242       EmitInITBlock = false;
9243       return Match_Success;
9244     }
9245   }
9246
9247   // Try to match in a new IT block. The matcher doesn't check the actual
9248   // condition, so we create an IT block with a dummy condition, and fix it up
9249   // once we know the actual condition.
9250   startImplicitITBlock();
9251   if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) ==
9252       Match_Success) {
9253     const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
9254     if (MCID.isPredicable()) {
9255       ITState.Cond =
9256           (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
9257               .getImm();
9258       EmitInITBlock = true;
9259       return Match_Success;
9260     }
9261   }
9262   discardImplicitITBlock();
9263
9264   // If none of these succeed, return the error we got when trying to match
9265   // outside any IT blocks.
9266   EmitInITBlock = false;
9267   return PlainMatchResult;
9268 }
9269
9270 static std::string ARMMnemonicSpellCheck(StringRef S, uint64_t FBS,
9271                                          unsigned VariantID = 0);
9272
9273 static const char *getSubtargetFeatureName(uint64_t Val);
9274 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
9275                                            OperandVector &Operands,
9276                                            MCStreamer &Out, uint64_t &ErrorInfo,
9277                                            bool MatchingInlineAsm) {
9278   MCInst Inst;
9279   unsigned MatchResult;
9280   bool PendConditionalInstruction = false;
9281
9282   SmallVector<NearMissInfo, 4> NearMisses;
9283   MatchResult = MatchInstruction(Operands, Inst, NearMisses, MatchingInlineAsm,
9284                                  PendConditionalInstruction, Out);
9285
9286   switch (MatchResult) {
9287   case Match_Success:
9288     LLVM_DEBUG(dbgs() << "Parsed as: ";
9289                Inst.dump_pretty(dbgs(), MII.getName(Inst.getOpcode()));
9290                dbgs() << "\n");
9291
9292     // Context sensitive operand constraints aren't handled by the matcher,
9293     // so check them here.
9294     if (validateInstruction(Inst, Operands)) {
9295       // Still progress the IT block, otherwise one wrong condition causes
9296       // nasty cascading errors.
9297       forwardITPosition();
9298       return true;
9299     }
9300
9301     { // processInstruction() updates inITBlock state, we need to save it away
9302       bool wasInITBlock = inITBlock();
9303
9304       // Some instructions need post-processing to, for example, tweak which
9305       // encoding is selected. Loop on it while changes happen so the
9306       // individual transformations can chain off each other. E.g.,
9307       // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
9308       while (processInstruction(Inst, Operands, Out))
9309         LLVM_DEBUG(dbgs() << "Changed to: ";
9310                    Inst.dump_pretty(dbgs(), MII.getName(Inst.getOpcode()));
9311                    dbgs() << "\n");
9312
9313       // Only after the instruction is fully processed, we can validate it
9314       if (wasInITBlock && hasV8Ops() && isThumb() &&
9315           !isV8EligibleForIT(&Inst)) {
9316         Warning(IDLoc, "deprecated instruction in IT block");
9317       }
9318     }
9319
9320     // Only move forward at the very end so that everything in validate
9321     // and process gets a consistent answer about whether we're in an IT
9322     // block.
9323     forwardITPosition();
9324
9325     // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
9326     // doesn't actually encode.
9327     if (Inst.getOpcode() == ARM::ITasm)
9328       return false;
9329
9330     Inst.setLoc(IDLoc);
9331     if (PendConditionalInstruction) {
9332       PendingConditionalInsts.push_back(Inst);
9333       if (isITBlockFull() || isITBlockTerminator(Inst))
9334         flushPendingInstructions(Out);
9335     } else {
9336       Out.EmitInstruction(Inst, getSTI());
9337     }
9338     return false;
9339   case Match_NearMisses:
9340     ReportNearMisses(NearMisses, IDLoc, Operands);
9341     return true;
9342   case Match_MnemonicFail: {
9343     uint64_t FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
9344     std::string Suggestion = ARMMnemonicSpellCheck(
9345       ((ARMOperand &)*Operands[0]).getToken(), FBS);
9346     return Error(IDLoc, "invalid instruction" + Suggestion,
9347                  ((ARMOperand &)*Operands[0]).getLocRange());
9348   }
9349   }
9350
9351   llvm_unreachable("Implement any new match types added!");
9352 }
9353
9354 /// parseDirective parses the arm specific directives
9355 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
9356   const MCObjectFileInfo::Environment Format =
9357     getContext().getObjectFileInfo()->getObjectFileType();
9358   bool IsMachO = Format == MCObjectFileInfo::IsMachO;
9359   bool IsCOFF = Format == MCObjectFileInfo::IsCOFF;
9360
9361   StringRef IDVal = DirectiveID.getIdentifier();
9362   if (IDVal == ".word")
9363     parseLiteralValues(4, DirectiveID.getLoc());
9364   else if (IDVal == ".short" || IDVal == ".hword")
9365     parseLiteralValues(2, DirectiveID.getLoc());
9366   else if (IDVal == ".thumb")
9367     parseDirectiveThumb(DirectiveID.getLoc());
9368   else if (IDVal == ".arm")
9369     parseDirectiveARM(DirectiveID.getLoc());
9370   else if (IDVal == ".thumb_func")
9371     parseDirectiveThumbFunc(DirectiveID.getLoc());
9372   else if (IDVal == ".code")
9373     parseDirectiveCode(DirectiveID.getLoc());
9374   else if (IDVal == ".syntax")
9375     parseDirectiveSyntax(DirectiveID.getLoc());
9376   else if (IDVal == ".unreq")
9377     parseDirectiveUnreq(DirectiveID.getLoc());
9378   else if (IDVal == ".fnend")
9379     parseDirectiveFnEnd(DirectiveID.getLoc());
9380   else if (IDVal == ".cantunwind")
9381     parseDirectiveCantUnwind(DirectiveID.getLoc());
9382   else if (IDVal == ".personality")
9383     parseDirectivePersonality(DirectiveID.getLoc());
9384   else if (IDVal == ".handlerdata")
9385     parseDirectiveHandlerData(DirectiveID.getLoc());
9386   else if (IDVal == ".setfp")
9387     parseDirectiveSetFP(DirectiveID.getLoc());
9388   else if (IDVal == ".pad")
9389     parseDirectivePad(DirectiveID.getLoc());
9390   else if (IDVal == ".save")
9391     parseDirectiveRegSave(DirectiveID.getLoc(), false);
9392   else if (IDVal == ".vsave")
9393     parseDirectiveRegSave(DirectiveID.getLoc(), true);
9394   else if (IDVal == ".ltorg" || IDVal == ".pool")
9395     parseDirectiveLtorg(DirectiveID.getLoc());
9396   else if (IDVal == ".even")
9397     parseDirectiveEven(DirectiveID.getLoc());
9398   else if (IDVal == ".personalityindex")
9399     parseDirectivePersonalityIndex(DirectiveID.getLoc());
9400   else if (IDVal == ".unwind_raw")
9401     parseDirectiveUnwindRaw(DirectiveID.getLoc());
9402   else if (IDVal == ".movsp")
9403     parseDirectiveMovSP(DirectiveID.getLoc());
9404   else if (IDVal == ".arch_extension")
9405     parseDirectiveArchExtension(DirectiveID.getLoc());
9406   else if (IDVal == ".align")
9407     return parseDirectiveAlign(DirectiveID.getLoc()); // Use Generic on failure.
9408   else if (IDVal == ".thumb_set")
9409     parseDirectiveThumbSet(DirectiveID.getLoc());
9410   else if (IDVal == ".inst")
9411     parseDirectiveInst(DirectiveID.getLoc());
9412   else if (IDVal == ".inst.n")
9413     parseDirectiveInst(DirectiveID.getLoc(), 'n');
9414   else if (IDVal == ".inst.w")
9415     parseDirectiveInst(DirectiveID.getLoc(), 'w');
9416   else if (!IsMachO && !IsCOFF) {
9417     if (IDVal == ".arch")
9418       parseDirectiveArch(DirectiveID.getLoc());
9419     else if (IDVal == ".cpu")
9420       parseDirectiveCPU(DirectiveID.getLoc());
9421     else if (IDVal == ".eabi_attribute")
9422       parseDirectiveEabiAttr(DirectiveID.getLoc());
9423     else if (IDVal == ".fpu")
9424       parseDirectiveFPU(DirectiveID.getLoc());
9425     else if (IDVal == ".fnstart")
9426       parseDirectiveFnStart(DirectiveID.getLoc());
9427     else if (IDVal == ".object_arch")
9428       parseDirectiveObjectArch(DirectiveID.getLoc());
9429     else if (IDVal == ".tlsdescseq")
9430       parseDirectiveTLSDescSeq(DirectiveID.getLoc());
9431     else
9432       return true;
9433   } else
9434     return true;
9435   return false;
9436 }
9437
9438 /// parseLiteralValues
9439 ///  ::= .hword expression [, expression]*
9440 ///  ::= .short expression [, expression]*
9441 ///  ::= .word expression [, expression]*
9442 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
9443   auto parseOne = [&]() -> bool {
9444     const MCExpr *Value;
9445     if (getParser().parseExpression(Value))
9446       return true;
9447     getParser().getStreamer().EmitValue(Value, Size, L);
9448     return false;
9449   };
9450   return (parseMany(parseOne));
9451 }
9452
9453 /// parseDirectiveThumb
9454 ///  ::= .thumb
9455 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
9456   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive") ||
9457       check(!hasThumb(), L, "target does not support Thumb mode"))
9458     return true;
9459
9460   if (!isThumb())
9461     SwitchMode();
9462
9463   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
9464   return false;
9465 }
9466
9467 /// parseDirectiveARM
9468 ///  ::= .arm
9469 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
9470   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive") ||
9471       check(!hasARM(), L, "target does not support ARM mode"))
9472     return true;
9473
9474   if (isThumb())
9475     SwitchMode();
9476   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
9477   return false;
9478 }
9479
9480 void ARMAsmParser::doBeforeLabelEmit(MCSymbol *Symbol) {
9481   // We need to flush the current implicit IT block on a label, because it is
9482   // not legal to branch into an IT block.
9483   flushPendingInstructions(getStreamer());
9484 }
9485
9486 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
9487   if (NextSymbolIsThumb) {
9488     getParser().getStreamer().EmitThumbFunc(Symbol);
9489     NextSymbolIsThumb = false;
9490   }
9491 }
9492
9493 /// parseDirectiveThumbFunc
9494 ///  ::= .thumbfunc symbol_name
9495 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
9496   MCAsmParser &Parser = getParser();
9497   const auto Format = getContext().getObjectFileInfo()->getObjectFileType();
9498   bool IsMachO = Format == MCObjectFileInfo::IsMachO;
9499
9500   // Darwin asm has (optionally) function name after .thumb_func direction
9501   // ELF doesn't
9502
9503   if (IsMachO) {
9504     if (Parser.getTok().is(AsmToken::Identifier) ||
9505         Parser.getTok().is(AsmToken::String)) {
9506       MCSymbol *Func = getParser().getContext().getOrCreateSymbol(
9507           Parser.getTok().getIdentifier());
9508       getParser().getStreamer().EmitThumbFunc(Func);
9509       Parser.Lex();
9510       if (parseToken(AsmToken::EndOfStatement,
9511                      "unexpected token in '.thumb_func' directive"))
9512         return true;
9513       return false;
9514     }
9515   }
9516
9517   if (parseToken(AsmToken::EndOfStatement,
9518                  "unexpected token in '.thumb_func' directive"))
9519     return true;
9520
9521   NextSymbolIsThumb = true;
9522   return false;
9523 }
9524
9525 /// parseDirectiveSyntax
9526 ///  ::= .syntax unified | divided
9527 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
9528   MCAsmParser &Parser = getParser();
9529   const AsmToken &Tok = Parser.getTok();
9530   if (Tok.isNot(AsmToken::Identifier)) {
9531     Error(L, "unexpected token in .syntax directive");
9532     return false;
9533   }
9534
9535   StringRef Mode = Tok.getString();
9536   Parser.Lex();
9537   if (check(Mode == "divided" || Mode == "DIVIDED", L,
9538             "'.syntax divided' arm assembly not supported") ||
9539       check(Mode != "unified" && Mode != "UNIFIED", L,
9540             "unrecognized syntax mode in .syntax directive") ||
9541       parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
9542     return true;
9543
9544   // TODO tell the MC streamer the mode
9545   // getParser().getStreamer().Emit???();
9546   return false;
9547 }
9548
9549 /// parseDirectiveCode
9550 ///  ::= .code 16 | 32
9551 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
9552   MCAsmParser &Parser = getParser();
9553   const AsmToken &Tok = Parser.getTok();
9554   if (Tok.isNot(AsmToken::Integer))
9555     return Error(L, "unexpected token in .code directive");
9556   int64_t Val = Parser.getTok().getIntVal();
9557   if (Val != 16 && Val != 32) {
9558     Error(L, "invalid operand to .code directive");
9559     return false;
9560   }
9561   Parser.Lex();
9562
9563   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
9564     return true;
9565
9566   if (Val == 16) {
9567     if (!hasThumb())
9568       return Error(L, "target does not support Thumb mode");
9569
9570     if (!isThumb())
9571       SwitchMode();
9572     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
9573   } else {
9574     if (!hasARM())
9575       return Error(L, "target does not support ARM mode");
9576
9577     if (isThumb())
9578       SwitchMode();
9579     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
9580   }
9581
9582   return false;
9583 }
9584
9585 /// parseDirectiveReq
9586 ///  ::= name .req registername
9587 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
9588   MCAsmParser &Parser = getParser();
9589   Parser.Lex(); // Eat the '.req' token.
9590   unsigned Reg;
9591   SMLoc SRegLoc, ERegLoc;
9592   if (check(ParseRegister(Reg, SRegLoc, ERegLoc), SRegLoc,
9593             "register name expected") ||
9594       parseToken(AsmToken::EndOfStatement,
9595                  "unexpected input in .req directive."))
9596     return true;
9597
9598   if (RegisterReqs.insert(std::make_pair(Name, Reg)).first->second != Reg)
9599     return Error(SRegLoc,
9600                  "redefinition of '" + Name + "' does not match original.");
9601
9602   return false;
9603 }
9604
9605 /// parseDirectiveUneq
9606 ///  ::= .unreq registername
9607 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
9608   MCAsmParser &Parser = getParser();
9609   if (Parser.getTok().isNot(AsmToken::Identifier))
9610     return Error(L, "unexpected input in .unreq directive.");
9611   RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
9612   Parser.Lex(); // Eat the identifier.
9613   if (parseToken(AsmToken::EndOfStatement,
9614                  "unexpected input in '.unreq' directive"))
9615     return true;
9616   return false;
9617 }
9618
9619 // After changing arch/CPU, try to put the ARM/Thumb mode back to what it was
9620 // before, if supported by the new target, or emit mapping symbols for the mode
9621 // switch.
9622 void ARMAsmParser::FixModeAfterArchChange(bool WasThumb, SMLoc Loc) {
9623   if (WasThumb != isThumb()) {
9624     if (WasThumb && hasThumb()) {
9625       // Stay in Thumb mode
9626       SwitchMode();
9627     } else if (!WasThumb && hasARM()) {
9628       // Stay in ARM mode
9629       SwitchMode();
9630     } else {
9631       // Mode switch forced, because the new arch doesn't support the old mode.
9632       getParser().getStreamer().EmitAssemblerFlag(isThumb() ? MCAF_Code16
9633                                                             : MCAF_Code32);
9634       // Warn about the implcit mode switch. GAS does not switch modes here,
9635       // but instead stays in the old mode, reporting an error on any following
9636       // instructions as the mode does not exist on the target.
9637       Warning(Loc, Twine("new target does not support ") +
9638                        (WasThumb ? "thumb" : "arm") + " mode, switching to " +
9639                        (!WasThumb ? "thumb" : "arm") + " mode");
9640     }
9641   }
9642 }
9643
9644 /// parseDirectiveArch
9645 ///  ::= .arch token
9646 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
9647   StringRef Arch = getParser().parseStringToEndOfStatement().trim();
9648   ARM::ArchKind ID = ARM::parseArch(Arch);
9649
9650   if (ID == ARM::ArchKind::INVALID)
9651     return Error(L, "Unknown arch name");
9652
9653   bool WasThumb = isThumb();
9654   Triple T;
9655   MCSubtargetInfo &STI = copySTI();
9656   STI.setDefaultFeatures("", ("+" + ARM::getArchName(ID)).str());
9657   setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
9658   FixModeAfterArchChange(WasThumb, L);
9659
9660   getTargetStreamer().emitArch(ID);
9661   return false;
9662 }
9663
9664 /// parseDirectiveEabiAttr
9665 ///  ::= .eabi_attribute int, int [, "str"]
9666 ///  ::= .eabi_attribute Tag_name, int [, "str"]
9667 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
9668   MCAsmParser &Parser = getParser();
9669   int64_t Tag;
9670   SMLoc TagLoc;
9671   TagLoc = Parser.getTok().getLoc();
9672   if (Parser.getTok().is(AsmToken::Identifier)) {
9673     StringRef Name = Parser.getTok().getIdentifier();
9674     Tag = ARMBuildAttrs::AttrTypeFromString(Name);
9675     if (Tag == -1) {
9676       Error(TagLoc, "attribute name not recognised: " + Name);
9677       return false;
9678     }
9679     Parser.Lex();
9680   } else {
9681     const MCExpr *AttrExpr;
9682
9683     TagLoc = Parser.getTok().getLoc();
9684     if (Parser.parseExpression(AttrExpr))
9685       return true;
9686
9687     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
9688     if (check(!CE, TagLoc, "expected numeric constant"))
9689       return true;
9690
9691     Tag = CE->getValue();
9692   }
9693
9694   if (Parser.parseToken(AsmToken::Comma, "comma expected"))
9695     return true;
9696
9697   StringRef StringValue = "";
9698   bool IsStringValue = false;
9699
9700   int64_t IntegerValue = 0;
9701   bool IsIntegerValue = false;
9702
9703   if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
9704     IsStringValue = true;
9705   else if (Tag == ARMBuildAttrs::compatibility) {
9706     IsStringValue = true;
9707     IsIntegerValue = true;
9708   } else if (Tag < 32 || Tag % 2 == 0)
9709     IsIntegerValue = true;
9710   else if (Tag % 2 == 1)
9711     IsStringValue = true;
9712   else
9713     llvm_unreachable("invalid tag type");
9714
9715   if (IsIntegerValue) {
9716     const MCExpr *ValueExpr;
9717     SMLoc ValueExprLoc = Parser.getTok().getLoc();
9718     if (Parser.parseExpression(ValueExpr))
9719       return true;
9720
9721     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
9722     if (!CE)
9723       return Error(ValueExprLoc, "expected numeric constant");
9724     IntegerValue = CE->getValue();
9725   }
9726
9727   if (Tag == ARMBuildAttrs::compatibility) {
9728     if (Parser.parseToken(AsmToken::Comma, "comma expected"))
9729       return true;
9730   }
9731
9732   if (IsStringValue) {
9733     if (Parser.getTok().isNot(AsmToken::String))
9734       return Error(Parser.getTok().getLoc(), "bad string constant");
9735
9736     StringValue = Parser.getTok().getStringContents();
9737     Parser.Lex();
9738   }
9739
9740   if (Parser.parseToken(AsmToken::EndOfStatement,
9741                         "unexpected token in '.eabi_attribute' directive"))
9742     return true;
9743
9744   if (IsIntegerValue && IsStringValue) {
9745     assert(Tag == ARMBuildAttrs::compatibility);
9746     getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
9747   } else if (IsIntegerValue)
9748     getTargetStreamer().emitAttribute(Tag, IntegerValue);
9749   else if (IsStringValue)
9750     getTargetStreamer().emitTextAttribute(Tag, StringValue);
9751   return false;
9752 }
9753
9754 /// parseDirectiveCPU
9755 ///  ::= .cpu str
9756 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
9757   StringRef CPU = getParser().parseStringToEndOfStatement().trim();
9758   getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
9759
9760   // FIXME: This is using table-gen data, but should be moved to
9761   // ARMTargetParser once that is table-gen'd.
9762   if (!getSTI().isCPUStringValid(CPU))
9763     return Error(L, "Unknown CPU name");
9764
9765   bool WasThumb = isThumb();
9766   MCSubtargetInfo &STI = copySTI();
9767   STI.setDefaultFeatures(CPU, "");
9768   setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
9769   FixModeAfterArchChange(WasThumb, L);
9770
9771   return false;
9772 }
9773
9774 /// parseDirectiveFPU
9775 ///  ::= .fpu str
9776 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
9777   SMLoc FPUNameLoc = getTok().getLoc();
9778   StringRef FPU = getParser().parseStringToEndOfStatement().trim();
9779
9780   unsigned ID = ARM::parseFPU(FPU);
9781   std::vector<StringRef> Features;
9782   if (!ARM::getFPUFeatures(ID, Features))
9783     return Error(FPUNameLoc, "Unknown FPU name");
9784
9785   MCSubtargetInfo &STI = copySTI();
9786   for (auto Feature : Features)
9787     STI.ApplyFeatureFlag(Feature);
9788   setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
9789
9790   getTargetStreamer().emitFPU(ID);
9791   return false;
9792 }
9793
9794 /// parseDirectiveFnStart
9795 ///  ::= .fnstart
9796 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
9797   if (parseToken(AsmToken::EndOfStatement,
9798                  "unexpected token in '.fnstart' directive"))
9799     return true;
9800
9801   if (UC.hasFnStart()) {
9802     Error(L, ".fnstart starts before the end of previous one");
9803     UC.emitFnStartLocNotes();
9804     return true;
9805   }
9806
9807   // Reset the unwind directives parser state
9808   UC.reset();
9809
9810   getTargetStreamer().emitFnStart();
9811
9812   UC.recordFnStart(L);
9813   return false;
9814 }
9815
9816 /// parseDirectiveFnEnd
9817 ///  ::= .fnend
9818 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
9819   if (parseToken(AsmToken::EndOfStatement,
9820                  "unexpected token in '.fnend' directive"))
9821     return true;
9822   // Check the ordering of unwind directives
9823   if (!UC.hasFnStart())
9824     return Error(L, ".fnstart must precede .fnend directive");
9825
9826   // Reset the unwind directives parser state
9827   getTargetStreamer().emitFnEnd();
9828
9829   UC.reset();
9830   return false;
9831 }
9832
9833 /// parseDirectiveCantUnwind
9834 ///  ::= .cantunwind
9835 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
9836   if (parseToken(AsmToken::EndOfStatement,
9837                  "unexpected token in '.cantunwind' directive"))
9838     return true;
9839
9840   UC.recordCantUnwind(L);
9841   // Check the ordering of unwind directives
9842   if (check(!UC.hasFnStart(), L, ".fnstart must precede .cantunwind directive"))
9843     return true;
9844
9845   if (UC.hasHandlerData()) {
9846     Error(L, ".cantunwind can't be used with .handlerdata directive");
9847     UC.emitHandlerDataLocNotes();
9848     return true;
9849   }
9850   if (UC.hasPersonality()) {
9851     Error(L, ".cantunwind can't be used with .personality directive");
9852     UC.emitPersonalityLocNotes();
9853     return true;
9854   }
9855
9856   getTargetStreamer().emitCantUnwind();
9857   return false;
9858 }
9859
9860 /// parseDirectivePersonality
9861 ///  ::= .personality name
9862 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
9863   MCAsmParser &Parser = getParser();
9864   bool HasExistingPersonality = UC.hasPersonality();
9865
9866   // Parse the name of the personality routine
9867   if (Parser.getTok().isNot(AsmToken::Identifier))
9868     return Error(L, "unexpected input in .personality directive.");
9869   StringRef Name(Parser.getTok().getIdentifier());
9870   Parser.Lex();
9871
9872   if (parseToken(AsmToken::EndOfStatement,
9873                  "unexpected token in '.personality' directive"))
9874     return true;
9875
9876   UC.recordPersonality(L);
9877
9878   // Check the ordering of unwind directives
9879   if (!UC.hasFnStart())
9880     return Error(L, ".fnstart must precede .personality directive");
9881   if (UC.cantUnwind()) {
9882     Error(L, ".personality can't be used with .cantunwind directive");
9883     UC.emitCantUnwindLocNotes();
9884     return true;
9885   }
9886   if (UC.hasHandlerData()) {
9887     Error(L, ".personality must precede .handlerdata directive");
9888     UC.emitHandlerDataLocNotes();
9889     return true;
9890   }
9891   if (HasExistingPersonality) {
9892     Error(L, "multiple personality directives");
9893     UC.emitPersonalityLocNotes();
9894     return true;
9895   }
9896
9897   MCSymbol *PR = getParser().getContext().getOrCreateSymbol(Name);
9898   getTargetStreamer().emitPersonality(PR);
9899   return false;
9900 }
9901
9902 /// parseDirectiveHandlerData
9903 ///  ::= .handlerdata
9904 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
9905   if (parseToken(AsmToken::EndOfStatement,
9906                  "unexpected token in '.handlerdata' directive"))
9907     return true;
9908
9909   UC.recordHandlerData(L);
9910   // Check the ordering of unwind directives
9911   if (!UC.hasFnStart())
9912     return Error(L, ".fnstart must precede .personality directive");
9913   if (UC.cantUnwind()) {
9914     Error(L, ".handlerdata can't be used with .cantunwind directive");
9915     UC.emitCantUnwindLocNotes();
9916     return true;
9917   }
9918
9919   getTargetStreamer().emitHandlerData();
9920   return false;
9921 }
9922
9923 /// parseDirectiveSetFP
9924 ///  ::= .setfp fpreg, spreg [, offset]
9925 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
9926   MCAsmParser &Parser = getParser();
9927   // Check the ordering of unwind directives
9928   if (check(!UC.hasFnStart(), L, ".fnstart must precede .setfp directive") ||
9929       check(UC.hasHandlerData(), L,
9930             ".setfp must precede .handlerdata directive"))
9931     return true;
9932
9933   // Parse fpreg
9934   SMLoc FPRegLoc = Parser.getTok().getLoc();
9935   int FPReg = tryParseRegister();
9936
9937   if (check(FPReg == -1, FPRegLoc, "frame pointer register expected") ||
9938       Parser.parseToken(AsmToken::Comma, "comma expected"))
9939     return true;
9940
9941   // Parse spreg
9942   SMLoc SPRegLoc = Parser.getTok().getLoc();
9943   int SPReg = tryParseRegister();
9944   if (check(SPReg == -1, SPRegLoc, "stack pointer register expected") ||
9945       check(SPReg != ARM::SP && SPReg != UC.getFPReg(), SPRegLoc,
9946             "register should be either $sp or the latest fp register"))
9947     return true;
9948
9949   // Update the frame pointer register
9950   UC.saveFPReg(FPReg);
9951
9952   // Parse offset
9953   int64_t Offset = 0;
9954   if (Parser.parseOptionalToken(AsmToken::Comma)) {
9955     if (Parser.getTok().isNot(AsmToken::Hash) &&
9956         Parser.getTok().isNot(AsmToken::Dollar))
9957       return Error(Parser.getTok().getLoc(), "'#' expected");
9958     Parser.Lex(); // skip hash token.
9959
9960     const MCExpr *OffsetExpr;
9961     SMLoc ExLoc = Parser.getTok().getLoc();
9962     SMLoc EndLoc;
9963     if (getParser().parseExpression(OffsetExpr, EndLoc))
9964       return Error(ExLoc, "malformed setfp offset");
9965     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9966     if (check(!CE, ExLoc, "setfp offset must be an immediate"))
9967       return true;
9968     Offset = CE->getValue();
9969   }
9970
9971   if (Parser.parseToken(AsmToken::EndOfStatement))
9972     return true;
9973
9974   getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
9975                                 static_cast<unsigned>(SPReg), Offset);
9976   return false;
9977 }
9978
9979 /// parseDirective
9980 ///  ::= .pad offset
9981 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
9982   MCAsmParser &Parser = getParser();
9983   // Check the ordering of unwind directives
9984   if (!UC.hasFnStart())
9985     return Error(L, ".fnstart must precede .pad directive");
9986   if (UC.hasHandlerData())
9987     return Error(L, ".pad must precede .handlerdata directive");
9988
9989   // Parse the offset
9990   if (Parser.getTok().isNot(AsmToken::Hash) &&
9991       Parser.getTok().isNot(AsmToken::Dollar))
9992     return Error(Parser.getTok().getLoc(), "'#' expected");
9993   Parser.Lex(); // skip hash token.
9994
9995   const MCExpr *OffsetExpr;
9996   SMLoc ExLoc = Parser.getTok().getLoc();
9997   SMLoc EndLoc;
9998   if (getParser().parseExpression(OffsetExpr, EndLoc))
9999     return Error(ExLoc, "malformed pad offset");
10000   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
10001   if (!CE)
10002     return Error(ExLoc, "pad offset must be an immediate");
10003
10004   if (parseToken(AsmToken::EndOfStatement,
10005                  "unexpected token in '.pad' directive"))
10006     return true;
10007
10008   getTargetStreamer().emitPad(CE->getValue());
10009   return false;
10010 }
10011
10012 /// parseDirectiveRegSave
10013 ///  ::= .save  { registers }
10014 ///  ::= .vsave { registers }
10015 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
10016   // Check the ordering of unwind directives
10017   if (!UC.hasFnStart())
10018     return Error(L, ".fnstart must precede .save or .vsave directives");
10019   if (UC.hasHandlerData())
10020     return Error(L, ".save or .vsave must precede .handlerdata directive");
10021
10022   // RAII object to make sure parsed operands are deleted.
10023   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
10024
10025   // Parse the register list
10026   if (parseRegisterList(Operands) ||
10027       parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
10028     return true;
10029   ARMOperand &Op = (ARMOperand &)*Operands[0];
10030   if (!IsVector && !Op.isRegList())
10031     return Error(L, ".save expects GPR registers");
10032   if (IsVector && !Op.isDPRRegList())
10033     return Error(L, ".vsave expects DPR registers");
10034
10035   getTargetStreamer().emitRegSave(Op.getRegList(), IsVector);
10036   return false;
10037 }
10038
10039 /// parseDirectiveInst
10040 ///  ::= .inst opcode [, ...]
10041 ///  ::= .inst.n opcode [, ...]
10042 ///  ::= .inst.w opcode [, ...]
10043 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
10044   int Width = 4;
10045
10046   if (isThumb()) {
10047     switch (Suffix) {
10048     case 'n':
10049       Width = 2;
10050       break;
10051     case 'w':
10052       break;
10053     default:
10054       Width = 0;
10055       break;
10056     }
10057   } else {
10058     if (Suffix)
10059       return Error(Loc, "width suffixes are invalid in ARM mode");
10060   }
10061
10062   auto parseOne = [&]() -> bool {
10063     const MCExpr *Expr;
10064     if (getParser().parseExpression(Expr))
10065       return true;
10066     const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
10067     if (!Value) {
10068       return Error(Loc, "expected constant expression");
10069     }
10070
10071     char CurSuffix = Suffix;
10072     switch (Width) {
10073     case 2:
10074       if (Value->getValue() > 0xffff)
10075         return Error(Loc, "inst.n operand is too big, use inst.w instead");
10076       break;
10077     case 4:
10078       if (Value->getValue() > 0xffffffff)
10079         return Error(Loc, StringRef(Suffix ? "inst.w" : "inst") +
10080                               " operand is too big");
10081       break;
10082     case 0:
10083       // Thumb mode, no width indicated. Guess from the opcode, if possible.
10084       if (Value->getValue() < 0xe800)
10085         CurSuffix = 'n';
10086       else if (Value->getValue() >= 0xe8000000)
10087         CurSuffix = 'w';
10088       else
10089         return Error(Loc, "cannot determine Thumb instruction size, "
10090                           "use inst.n/inst.w instead");
10091       break;
10092     default:
10093       llvm_unreachable("only supported widths are 2 and 4");
10094     }
10095
10096     getTargetStreamer().emitInst(Value->getValue(), CurSuffix);
10097     return false;
10098   };
10099
10100   if (parseOptionalToken(AsmToken::EndOfStatement))
10101     return Error(Loc, "expected expression following directive");
10102   if (parseMany(parseOne))
10103     return true;
10104   return false;
10105 }
10106
10107 /// parseDirectiveLtorg
10108 ///  ::= .ltorg | .pool
10109 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
10110   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
10111     return true;
10112   getTargetStreamer().emitCurrentConstantPool();
10113   return false;
10114 }
10115
10116 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
10117   const MCSection *Section = getStreamer().getCurrentSectionOnly();
10118
10119   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
10120     return true;
10121
10122   if (!Section) {
10123     getStreamer().InitSections(false);
10124     Section = getStreamer().getCurrentSectionOnly();
10125   }
10126
10127   assert(Section && "must have section to emit alignment");
10128   if (Section->UseCodeAlign())
10129     getStreamer().EmitCodeAlignment(2);
10130   else
10131     getStreamer().EmitValueToAlignment(2);
10132
10133   return false;
10134 }
10135
10136 /// parseDirectivePersonalityIndex
10137 ///   ::= .personalityindex index
10138 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
10139   MCAsmParser &Parser = getParser();
10140   bool HasExistingPersonality = UC.hasPersonality();
10141
10142   const MCExpr *IndexExpression;
10143   SMLoc IndexLoc = Parser.getTok().getLoc();
10144   if (Parser.parseExpression(IndexExpression) ||
10145       parseToken(AsmToken::EndOfStatement,
10146                  "unexpected token in '.personalityindex' directive")) {
10147     return true;
10148   }
10149
10150   UC.recordPersonalityIndex(L);
10151
10152   if (!UC.hasFnStart()) {
10153     return Error(L, ".fnstart must precede .personalityindex directive");
10154   }
10155   if (UC.cantUnwind()) {
10156     Error(L, ".personalityindex cannot be used with .cantunwind");
10157     UC.emitCantUnwindLocNotes();
10158     return true;
10159   }
10160   if (UC.hasHandlerData()) {
10161     Error(L, ".personalityindex must precede .handlerdata directive");
10162     UC.emitHandlerDataLocNotes();
10163     return true;
10164   }
10165   if (HasExistingPersonality) {
10166     Error(L, "multiple personality directives");
10167     UC.emitPersonalityLocNotes();
10168     return true;
10169   }
10170
10171   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
10172   if (!CE)
10173     return Error(IndexLoc, "index must be a constant number");
10174   if (CE->getValue() < 0 || CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX)
10175     return Error(IndexLoc,
10176                  "personality routine index should be in range [0-3]");
10177
10178   getTargetStreamer().emitPersonalityIndex(CE->getValue());
10179   return false;
10180 }
10181
10182 /// parseDirectiveUnwindRaw
10183 ///   ::= .unwind_raw offset, opcode [, opcode...]
10184 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
10185   MCAsmParser &Parser = getParser();
10186   int64_t StackOffset;
10187   const MCExpr *OffsetExpr;
10188   SMLoc OffsetLoc = getLexer().getLoc();
10189
10190   if (!UC.hasFnStart())
10191     return Error(L, ".fnstart must precede .unwind_raw directives");
10192   if (getParser().parseExpression(OffsetExpr))
10193     return Error(OffsetLoc, "expected expression");
10194
10195   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
10196   if (!CE)
10197     return Error(OffsetLoc, "offset must be a constant");
10198
10199   StackOffset = CE->getValue();
10200
10201   if (Parser.parseToken(AsmToken::Comma, "expected comma"))
10202     return true;
10203
10204   SmallVector<uint8_t, 16> Opcodes;
10205
10206   auto parseOne = [&]() -> bool {
10207     const MCExpr *OE;
10208     SMLoc OpcodeLoc = getLexer().getLoc();
10209     if (check(getLexer().is(AsmToken::EndOfStatement) ||
10210                   Parser.parseExpression(OE),
10211               OpcodeLoc, "expected opcode expression"))
10212       return true;
10213     const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
10214     if (!OC)
10215       return Error(OpcodeLoc, "opcode value must be a constant");
10216     const int64_t Opcode = OC->getValue();
10217     if (Opcode & ~0xff)
10218       return Error(OpcodeLoc, "invalid opcode");
10219     Opcodes.push_back(uint8_t(Opcode));
10220     return false;
10221   };
10222
10223   // Must have at least 1 element
10224   SMLoc OpcodeLoc = getLexer().getLoc();
10225   if (parseOptionalToken(AsmToken::EndOfStatement))
10226     return Error(OpcodeLoc, "expected opcode expression");
10227   if (parseMany(parseOne))
10228     return true;
10229
10230   getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
10231   return false;
10232 }
10233
10234 /// parseDirectiveTLSDescSeq
10235 ///   ::= .tlsdescseq tls-variable
10236 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
10237   MCAsmParser &Parser = getParser();
10238
10239   if (getLexer().isNot(AsmToken::Identifier))
10240     return TokError("expected variable after '.tlsdescseq' directive");
10241
10242   const MCSymbolRefExpr *SRE =
10243     MCSymbolRefExpr::create(Parser.getTok().getIdentifier(),
10244                             MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
10245   Lex();
10246
10247   if (parseToken(AsmToken::EndOfStatement,
10248                  "unexpected token in '.tlsdescseq' directive"))
10249     return true;
10250
10251   getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
10252   return false;
10253 }
10254
10255 /// parseDirectiveMovSP
10256 ///  ::= .movsp reg [, #offset]
10257 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
10258   MCAsmParser &Parser = getParser();
10259   if (!UC.hasFnStart())
10260     return Error(L, ".fnstart must precede .movsp directives");
10261   if (UC.getFPReg() != ARM::SP)
10262     return Error(L, "unexpected .movsp directive");
10263
10264   SMLoc SPRegLoc = Parser.getTok().getLoc();
10265   int SPReg = tryParseRegister();
10266   if (SPReg == -1)
10267     return Error(SPRegLoc, "register expected");
10268   if (SPReg == ARM::SP || SPReg == ARM::PC)
10269     return Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
10270
10271   int64_t Offset = 0;
10272   if (Parser.parseOptionalToken(AsmToken::Comma)) {
10273     if (Parser.parseToken(AsmToken::Hash, "expected #constant"))
10274       return true;
10275
10276     const MCExpr *OffsetExpr;
10277     SMLoc OffsetLoc = Parser.getTok().getLoc();
10278
10279     if (Parser.parseExpression(OffsetExpr))
10280       return Error(OffsetLoc, "malformed offset expression");
10281
10282     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
10283     if (!CE)
10284       return Error(OffsetLoc, "offset must be an immediate constant");
10285
10286     Offset = CE->getValue();
10287   }
10288
10289   if (parseToken(AsmToken::EndOfStatement,
10290                  "unexpected token in '.movsp' directive"))
10291     return true;
10292
10293   getTargetStreamer().emitMovSP(SPReg, Offset);
10294   UC.saveFPReg(SPReg);
10295
10296   return false;
10297 }
10298
10299 /// parseDirectiveObjectArch
10300 ///   ::= .object_arch name
10301 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
10302   MCAsmParser &Parser = getParser();
10303   if (getLexer().isNot(AsmToken::Identifier))
10304     return Error(getLexer().getLoc(), "unexpected token");
10305
10306   StringRef Arch = Parser.getTok().getString();
10307   SMLoc ArchLoc = Parser.getTok().getLoc();
10308   Lex();
10309
10310   ARM::ArchKind ID = ARM::parseArch(Arch);
10311
10312   if (ID == ARM::ArchKind::INVALID)
10313     return Error(ArchLoc, "unknown architecture '" + Arch + "'");
10314   if (parseToken(AsmToken::EndOfStatement))
10315     return true;
10316
10317   getTargetStreamer().emitObjectArch(ID);
10318   return false;
10319 }
10320
10321 /// parseDirectiveAlign
10322 ///   ::= .align
10323 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
10324   // NOTE: if this is not the end of the statement, fall back to the target
10325   // agnostic handling for this directive which will correctly handle this.
10326   if (parseOptionalToken(AsmToken::EndOfStatement)) {
10327     // '.align' is target specifically handled to mean 2**2 byte alignment.
10328     const MCSection *Section = getStreamer().getCurrentSectionOnly();
10329     assert(Section && "must have section to emit alignment");
10330     if (Section->UseCodeAlign())
10331       getStreamer().EmitCodeAlignment(4, 0);
10332     else
10333       getStreamer().EmitValueToAlignment(4, 0, 1, 0);
10334     return false;
10335   }
10336   return true;
10337 }
10338
10339 /// parseDirectiveThumbSet
10340 ///  ::= .thumb_set name, value
10341 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
10342   MCAsmParser &Parser = getParser();
10343
10344   StringRef Name;
10345   if (check(Parser.parseIdentifier(Name),
10346             "expected identifier after '.thumb_set'") ||
10347       parseToken(AsmToken::Comma, "expected comma after name '" + Name + "'"))
10348     return true;
10349
10350   MCSymbol *Sym;
10351   const MCExpr *Value;
10352   if (MCParserUtils::parseAssignmentExpression(Name, /* allow_redef */ true,
10353                                                Parser, Sym, Value))
10354     return true;
10355
10356   getTargetStreamer().emitThumbSet(Sym, Value);
10357   return false;
10358 }
10359
10360 /// Force static initialization.
10361 extern "C" void LLVMInitializeARMAsmParser() {
10362   RegisterMCAsmParser<ARMAsmParser> X(getTheARMLETarget());
10363   RegisterMCAsmParser<ARMAsmParser> Y(getTheARMBETarget());
10364   RegisterMCAsmParser<ARMAsmParser> A(getTheThumbLETarget());
10365   RegisterMCAsmParser<ARMAsmParser> B(getTheThumbBETarget());
10366 }
10367
10368 #define GET_REGISTER_MATCHER
10369 #define GET_SUBTARGET_FEATURE_NAME
10370 #define GET_MATCHER_IMPLEMENTATION
10371 #define GET_MNEMONIC_SPELL_CHECKER
10372 #include "ARMGenAsmMatcher.inc"
10373
10374 // Some diagnostics need to vary with subtarget features, so they are handled
10375 // here. For example, the DPR class has either 16 or 32 registers, depending
10376 // on the FPU available.
10377 const char *
10378 ARMAsmParser::getCustomOperandDiag(ARMMatchResultTy MatchError) {
10379   switch (MatchError) {
10380   // rGPR contains sp starting with ARMv8.
10381   case Match_rGPR:
10382     return hasV8Ops() ? "operand must be a register in range [r0, r14]"
10383                       : "operand must be a register in range [r0, r12] or r14";
10384   // DPR contains 16 registers for some FPUs, and 32 for others.
10385   case Match_DPR:
10386     return hasD16() ? "operand must be a register in range [d0, d15]"
10387                     : "operand must be a register in range [d0, d31]";
10388   case Match_DPR_RegList:
10389     return hasD16() ? "operand must be a list of registers in range [d0, d15]"
10390                     : "operand must be a list of registers in range [d0, d31]";
10391
10392   // For all other diags, use the static string from tablegen.
10393   default:
10394     return getMatchKindDiag(MatchError);
10395   }
10396 }
10397
10398 // Process the list of near-misses, throwing away ones we don't want to report
10399 // to the user, and converting the rest to a source location and string that
10400 // should be reported.
10401 void
10402 ARMAsmParser::FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn,
10403                                SmallVectorImpl<NearMissMessage> &NearMissesOut,
10404                                SMLoc IDLoc, OperandVector &Operands) {
10405   // TODO: If operand didn't match, sub in a dummy one and run target
10406   // predicate, so that we can avoid reporting near-misses that are invalid?
10407   // TODO: Many operand types dont have SuperClasses set, so we report
10408   // redundant ones.
10409   // TODO: Some operands are superclasses of registers (e.g.
10410   // MCK_RegShiftedImm), we don't have any way to represent that currently.
10411   // TODO: This is not all ARM-specific, can some of it be factored out?
10412
10413   // Record some information about near-misses that we have already seen, so
10414   // that we can avoid reporting redundant ones. For example, if there are
10415   // variants of an instruction that take 8- and 16-bit immediates, we want
10416   // to only report the widest one.
10417   std::multimap<unsigned, unsigned> OperandMissesSeen;
10418   SmallSet<uint64_t, 4> FeatureMissesSeen;
10419   bool ReportedTooFewOperands = false;
10420
10421   // Process the near-misses in reverse order, so that we see more general ones
10422   // first, and so can avoid emitting more specific ones.
10423   for (NearMissInfo &I : reverse(NearMissesIn)) {
10424     switch (I.getKind()) {
10425     case NearMissInfo::NearMissOperand: {
10426       SMLoc OperandLoc =
10427           ((ARMOperand &)*Operands[I.getOperandIndex()]).getStartLoc();
10428       const char *OperandDiag =
10429           getCustomOperandDiag((ARMMatchResultTy)I.getOperandError());
10430
10431       // If we have already emitted a message for a superclass, don't also report
10432       // the sub-class. We consider all operand classes that we don't have a
10433       // specialised diagnostic for to be equal for the propose of this check,
10434       // so that we don't report the generic error multiple times on the same
10435       // operand.
10436       unsigned DupCheckMatchClass = OperandDiag ? I.getOperandClass() : ~0U;
10437       auto PrevReports = OperandMissesSeen.equal_range(I.getOperandIndex());
10438       if (std::any_of(PrevReports.first, PrevReports.second,
10439                       [DupCheckMatchClass](
10440                           const std::pair<unsigned, unsigned> Pair) {
10441             if (DupCheckMatchClass == ~0U || Pair.second == ~0U)
10442               return Pair.second == DupCheckMatchClass;
10443             else
10444               return isSubclass((MatchClassKind)DupCheckMatchClass,
10445                                 (MatchClassKind)Pair.second);
10446           }))
10447         break;
10448       OperandMissesSeen.insert(
10449           std::make_pair(I.getOperandIndex(), DupCheckMatchClass));
10450
10451       NearMissMessage Message;
10452       Message.Loc = OperandLoc;
10453       if (OperandDiag) {
10454         Message.Message = OperandDiag;
10455       } else if (I.getOperandClass() == InvalidMatchClass) {
10456         Message.Message = "too many operands for instruction";
10457       } else {
10458         Message.Message = "invalid operand for instruction";
10459         LLVM_DEBUG(
10460             dbgs() << "Missing diagnostic string for operand class "
10461                    << getMatchClassName((MatchClassKind)I.getOperandClass())
10462                    << I.getOperandClass() << ", error " << I.getOperandError()
10463                    << ", opcode " << MII.getName(I.getOpcode()) << "\n");
10464       }
10465       NearMissesOut.emplace_back(Message);
10466       break;
10467     }
10468     case NearMissInfo::NearMissFeature: {
10469       uint64_t MissingFeatures = I.getFeatures();
10470       // Don't report the same set of features twice.
10471       if (FeatureMissesSeen.count(MissingFeatures))
10472         break;
10473       FeatureMissesSeen.insert(MissingFeatures);
10474
10475       // Special case: don't report a feature set which includes arm-mode for
10476       // targets that don't have ARM mode.
10477       if ((MissingFeatures & Feature_IsARM) && !hasARM())
10478         break;
10479       // Don't report any near-misses that both require switching instruction
10480       // set, and adding other subtarget features.
10481       if (isThumb() && (MissingFeatures & Feature_IsARM) &&
10482           (MissingFeatures & ~Feature_IsARM))
10483         break;
10484       if (!isThumb() && (MissingFeatures & Feature_IsThumb) &&
10485           (MissingFeatures & ~Feature_IsThumb))
10486         break;
10487       if (!isThumb() && (MissingFeatures & Feature_IsThumb2) &&
10488           (MissingFeatures & ~(Feature_IsThumb2 | Feature_IsThumb)))
10489         break;
10490       if (isMClass() && (MissingFeatures & Feature_HasNEON))
10491         break;
10492
10493       NearMissMessage Message;
10494       Message.Loc = IDLoc;
10495       raw_svector_ostream OS(Message.Message);
10496
10497       OS << "instruction requires:";
10498       uint64_t Mask = 1;
10499       for (unsigned MaskPos = 0; MaskPos < (sizeof(MissingFeatures) * 8 - 1);
10500            ++MaskPos) {
10501         if (MissingFeatures & Mask) {
10502           OS << " " << getSubtargetFeatureName(MissingFeatures & Mask);
10503         }
10504         Mask <<= 1;
10505       }
10506       NearMissesOut.emplace_back(Message);
10507
10508       break;
10509     }
10510     case NearMissInfo::NearMissPredicate: {
10511       NearMissMessage Message;
10512       Message.Loc = IDLoc;
10513       switch (I.getPredicateError()) {
10514       case Match_RequiresNotITBlock:
10515         Message.Message = "flag setting instruction only valid outside IT block";
10516         break;
10517       case Match_RequiresITBlock:
10518         Message.Message = "instruction only valid inside IT block";
10519         break;
10520       case Match_RequiresV6:
10521         Message.Message = "instruction variant requires ARMv6 or later";
10522         break;
10523       case Match_RequiresThumb2:
10524         Message.Message = "instruction variant requires Thumb2";
10525         break;
10526       case Match_RequiresV8:
10527         Message.Message = "instruction variant requires ARMv8 or later";
10528         break;
10529       case Match_RequiresFlagSetting:
10530         Message.Message = "no flag-preserving variant of this instruction available";
10531         break;
10532       case Match_InvalidOperand:
10533         Message.Message = "invalid operand for instruction";
10534         break;
10535       default:
10536         llvm_unreachable("Unhandled target predicate error");
10537         break;
10538       }
10539       NearMissesOut.emplace_back(Message);
10540       break;
10541     }
10542     case NearMissInfo::NearMissTooFewOperands: {
10543       if (!ReportedTooFewOperands) {
10544         SMLoc EndLoc = ((ARMOperand &)*Operands.back()).getEndLoc();
10545         NearMissesOut.emplace_back(NearMissMessage{
10546             EndLoc, StringRef("too few operands for instruction")});
10547         ReportedTooFewOperands = true;
10548       }
10549       break;
10550     }
10551     case NearMissInfo::NoNearMiss:
10552       // This should never leave the matcher.
10553       llvm_unreachable("not a near-miss");
10554       break;
10555     }
10556   }
10557 }
10558
10559 void ARMAsmParser::ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses,
10560                                     SMLoc IDLoc, OperandVector &Operands) {
10561   SmallVector<NearMissMessage, 4> Messages;
10562   FilterNearMisses(NearMisses, Messages, IDLoc, Operands);
10563
10564   if (Messages.size() == 0) {
10565     // No near-misses were found, so the best we can do is "invalid
10566     // instruction".
10567     Error(IDLoc, "invalid instruction");
10568   } else if (Messages.size() == 1) {
10569     // One near miss was found, report it as the sole error.
10570     Error(Messages[0].Loc, Messages[0].Message);
10571   } else {
10572     // More than one near miss, so report a generic "invalid instruction"
10573     // error, followed by notes for each of the near-misses.
10574     Error(IDLoc, "invalid instruction, any one of the following would fix this:");
10575     for (auto &M : Messages) {
10576       Note(M.Loc, M.Message);
10577     }
10578   }
10579 }
10580
10581 // FIXME: This structure should be moved inside ARMTargetParser
10582 // when we start to table-generate them, and we can use the ARM
10583 // flags below, that were generated by table-gen.
10584 static const struct {
10585   const unsigned Kind;
10586   const uint64_t ArchCheck;
10587   const FeatureBitset Features;
10588 } Extensions[] = {
10589   { ARM::AEK_CRC, Feature_HasV8, {ARM::FeatureCRC} },
10590   { ARM::AEK_CRYPTO,  Feature_HasV8,
10591     {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} },
10592   { ARM::AEK_FP, Feature_HasV8, {ARM::FeatureFPARMv8} },
10593   { (ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM), Feature_HasV7 | Feature_IsNotMClass,
10594     {ARM::FeatureHWDivThumb, ARM::FeatureHWDivARM} },
10595   { ARM::AEK_MP, Feature_HasV7 | Feature_IsNotMClass, {ARM::FeatureMP} },
10596   { ARM::AEK_SIMD, Feature_HasV8, {ARM::FeatureNEON, ARM::FeatureFPARMv8} },
10597   { ARM::AEK_SEC, Feature_HasV6K, {ARM::FeatureTrustZone} },
10598   // FIXME: Only available in A-class, isel not predicated
10599   { ARM::AEK_VIRT, Feature_HasV7, {ARM::FeatureVirtualization} },
10600   { ARM::AEK_FP16, Feature_HasV8_2a, {ARM::FeatureFPARMv8, ARM::FeatureFullFP16} },
10601   { ARM::AEK_RAS, Feature_HasV8, {ARM::FeatureRAS} },
10602   // FIXME: Unsupported extensions.
10603   { ARM::AEK_OS, Feature_None, {} },
10604   { ARM::AEK_IWMMXT, Feature_None, {} },
10605   { ARM::AEK_IWMMXT2, Feature_None, {} },
10606   { ARM::AEK_MAVERICK, Feature_None, {} },
10607   { ARM::AEK_XSCALE, Feature_None, {} },
10608 };
10609
10610 /// parseDirectiveArchExtension
10611 ///   ::= .arch_extension [no]feature
10612 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
10613   MCAsmParser &Parser = getParser();
10614
10615   if (getLexer().isNot(AsmToken::Identifier))
10616     return Error(getLexer().getLoc(), "expected architecture extension name");
10617
10618   StringRef Name = Parser.getTok().getString();
10619   SMLoc ExtLoc = Parser.getTok().getLoc();
10620   Lex();
10621
10622   if (parseToken(AsmToken::EndOfStatement,
10623                  "unexpected token in '.arch_extension' directive"))
10624     return true;
10625
10626   bool EnableFeature = true;
10627   if (Name.startswith_lower("no")) {
10628     EnableFeature = false;
10629     Name = Name.substr(2);
10630   }
10631   unsigned FeatureKind = ARM::parseArchExt(Name);
10632   if (FeatureKind == ARM::AEK_INVALID)
10633     return Error(ExtLoc, "unknown architectural extension: " + Name);
10634
10635   for (const auto &Extension : Extensions) {
10636     if (Extension.Kind != FeatureKind)
10637       continue;
10638
10639     if (Extension.Features.none())
10640       return Error(ExtLoc, "unsupported architectural extension: " + Name);
10641
10642     if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck)
10643       return Error(ExtLoc, "architectural extension '" + Name +
10644                                "' is not "
10645                                "allowed for the current base architecture");
10646
10647     MCSubtargetInfo &STI = copySTI();
10648     FeatureBitset ToggleFeatures = EnableFeature
10649       ? (~STI.getFeatureBits() & Extension.Features)
10650       : ( STI.getFeatureBits() & Extension.Features);
10651
10652     uint64_t Features =
10653         ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures));
10654     setAvailableFeatures(Features);
10655     return false;
10656   }
10657
10658   return Error(ExtLoc, "unknown architectural extension: " + Name);
10659 }
10660
10661 // Define this matcher function after the auto-generated include so we
10662 // have the match class enum definitions.
10663 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
10664                                                   unsigned Kind) {
10665   ARMOperand &Op = static_cast<ARMOperand &>(AsmOp);
10666   // If the kind is a token for a literal immediate, check if our asm
10667   // operand matches. This is for InstAliases which have a fixed-value
10668   // immediate in the syntax.
10669   switch (Kind) {
10670   default: break;
10671   case MCK__35_0:
10672     if (Op.isImm())
10673       if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
10674         if (CE->getValue() == 0)
10675           return Match_Success;
10676     break;
10677   case MCK_ModImm:
10678     if (Op.isImm()) {
10679       const MCExpr *SOExpr = Op.getImm();
10680       int64_t Value;
10681       if (!SOExpr->evaluateAsAbsolute(Value))
10682         return Match_Success;
10683       assert((Value >= std::numeric_limits<int32_t>::min() &&
10684               Value <= std::numeric_limits<uint32_t>::max()) &&
10685              "expression value must be representable in 32 bits");
10686     }
10687     break;
10688   case MCK_rGPR:
10689     if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP)
10690       return Match_Success;
10691     return Match_rGPR;
10692   case MCK_GPRPair:
10693     if (Op.isReg() &&
10694         MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
10695       return Match_Success;
10696     break;
10697   }
10698   return Match_InvalidOperand;
10699 }