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Revert r354244 "[DAGCombiner] Eliminate dead stores to stack."
[llvm-complete.git] / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob1ac1ade2f7e283d1a055bc6f72c2c1f1b393b0ae
1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "MCTargetDesc/ARMAddressingModes.h"
10 #include "MCTargetDesc/ARMBaseInfo.h"
11 #include "MCTargetDesc/ARMMCTargetDesc.h"
12 #include "Utils/ARMBaseInfo.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
15 #include "llvm/MC/MCFixedLenDisassembler.h"
16 #include "llvm/MC/MCInst.h"
17 #include "llvm/MC/MCInstrDesc.h"
18 #include "llvm/MC/MCSubtargetInfo.h"
19 #include "llvm/MC/SubtargetFeature.h"
20 #include "llvm/Support/Compiler.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Support/raw_ostream.h"
25 #include <algorithm>
26 #include <cassert>
27 #include <cstdint>
28 #include <vector>
29
30 using namespace llvm;
31
32 #define DEBUG_TYPE "arm-disassembler"
33
34 using DecodeStatus = MCDisassembler::DecodeStatus;
35
36 namespace {
37
38 // Handles the condition code status of instructions in IT blocks
39 class ITStatus
40 {
41 public:
42 // Returns the condition code for instruction in IT block
43 unsigned getITCC() {
44 unsigned CC = ARMCC::AL;
45 if (instrInITBlock())
46 CC = ITStates.back();
47 return CC;
48 }
49
50 // Advances the IT block state to the next T or E
51 void advanceITState() {
52 ITStates.pop_back();
53 }
54
55 // Returns true if the current instruction is in an IT block
56 bool instrInITBlock() {
57 return !ITStates.empty();
58 }
59
60 // Returns true if current instruction is the last instruction in an IT block
61 bool instrLastInITBlock() {
62 return ITStates.size() == 1;
63 }
64
65 // Called when decoding an IT instruction. Sets the IT state for the following
66 // instructions that for the IT block. Firstcond and Mask correspond to the
67 // fields in the IT instruction encoding.
68 void setITState(char Firstcond, char Mask) {
69 // (3 - the number of trailing zeros) is the number of then / else.
70 unsigned CondBit0 = Firstcond & 1;
71 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
72 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
73 assert(NumTZ <= 3 && "Invalid IT mask!");
74 // push condition codes onto the stack the correct order for the pops
75 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
76 bool T = ((Mask >> Pos) & 1) == CondBit0;
77 if (T)
78 ITStates.push_back(CCBits);
79 else
80 ITStates.push_back(CCBits ^ 1);
81 }
82 ITStates.push_back(CCBits);
83 }
84
85 private:
86 std::vector<unsigned char> ITStates;
87 };
88
89 /// ARM disassembler for all ARM platforms.
90 class ARMDisassembler : public MCDisassembler {
91 public:
92 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
93 MCDisassembler(STI, Ctx) {
94 }
95
96 ~ARMDisassembler() override = default;
97
98 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
99 ArrayRef<uint8_t> Bytes, uint64_t Address,
100 raw_ostream &VStream,
101 raw_ostream &CStream) const override;
102 };
103
104 /// Thumb disassembler for all Thumb platforms.
105 class ThumbDisassembler : public MCDisassembler {
106 public:
107 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
108 MCDisassembler(STI, Ctx) {
109 }
110
111 ~ThumbDisassembler() override = default;
112
113 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
114 ArrayRef<uint8_t> Bytes, uint64_t Address,
115 raw_ostream &VStream,
116 raw_ostream &CStream) const override;
117
118 private:
119 mutable ITStatus ITBlock;
120
121 DecodeStatus AddThumbPredicate(MCInst&) const;
122 void UpdateThumbVFPPredicate(MCInst&) const;
123 };
124
125 } // end anonymous namespace
126
127 static bool Check(DecodeStatus &Out, DecodeStatus In) {
128 switch (In) {
129 case MCDisassembler::Success:
130 // Out stays the same.
131 return true;
132 case MCDisassembler::SoftFail:
133 Out = In;
134 return true;
135 case MCDisassembler::Fail:
136 Out = In;
137 return false;
138 }
139 llvm_unreachable("Invalid DecodeStatus!");
140 }
141
142 // Forward declare these because the autogenerated code will reference them.
143 // Definitions are further down.
144 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
145 uint64_t Address, const void *Decoder);
146 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
147 unsigned RegNo, uint64_t Address,
148 const void *Decoder);
149 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
150 unsigned RegNo, uint64_t Address,
151 const void *Decoder);
152 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
153 uint64_t Address, const void *Decoder);
154 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
155 uint64_t Address, const void *Decoder);
156 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
157 uint64_t Address, const void *Decoder);
158 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
159 uint64_t Address, const void *Decoder);
160 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
161 uint64_t Address, const void *Decoder);
162 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
163 uint64_t Address, const void *Decoder);
164 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
165 uint64_t Address, const void *Decoder);
166 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
167 uint64_t Address, const void *Decoder);
168 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
169 unsigned RegNo,
170 uint64_t Address,
171 const void *Decoder);
172 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
173 uint64_t Address, const void *Decoder);
174 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
175 uint64_t Address, const void *Decoder);
176 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
177 unsigned RegNo, uint64_t Address,
178 const void *Decoder);
179
180 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
181 uint64_t Address, const void *Decoder);
182 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
183 uint64_t Address, const void *Decoder);
184 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
185 uint64_t Address, const void *Decoder);
186 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
187 uint64_t Address, const void *Decoder);
188 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
189 uint64_t Address, const void *Decoder);
190
191 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
192 uint64_t Address, const void *Decoder);
193 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
194 uint64_t Address, const void *Decoder);
195 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
196 unsigned Insn,
197 uint64_t Address,
198 const void *Decoder);
199 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
200 uint64_t Address, const void *Decoder);
201 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
202 uint64_t Address, const void *Decoder);
203 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
204 uint64_t Address, const void *Decoder);
205 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
206 uint64_t Address, const void *Decoder);
207
208 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
209 unsigned Insn,
210 uint64_t Adddress,
211 const void *Decoder);
212 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
213 uint64_t Address, const void *Decoder);
214 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
215 uint64_t Address, const void *Decoder);
216 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
217 uint64_t Address, const void *Decoder);
218 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
219 uint64_t Address, const void *Decoder);
220 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
221 uint64_t Address, const void *Decoder);
222 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
223 uint64_t Address, const void *Decoder);
224 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
225 uint64_t Address, const void *Decoder);
226 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
227 uint64_t Address, const void *Decoder);
228 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
229 uint64_t Address, const void *Decoder);
230 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
231 uint64_t Address, const void *Decoder);
232 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
233 uint64_t Address, const void *Decoder);
234 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
235 uint64_t Address, const void *Decoder);
236 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
237 uint64_t Address, const void *Decoder);
238 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
239 uint64_t Address, const void *Decoder);
240 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
241 uint64_t Address, const void *Decoder);
242 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
243 uint64_t Address, const void *Decoder);
244 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
245 uint64_t Address, const void *Decoder);
246 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
247 uint64_t Address, const void *Decoder);
248 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
249 uint64_t Address, const void *Decoder);
250 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
251 uint64_t Address, const void *Decoder);
252 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
253 uint64_t Address, const void *Decoder);
254 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
255 uint64_t Address, const void *Decoder);
256 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
257 uint64_t Address, const void *Decoder);
258 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
259 uint64_t Address, const void *Decoder);
260 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
261 uint64_t Address, const void *Decoder);
262 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
263 uint64_t Address, const void *Decoder);
264 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
265 uint64_t Address, const void *Decoder);
266 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
267 uint64_t Address, const void *Decoder);
268 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
269 uint64_t Address, const void *Decoder);
270 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
271 uint64_t Address, const void *Decoder);
272 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
273 uint64_t Address, const void *Decoder);
274 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
275 uint64_t Address, const void *Decoder);
276 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
277 uint64_t Address, const void *Decoder);
278 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
279 uint64_t Address, const void *Decoder);
280 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
281 uint64_t Address, const void *Decoder);
282 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
283 uint64_t Address, const void *Decoder);
284 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
285 uint64_t Address, const void *Decoder);
286 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
287 uint64_t Address, const void *Decoder);
288 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
289 uint64_t Address, const void *Decoder);
290 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
291 uint64_t Address, const void *Decoder);
292 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
293 uint64_t Address, const void *Decoder);
294 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
295 uint64_t Address, const void *Decoder);
296 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
297 uint64_t Address, const void *Decoder);
298 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
299 uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
301 uint64_t Address, const void *Decoder);
302 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
303 uint64_t Address, const void *Decoder);
304 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
305 uint64_t Address, const void *Decoder);
306 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
307 uint64_t Address, const void *Decoder);
308 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
309 uint64_t Address, const void *Decoder);
310 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
311 uint64_t Address, const void *Decoder);
312 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
313 uint64_t Address, const void *Decoder);
314 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
315 uint64_t Address, const void *Decoder);
316 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
317 uint64_t Address, const void *Decoder);
318 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
319 uint64_t Address, const void *Decoder);
320 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
321 uint64_t Address, const void *Decoder);
322 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
323 uint64_t Address, const void *Decoder);
324 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
325 uint64_t Address, const void *Decoder);
326 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
327 unsigned Val,
328 uint64_t Address,
329 const void *Decoder);
330
331 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
332 uint64_t Address, const void *Decoder);
333 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
334 uint64_t Address, const void *Decoder);
335 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
336 uint64_t Address, const void *Decoder);
337 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
338 uint64_t Address, const void *Decoder);
339 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
340 uint64_t Address, const void *Decoder);
341 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
342 uint64_t Address, const void *Decoder);
343 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
344 uint64_t Address, const void *Decoder);
345 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
346 uint64_t Address, const void *Decoder);
347 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
348 uint64_t Address, const void *Decoder);
349 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
350 uint64_t Address, const void *Decoder);
351 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
352 uint64_t Address, const void* Decoder);
353 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
354 uint64_t Address, const void* Decoder);
355 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
356 uint64_t Address, const void* Decoder);
357 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
358 uint64_t Address, const void* Decoder);
359 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
360 uint64_t Address, const void *Decoder);
361 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
362 uint64_t Address, const void *Decoder);
363 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
364 uint64_t Address, const void *Decoder);
365 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
366 uint64_t Address, const void *Decoder);
367 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
368 uint64_t Address, const void *Decoder);
369 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
370 uint64_t Address, const void *Decoder);
371 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
372 uint64_t Address, const void *Decoder);
373 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
374 uint64_t Address, const void *Decoder);
375 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
376 uint64_t Address, const void *Decoder);
377 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
378 uint64_t Address, const void *Decoder);
379 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
380 uint64_t Address, const void *Decoder);
381 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
382 uint64_t Address, const void *Decoder);
383 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
384 uint64_t Address, const void *Decoder);
385 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
386 uint64_t Address, const void *Decoder);
387 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
388 uint64_t Address, const void *Decoder);
389 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
390 uint64_t Address, const void *Decoder);
391 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
392 uint64_t Address, const void *Decoder);
393 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
394 uint64_t Address, const void *Decoder);
395 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
396 uint64_t Address, const void *Decoder);
397 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
398 uint64_t Address, const void *Decoder);
399 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
400 uint64_t Address, const void *Decoder);
401 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
402 uint64_t Address, const void *Decoder);
403
404 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
405 uint64_t Address, const void *Decoder);
406 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
407 uint64_t Address, const void *Decoder);
408 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
409 uint64_t Address, const void *Decoder);
410
411 #include "ARMGenDisassemblerTables.inc"
412
413 static MCDisassembler *createARMDisassembler(const Target &T,
414 const MCSubtargetInfo &STI,
415 MCContext &Ctx) {
416 return new ARMDisassembler(STI, Ctx);
417 }
418
419 static MCDisassembler *createThumbDisassembler(const Target &T,
420 const MCSubtargetInfo &STI,
421 MCContext &Ctx) {
422 return new ThumbDisassembler(STI, Ctx);
423 }
424
425 // Post-decoding checks
426 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
427 uint64_t Address, raw_ostream &OS,
428 raw_ostream &CS,
429 uint32_t Insn,
430 DecodeStatus Result) {
431 switch (MI.getOpcode()) {
432 case ARM::HVC: {
433 // HVC is undefined if condition = 0xf otherwise upredictable
434 // if condition != 0xe
435 uint32_t Cond = (Insn >> 28) & 0xF;
436 if (Cond == 0xF)
437 return MCDisassembler::Fail;
438 if (Cond != 0xE)
439 return MCDisassembler::SoftFail;
440 return Result;
441 }
442 default: return Result;
443 }
444 }
445
446 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
447 ArrayRef<uint8_t> Bytes,
448 uint64_t Address, raw_ostream &OS,
449 raw_ostream &CS) const {
450 CommentStream = &CS;
451
452 assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
453 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
454 "mode!");
455
456 // We want to read exactly 4 bytes of data.
457 if (Bytes.size() < 4) {
458 Size = 0;
459 return MCDisassembler::Fail;
460 }
461
462 // Encoded as a small-endian 32-bit word in the stream.
463 uint32_t Insn =
464 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
465
466 // Calling the auto-generated decoder function.
467 DecodeStatus Result =
468 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
469 if (Result != MCDisassembler::Fail) {
470 Size = 4;
471 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
472 }
473
474 struct DecodeTable {
475 const uint8_t *P;
476 bool DecodePred;
477 };
478
479 const DecodeTable Tables[] = {
480 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false},
481 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true},
482 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false},
483 {DecoderTablev8Crypto32, false},
484 };
485
486 for (auto Table : Tables) {
487 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI);
488 if (Result != MCDisassembler::Fail) {
489 Size = 4;
490 // Add a fake predicate operand, because we share these instruction
491 // definitions with Thumb2 where these instructions are predicable.
492 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this))
493 return MCDisassembler::Fail;
494 return Result;
495 }
496 }
497
498 Result =
499 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);
500 if (Result != MCDisassembler::Fail) {
501 Size = 4;
502 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
503 }
504
505 Size = 4;
506 return MCDisassembler::Fail;
507 }
508
509 namespace llvm {
510
511 extern const MCInstrDesc ARMInsts[];
512
513 } // end namespace llvm
514
515 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
516 /// immediate Value in the MCInst. The immediate Value has had any PC
517 /// adjustment made by the caller. If the instruction is a branch instruction
518 /// then isBranch is true, else false. If the getOpInfo() function was set as
519 /// part of the setupForSymbolicDisassembly() call then that function is called
520 /// to get any symbolic information at the Address for this instruction. If
521 /// that returns non-zero then the symbolic information it returns is used to
522 /// create an MCExpr and that is added as an operand to the MCInst. If
523 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
524 /// Value is done and if a symbol is found an MCExpr is created with that, else
525 /// an MCExpr with Value is created. This function returns true if it adds an
526 /// operand to the MCInst and false otherwise.
527 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
528 bool isBranch, uint64_t InstSize,
529 MCInst &MI, const void *Decoder) {
530 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
531 // FIXME: Does it make sense for value to be negative?
532 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
533 /* Offset */ 0, InstSize);
534 }
535
536 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
537 /// referenced by a load instruction with the base register that is the Pc.
538 /// These can often be values in a literal pool near the Address of the
539 /// instruction. The Address of the instruction and its immediate Value are
540 /// used as a possible literal pool entry. The SymbolLookUp call back will
541 /// return the name of a symbol referenced by the literal pool's entry if
542 /// the referenced address is that of a symbol. Or it will return a pointer to
543 /// a literal 'C' string if the referenced address of the literal pool's entry
544 /// is an address into a section with 'C' string literals.
545 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
546 const void *Decoder) {
547 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
548 Dis->tryAddingPcLoadReferenceComment(Value, Address);
549 }
550
551 // Thumb1 instructions don't have explicit S bits. Rather, they
552 // implicitly set CPSR. Since it's not represented in the encoding, the
553 // auto-generated decoder won't inject the CPSR operand. We need to fix
554 // that as a post-pass.
555 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
556 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
557 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
558 MCInst::iterator I = MI.begin();
559 for (unsigned i = 0; i < NumOps; ++i, ++I) {
560 if (I == MI.end()) break;
561 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
562 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
563 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
564 return;
565 }
566 }
567
568 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
569 }
570
571 // Most Thumb instructions don't have explicit predicates in the
572 // encoding, but rather get their predicates from IT context. We need
573 // to fix up the predicate operands using this context information as a
574 // post-pass.
575 MCDisassembler::DecodeStatus
576 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
577 MCDisassembler::DecodeStatus S = Success;
578
579 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
580
581 // A few instructions actually have predicates encoded in them. Don't
582 // try to overwrite it if we're seeing one of those.
583 switch (MI.getOpcode()) {
584 case ARM::tBcc:
585 case ARM::t2Bcc:
586 case ARM::tCBZ:
587 case ARM::tCBNZ:
588 case ARM::tCPS:
589 case ARM::t2CPS3p:
590 case ARM::t2CPS2p:
591 case ARM::t2CPS1p:
592 case ARM::tMOVSr:
593 case ARM::tSETEND:
594 // Some instructions (mostly conditional branches) are not
595 // allowed in IT blocks.
596 if (ITBlock.instrInITBlock())
597 S = SoftFail;
598 else
599 return Success;
600 break;
601 case ARM::t2HINT:
602 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
603 S = SoftFail;
604 break;
605 case ARM::tB:
606 case ARM::t2B:
607 case ARM::t2TBB:
608 case ARM::t2TBH:
609 // Some instructions (mostly unconditional branches) can
610 // only appears at the end of, or outside of, an IT.
611 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
612 S = SoftFail;
613 break;
614 default:
615 break;
616 }
617
618 // If we're in an IT block, base the predicate on that. Otherwise,
619 // assume a predicate of AL.
620 unsigned CC;
621 CC = ITBlock.getITCC();
622 if (CC == 0xF)
623 CC = ARMCC::AL;
624 if (ITBlock.instrInITBlock())
625 ITBlock.advanceITState();
626
627 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
628 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
629 MCInst::iterator I = MI.begin();
630 for (unsigned i = 0; i < NumOps; ++i, ++I) {
631 if (I == MI.end()) break;
632 if (OpInfo[i].isPredicate()) {
633 I = MI.insert(I, MCOperand::createImm(CC));
634 ++I;
635 if (CC == ARMCC::AL)
636 MI.insert(I, MCOperand::createReg(0));
637 else
638 MI.insert(I, MCOperand::createReg(ARM::CPSR));
639 return S;
640 }
641 }
642
643 I = MI.insert(I, MCOperand::createImm(CC));
644 ++I;
645 if (CC == ARMCC::AL)
646 MI.insert(I, MCOperand::createReg(0));
647 else
648 MI.insert(I, MCOperand::createReg(ARM::CPSR));
649
650 return S;
651 }
652
653 // Thumb VFP instructions are a special case. Because we share their
654 // encodings between ARM and Thumb modes, and they are predicable in ARM
655 // mode, the auto-generated decoder will give them an (incorrect)
656 // predicate operand. We need to rewrite these operands based on the IT
657 // context as a post-pass.
658 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
659 unsigned CC;
660 CC = ITBlock.getITCC();
661 if (CC == 0xF)
662 CC = ARMCC::AL;
663 if (ITBlock.instrInITBlock())
664 ITBlock.advanceITState();
665
666 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
667 MCInst::iterator I = MI.begin();
668 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
669 for (unsigned i = 0; i < NumOps; ++i, ++I) {
670 if (OpInfo[i].isPredicate() ) {
671 I->setImm(CC);
672 ++I;
673 if (CC == ARMCC::AL)
674 I->setReg(0);
675 else
676 I->setReg(ARM::CPSR);
677 return;
678 }
679 }
680 }
681
682 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
683 ArrayRef<uint8_t> Bytes,
684 uint64_t Address,
685 raw_ostream &OS,
686 raw_ostream &CS) const {
687 CommentStream = &CS;
688
689 assert(STI.getFeatureBits()[ARM::ModeThumb] &&
690 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
691
692 // We want to read exactly 2 bytes of data.
693 if (Bytes.size() < 2) {
694 Size = 0;
695 return MCDisassembler::Fail;
696 }
697
698 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
699 DecodeStatus Result =
700 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
701 if (Result != MCDisassembler::Fail) {
702 Size = 2;
703 Check(Result, AddThumbPredicate(MI));
704 return Result;
705 }
706
707 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
708 STI);
709 if (Result) {
710 Size = 2;
711 bool InITBlock = ITBlock.instrInITBlock();
712 Check(Result, AddThumbPredicate(MI));
713 AddThumb1SBit(MI, InITBlock);
714 return Result;
715 }
716
717 Result =
718 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
719 if (Result != MCDisassembler::Fail) {
720 Size = 2;
721
722 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
723 // the Thumb predicate.
724 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
725 Result = MCDisassembler::SoftFail;
726
727 Check(Result, AddThumbPredicate(MI));
728
729 // If we find an IT instruction, we need to parse its condition
730 // code and mask operands so that we can apply them correctly
731 // to the subsequent instructions.
732 if (MI.getOpcode() == ARM::t2IT) {
733 unsigned Firstcond = MI.getOperand(0).getImm();
734 unsigned Mask = MI.getOperand(1).getImm();
735 ITBlock.setITState(Firstcond, Mask);
736
737 // An IT instruction that would give a 'NV' predicate is unpredictable.
738 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask))
739 CS << "unpredictable IT predicate sequence";
740 }
741
742 return Result;
743 }
744
745 // We want to read exactly 4 bytes of data.
746 if (Bytes.size() < 4) {
747 Size = 0;
748 return MCDisassembler::Fail;
749 }
750
751 uint32_t Insn32 =
752 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
753 Result =
754 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
755 if (Result != MCDisassembler::Fail) {
756 Size = 4;
757 bool InITBlock = ITBlock.instrInITBlock();
758 Check(Result, AddThumbPredicate(MI));
759 AddThumb1SBit(MI, InITBlock);
760 return Result;
761 }
762
763 Result =
764 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
765 if (Result != MCDisassembler::Fail) {
766 Size = 4;
767 Check(Result, AddThumbPredicate(MI));
768 return Result;
769 }
770
771 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
772 Result =
773 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
774 if (Result != MCDisassembler::Fail) {
775 Size = 4;
776 UpdateThumbVFPPredicate(MI);
777 return Result;
778 }
779 }
780
781 Result =
782 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
783 if (Result != MCDisassembler::Fail) {
784 Size = 4;
785 return Result;
786 }
787
788 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
789 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
790 STI);
791 if (Result != MCDisassembler::Fail) {
792 Size = 4;
793 Check(Result, AddThumbPredicate(MI));
794 return Result;
795 }
796 }
797
798 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
799 uint32_t NEONLdStInsn = Insn32;
800 NEONLdStInsn &= 0xF0FFFFFF;
801 NEONLdStInsn |= 0x04000000;
802 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
803 Address, this, STI);
804 if (Result != MCDisassembler::Fail) {
805 Size = 4;
806 Check(Result, AddThumbPredicate(MI));
807 return Result;
808 }
809 }
810
811 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
812 uint32_t NEONDataInsn = Insn32;
813 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
814 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
815 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
816 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
817 Address, this, STI);
818 if (Result != MCDisassembler::Fail) {
819 Size = 4;
820 Check(Result, AddThumbPredicate(MI));
821 return Result;
822 }
823
824 uint32_t NEONCryptoInsn = Insn32;
825 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
826 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
827 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
828 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
829 Address, this, STI);
830 if (Result != MCDisassembler::Fail) {
831 Size = 4;
832 return Result;
833 }
834
835 uint32_t NEONv8Insn = Insn32;
836 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
837 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
838 this, STI);
839 if (Result != MCDisassembler::Fail) {
840 Size = 4;
841 return Result;
842 }
843 }
844
845 Result =
846 decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI);
847 if (Result != MCDisassembler::Fail) {
848 Size = 4;
849 Check(Result, AddThumbPredicate(MI));
850 return Result;
851 }
852
853 Size = 0;
854 return MCDisassembler::Fail;
855 }
856
857 extern "C" void LLVMInitializeARMDisassembler() {
858 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(),
859 createARMDisassembler);
860 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(),
861 createARMDisassembler);
862 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(),
863 createThumbDisassembler);
864 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(),
865 createThumbDisassembler);
866 }
867
868 static const uint16_t GPRDecoderTable[] = {
869 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
870 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
871 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
872 ARM::R12, ARM::SP, ARM::LR, ARM::PC
873 };
874
875 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
876 uint64_t Address, const void *Decoder) {
877 if (RegNo > 15)
878 return MCDisassembler::Fail;
879
880 unsigned Register = GPRDecoderTable[RegNo];
881 Inst.addOperand(MCOperand::createReg(Register));
882 return MCDisassembler::Success;
883 }
884
885 static DecodeStatus
886 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
887 uint64_t Address, const void *Decoder) {
888 DecodeStatus S = MCDisassembler::Success;
889
890 if (RegNo == 15)
891 S = MCDisassembler::SoftFail;
892
893 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
894
895 return S;
896 }
897
898 static DecodeStatus
899 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
900 uint64_t Address, const void *Decoder) {
901 DecodeStatus S = MCDisassembler::Success;
902
903 if (RegNo == 15)
904 {
905 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
906 return MCDisassembler::Success;
907 }
908
909 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
910 return S;
911 }
912
913 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
914 uint64_t Address, const void *Decoder) {
915 if (RegNo > 7)
916 return MCDisassembler::Fail;
917 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
918 }
919
920 static const uint16_t GPRPairDecoderTable[] = {
921 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
922 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
923 };
924
925 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
926 uint64_t Address, const void *Decoder) {
927 DecodeStatus S = MCDisassembler::Success;
928
929 if (RegNo > 13)
930 return MCDisassembler::Fail;
931
932 if ((RegNo & 1) || RegNo == 0xe)
933 S = MCDisassembler::SoftFail;
934
935 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
936 Inst.addOperand(MCOperand::createReg(RegisterPair));
937 return S;
938 }
939
940 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
941 uint64_t Address, const void *Decoder) {
942 unsigned Register = 0;
943 switch (RegNo) {
944 case 0:
945 Register = ARM::R0;
946 break;
947 case 1:
948 Register = ARM::R1;
949 break;
950 case 2:
951 Register = ARM::R2;
952 break;
953 case 3:
954 Register = ARM::R3;
955 break;
956 case 9:
957 Register = ARM::R9;
958 break;
959 case 12:
960 Register = ARM::R12;
961 break;
962 default:
963 return MCDisassembler::Fail;
964 }
965
966 Inst.addOperand(MCOperand::createReg(Register));
967 return MCDisassembler::Success;
968 }
969
970 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
971 uint64_t Address, const void *Decoder) {
972 DecodeStatus S = MCDisassembler::Success;
973
974 const FeatureBitset &featureBits =
975 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
976
977 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
978 S = MCDisassembler::SoftFail;
979
980 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
981 return S;
982 }
983
984 static const uint16_t SPRDecoderTable[] = {
985 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
986 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
987 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
988 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
989 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
990 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
991 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
992 ARM::S28, ARM::S29, ARM::S30, ARM::S31
993 };
994
995 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
996 uint64_t Address, const void *Decoder) {
997 if (RegNo > 31)
998 return MCDisassembler::Fail;
999
1000 unsigned Register = SPRDecoderTable[RegNo];
1001 Inst.addOperand(MCOperand::createReg(Register));
1002 return MCDisassembler::Success;
1003 }
1004
1005 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
1006 uint64_t Address, const void *Decoder) {
1007 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1008 }
1009
1010 static const uint16_t DPRDecoderTable[] = {
1011 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1012 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1013 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1014 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1015 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1016 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1017 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1018 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1019 };
1020
1021 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1022 uint64_t Address, const void *Decoder) {
1023 const FeatureBitset &featureBits =
1024 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1025
1026 bool hasD16 = featureBits[ARM::FeatureD16];
1027
1028 if (RegNo > 31 || (hasD16 && RegNo > 15))
1029 return MCDisassembler::Fail;
1030
1031 unsigned Register = DPRDecoderTable[RegNo];
1032 Inst.addOperand(MCOperand::createReg(Register));
1033 return MCDisassembler::Success;
1034 }
1035
1036 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1037 uint64_t Address, const void *Decoder) {
1038 if (RegNo > 7)
1039 return MCDisassembler::Fail;
1040 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1041 }
1042
1043 static DecodeStatus
1044 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1045 uint64_t Address, const void *Decoder) {
1046 if (RegNo > 15)
1047 return MCDisassembler::Fail;
1048 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1049 }
1050
1051 static const uint16_t QPRDecoderTable[] = {
1052 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1053 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1054 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1055 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1056 };
1057
1058 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1059 uint64_t Address, const void *Decoder) {
1060 if (RegNo > 31 || (RegNo & 1) != 0)
1061 return MCDisassembler::Fail;
1062 RegNo >>= 1;
1063
1064 unsigned Register = QPRDecoderTable[RegNo];
1065 Inst.addOperand(MCOperand::createReg(Register));
1066 return MCDisassembler::Success;
1067 }
1068
1069 static const uint16_t DPairDecoderTable[] = {
1070 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1071 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1072 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1073 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1074 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1075 ARM::Q15
1076 };
1077
1078 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1079 uint64_t Address, const void *Decoder) {
1080 if (RegNo > 30)
1081 return MCDisassembler::Fail;
1082
1083 unsigned Register = DPairDecoderTable[RegNo];
1084 Inst.addOperand(MCOperand::createReg(Register));
1085 return MCDisassembler::Success;
1086 }
1087
1088 static const uint16_t DPairSpacedDecoderTable[] = {
1089 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1090 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1091 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1092 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1093 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1094 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1095 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1096 ARM::D28_D30, ARM::D29_D31
1097 };
1098
1099 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1100 unsigned RegNo,
1101 uint64_t Address,
1102 const void *Decoder) {
1103 if (RegNo > 29)
1104 return MCDisassembler::Fail;
1105
1106 unsigned Register = DPairSpacedDecoderTable[RegNo];
1107 Inst.addOperand(MCOperand::createReg(Register));
1108 return MCDisassembler::Success;
1109 }
1110
1111 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1112 uint64_t Address, const void *Decoder) {
1113 if (Val == 0xF) return MCDisassembler::Fail;
1114 // AL predicate is not allowed on Thumb1 branches.
1115 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1116 return MCDisassembler::Fail;
1117 Inst.addOperand(MCOperand::createImm(Val));
1118 if (Val == ARMCC::AL) {
1119 Inst.addOperand(MCOperand::createReg(0));
1120 } else
1121 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1122 return MCDisassembler::Success;
1123 }
1124
1125 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1126 uint64_t Address, const void *Decoder) {
1127 if (Val)
1128 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1129 else
1130 Inst.addOperand(MCOperand::createReg(0));
1131 return MCDisassembler::Success;
1132 }
1133
1134 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1135 uint64_t Address, const void *Decoder) {
1136 DecodeStatus S = MCDisassembler::Success;
1137
1138 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1139 unsigned type = fieldFromInstruction(Val, 5, 2);
1140 unsigned imm = fieldFromInstruction(Val, 7, 5);
1141
1142 // Register-immediate
1143 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
1144 return MCDisassembler::Fail;
1145
1146 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1147 switch (type) {
1148 case 0:
1149 Shift = ARM_AM::lsl;
1150 break;
1151 case 1:
1152 Shift = ARM_AM::lsr;
1153 break;
1154 case 2:
1155 Shift = ARM_AM::asr;
1156 break;
1157 case 3:
1158 Shift = ARM_AM::ror;
1159 break;
1160 }
1161
1162 if (Shift == ARM_AM::ror && imm == 0)
1163 Shift = ARM_AM::rrx;
1164
1165 unsigned Op = Shift | (imm << 3);
1166 Inst.addOperand(MCOperand::createImm(Op));
1167
1168 return S;
1169 }
1170
1171 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1172 uint64_t Address, const void *Decoder) {
1173 DecodeStatus S = MCDisassembler::Success;
1174
1175 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1176 unsigned type = fieldFromInstruction(Val, 5, 2);
1177 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1178
1179 // Register-register
1180 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1181 return MCDisassembler::Fail;
1182 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1183 return MCDisassembler::Fail;
1184
1185 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1186 switch (type) {
1187 case 0:
1188 Shift = ARM_AM::lsl;
1189 break;
1190 case 1:
1191 Shift = ARM_AM::lsr;
1192 break;
1193 case 2:
1194 Shift = ARM_AM::asr;
1195 break;
1196 case 3:
1197 Shift = ARM_AM::ror;
1198 break;
1199 }
1200
1201 Inst.addOperand(MCOperand::createImm(Shift));
1202
1203 return S;
1204 }
1205
1206 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1207 uint64_t Address, const void *Decoder) {
1208 DecodeStatus S = MCDisassembler::Success;
1209
1210 bool NeedDisjointWriteback = false;
1211 unsigned WritebackReg = 0;
1212 switch (Inst.getOpcode()) {
1213 default:
1214 break;
1215 case ARM::LDMIA_UPD:
1216 case ARM::LDMDB_UPD:
1217 case ARM::LDMIB_UPD:
1218 case ARM::LDMDA_UPD:
1219 case ARM::t2LDMIA_UPD:
1220 case ARM::t2LDMDB_UPD:
1221 case ARM::t2STMIA_UPD:
1222 case ARM::t2STMDB_UPD:
1223 NeedDisjointWriteback = true;
1224 WritebackReg = Inst.getOperand(0).getReg();
1225 break;
1226 }
1227
1228 // Empty register lists are not allowed.
1229 if (Val == 0) return MCDisassembler::Fail;
1230 for (unsigned i = 0; i < 16; ++i) {
1231 if (Val & (1 << i)) {
1232 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1233 return MCDisassembler::Fail;
1234 // Writeback not allowed if Rn is in the target list.
1235 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1236 Check(S, MCDisassembler::SoftFail);
1237 }
1238 }
1239
1240 return S;
1241 }
1242
1243 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1244 uint64_t Address, const void *Decoder) {
1245 DecodeStatus S = MCDisassembler::Success;
1246
1247 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1248 unsigned regs = fieldFromInstruction(Val, 0, 8);
1249
1250 // In case of unpredictable encoding, tweak the operands.
1251 if (regs == 0 || (Vd + regs) > 32) {
1252 regs = Vd + regs > 32 ? 32 - Vd : regs;
1253 regs = std::max( 1u, regs);
1254 S = MCDisassembler::SoftFail;
1255 }
1256
1257 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1258 return MCDisassembler::Fail;
1259 for (unsigned i = 0; i < (regs - 1); ++i) {
1260 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1261 return MCDisassembler::Fail;
1262 }
1263
1264 return S;
1265 }
1266
1267 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1268 uint64_t Address, const void *Decoder) {
1269 DecodeStatus S = MCDisassembler::Success;
1270
1271 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1272 unsigned regs = fieldFromInstruction(Val, 1, 7);
1273
1274 // In case of unpredictable encoding, tweak the operands.
1275 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1276 regs = Vd + regs > 32 ? 32 - Vd : regs;
1277 regs = std::max( 1u, regs);
1278 regs = std::min(16u, regs);
1279 S = MCDisassembler::SoftFail;
1280 }
1281
1282 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1283 return MCDisassembler::Fail;
1284 for (unsigned i = 0; i < (regs - 1); ++i) {
1285 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1286 return MCDisassembler::Fail;
1287 }
1288
1289 return S;
1290 }
1291
1292 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1293 uint64_t Address, const void *Decoder) {
1294 // This operand encodes a mask of contiguous zeros between a specified MSB
1295 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1296 // the mask of all bits LSB-and-lower, and then xor them to create
1297 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1298 // create the final mask.
1299 unsigned msb = fieldFromInstruction(Val, 5, 5);
1300 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1301
1302 DecodeStatus S = MCDisassembler::Success;
1303 if (lsb > msb) {
1304 Check(S, MCDisassembler::SoftFail);
1305 // The check above will cause the warning for the "potentially undefined
1306 // instruction encoding" but we can't build a bad MCOperand value here
1307 // with a lsb > msb or else printing the MCInst will cause a crash.
1308 lsb = msb;
1309 }
1310
1311 uint32_t msb_mask = 0xFFFFFFFF;
1312 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1313 uint32_t lsb_mask = (1U << lsb) - 1;
1314
1315 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
1316 return S;
1317 }
1318
1319 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1320 uint64_t Address, const void *Decoder) {
1321 DecodeStatus S = MCDisassembler::Success;
1322
1323 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1324 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1325 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1326 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1327 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1328 unsigned U = fieldFromInstruction(Insn, 23, 1);
1329
1330 switch (Inst.getOpcode()) {
1331 case ARM::LDC_OFFSET:
1332 case ARM::LDC_PRE:
1333 case ARM::LDC_POST:
1334 case ARM::LDC_OPTION:
1335 case ARM::LDCL_OFFSET:
1336 case ARM::LDCL_PRE:
1337 case ARM::LDCL_POST:
1338 case ARM::LDCL_OPTION:
1339 case ARM::STC_OFFSET:
1340 case ARM::STC_PRE:
1341 case ARM::STC_POST:
1342 case ARM::STC_OPTION:
1343 case ARM::STCL_OFFSET:
1344 case ARM::STCL_PRE:
1345 case ARM::STCL_POST:
1346 case ARM::STCL_OPTION:
1347 case ARM::t2LDC_OFFSET:
1348 case ARM::t2LDC_PRE:
1349 case ARM::t2LDC_POST:
1350 case ARM::t2LDC_OPTION:
1351 case ARM::t2LDCL_OFFSET:
1352 case ARM::t2LDCL_PRE:
1353 case ARM::t2LDCL_POST:
1354 case ARM::t2LDCL_OPTION:
1355 case ARM::t2STC_OFFSET:
1356 case ARM::t2STC_PRE:
1357 case ARM::t2STC_POST:
1358 case ARM::t2STC_OPTION:
1359 case ARM::t2STCL_OFFSET:
1360 case ARM::t2STCL_PRE:
1361 case ARM::t2STCL_POST:
1362 case ARM::t2STCL_OPTION:
1363 if (coproc == 0xA || coproc == 0xB)
1364 return MCDisassembler::Fail;
1365 break;
1366 default:
1367 break;
1368 }
1369
1370 const FeatureBitset &featureBits =
1371 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1372 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1373 return MCDisassembler::Fail;
1374
1375 Inst.addOperand(MCOperand::createImm(coproc));
1376 Inst.addOperand(MCOperand::createImm(CRd));
1377 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1378 return MCDisassembler::Fail;
1379
1380 switch (Inst.getOpcode()) {
1381 case ARM::t2LDC2_OFFSET:
1382 case ARM::t2LDC2L_OFFSET:
1383 case ARM::t2LDC2_PRE:
1384 case ARM::t2LDC2L_PRE:
1385 case ARM::t2STC2_OFFSET:
1386 case ARM::t2STC2L_OFFSET:
1387 case ARM::t2STC2_PRE:
1388 case ARM::t2STC2L_PRE:
1389 case ARM::LDC2_OFFSET:
1390 case ARM::LDC2L_OFFSET:
1391 case ARM::LDC2_PRE:
1392 case ARM::LDC2L_PRE:
1393 case ARM::STC2_OFFSET:
1394 case ARM::STC2L_OFFSET:
1395 case ARM::STC2_PRE:
1396 case ARM::STC2L_PRE:
1397 case ARM::t2LDC_OFFSET:
1398 case ARM::t2LDCL_OFFSET:
1399 case ARM::t2LDC_PRE:
1400 case ARM::t2LDCL_PRE:
1401 case ARM::t2STC_OFFSET:
1402 case ARM::t2STCL_OFFSET:
1403 case ARM::t2STC_PRE:
1404 case ARM::t2STCL_PRE:
1405 case ARM::LDC_OFFSET:
1406 case ARM::LDCL_OFFSET:
1407 case ARM::LDC_PRE:
1408 case ARM::LDCL_PRE:
1409 case ARM::STC_OFFSET:
1410 case ARM::STCL_OFFSET:
1411 case ARM::STC_PRE:
1412 case ARM::STCL_PRE:
1413 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1414 Inst.addOperand(MCOperand::createImm(imm));
1415 break;
1416 case ARM::t2LDC2_POST:
1417 case ARM::t2LDC2L_POST:
1418 case ARM::t2STC2_POST:
1419 case ARM::t2STC2L_POST:
1420 case ARM::LDC2_POST:
1421 case ARM::LDC2L_POST:
1422 case ARM::STC2_POST:
1423 case ARM::STC2L_POST:
1424 case ARM::t2LDC_POST:
1425 case ARM::t2LDCL_POST:
1426 case ARM::t2STC_POST:
1427 case ARM::t2STCL_POST:
1428 case ARM::LDC_POST:
1429 case ARM::LDCL_POST:
1430 case ARM::STC_POST:
1431 case ARM::STCL_POST:
1432 imm |= U << 8;
1433 LLVM_FALLTHROUGH;
1434 default:
1435 // The 'option' variant doesn't encode 'U' in the immediate since
1436 // the immediate is unsigned [0,255].
1437 Inst.addOperand(MCOperand::createImm(imm));
1438 break;
1439 }
1440
1441 switch (Inst.getOpcode()) {
1442 case ARM::LDC_OFFSET:
1443 case ARM::LDC_PRE:
1444 case ARM::LDC_POST:
1445 case ARM::LDC_OPTION:
1446 case ARM::LDCL_OFFSET:
1447 case ARM::LDCL_PRE:
1448 case ARM::LDCL_POST:
1449 case ARM::LDCL_OPTION:
1450 case ARM::STC_OFFSET:
1451 case ARM::STC_PRE:
1452 case ARM::STC_POST:
1453 case ARM::STC_OPTION:
1454 case ARM::STCL_OFFSET:
1455 case ARM::STCL_PRE:
1456 case ARM::STCL_POST:
1457 case ARM::STCL_OPTION:
1458 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1459 return MCDisassembler::Fail;
1460 break;
1461 default:
1462 break;
1463 }
1464
1465 return S;
1466 }
1467
1468 static DecodeStatus
1469 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1470 uint64_t Address, const void *Decoder) {
1471 DecodeStatus S = MCDisassembler::Success;
1472
1473 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1474 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1475 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1476 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1477 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1478 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1479 unsigned P = fieldFromInstruction(Insn, 24, 1);
1480 unsigned W = fieldFromInstruction(Insn, 21, 1);
1481
1482 // On stores, the writeback operand precedes Rt.
1483 switch (Inst.getOpcode()) {
1484 case ARM::STR_POST_IMM:
1485 case ARM::STR_POST_REG:
1486 case ARM::STRB_POST_IMM:
1487 case ARM::STRB_POST_REG:
1488 case ARM::STRT_POST_REG:
1489 case ARM::STRT_POST_IMM:
1490 case ARM::STRBT_POST_REG:
1491 case ARM::STRBT_POST_IMM:
1492 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1493 return MCDisassembler::Fail;
1494 break;
1495 default:
1496 break;
1497 }
1498
1499 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1500 return MCDisassembler::Fail;
1501
1502 // On loads, the writeback operand comes after Rt.
1503 switch (Inst.getOpcode()) {
1504 case ARM::LDR_POST_IMM:
1505 case ARM::LDR_POST_REG:
1506 case ARM::LDRB_POST_IMM:
1507 case ARM::LDRB_POST_REG:
1508 case ARM::LDRBT_POST_REG:
1509 case ARM::LDRBT_POST_IMM:
1510 case ARM::LDRT_POST_REG:
1511 case ARM::LDRT_POST_IMM:
1512 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1513 return MCDisassembler::Fail;
1514 break;
1515 default:
1516 break;
1517 }
1518
1519 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1520 return MCDisassembler::Fail;
1521
1522 ARM_AM::AddrOpc Op = ARM_AM::add;
1523 if (!fieldFromInstruction(Insn, 23, 1))
1524 Op = ARM_AM::sub;
1525
1526 bool writeback = (P == 0) || (W == 1);
1527 unsigned idx_mode = 0;
1528 if (P && writeback)
1529 idx_mode = ARMII::IndexModePre;
1530 else if (!P && writeback)
1531 idx_mode = ARMII::IndexModePost;
1532
1533 if (writeback && (Rn == 15 || Rn == Rt))
1534 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1535
1536 if (reg) {
1537 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1538 return MCDisassembler::Fail;
1539 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1540 switch( fieldFromInstruction(Insn, 5, 2)) {
1541 case 0:
1542 Opc = ARM_AM::lsl;
1543 break;
1544 case 1:
1545 Opc = ARM_AM::lsr;
1546 break;
1547 case 2:
1548 Opc = ARM_AM::asr;
1549 break;
1550 case 3:
1551 Opc = ARM_AM::ror;
1552 break;
1553 default:
1554 return MCDisassembler::Fail;
1555 }
1556 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1557 if (Opc == ARM_AM::ror && amt == 0)
1558 Opc = ARM_AM::rrx;
1559 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1560
1561 Inst.addOperand(MCOperand::createImm(imm));
1562 } else {
1563 Inst.addOperand(MCOperand::createReg(0));
1564 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1565 Inst.addOperand(MCOperand::createImm(tmp));
1566 }
1567
1568 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1569 return MCDisassembler::Fail;
1570
1571 return S;
1572 }
1573
1574 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1575 uint64_t Address, const void *Decoder) {
1576 DecodeStatus S = MCDisassembler::Success;
1577
1578 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1579 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1580 unsigned type = fieldFromInstruction(Val, 5, 2);
1581 unsigned imm = fieldFromInstruction(Val, 7, 5);
1582 unsigned U = fieldFromInstruction(Val, 12, 1);
1583
1584 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1585 switch (type) {
1586 case 0:
1587 ShOp = ARM_AM::lsl;
1588 break;
1589 case 1:
1590 ShOp = ARM_AM::lsr;
1591 break;
1592 case 2:
1593 ShOp = ARM_AM::asr;
1594 break;
1595 case 3:
1596 ShOp = ARM_AM::ror;
1597 break;
1598 }
1599
1600 if (ShOp == ARM_AM::ror && imm == 0)
1601 ShOp = ARM_AM::rrx;
1602
1603 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1604 return MCDisassembler::Fail;
1605 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1606 return MCDisassembler::Fail;
1607 unsigned shift;
1608 if (U)
1609 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1610 else
1611 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1612 Inst.addOperand(MCOperand::createImm(shift));
1613
1614 return S;
1615 }
1616
1617 static DecodeStatus
1618 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1619 uint64_t Address, const void *Decoder) {
1620 DecodeStatus S = MCDisassembler::Success;
1621
1622 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1623 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1624 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1625 unsigned type = fieldFromInstruction(Insn, 22, 1);
1626 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1627 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1628 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1629 unsigned W = fieldFromInstruction(Insn, 21, 1);
1630 unsigned P = fieldFromInstruction(Insn, 24, 1);
1631 unsigned Rt2 = Rt + 1;
1632
1633 bool writeback = (W == 1) | (P == 0);
1634
1635 // For {LD,ST}RD, Rt must be even, else undefined.
1636 switch (Inst.getOpcode()) {
1637 case ARM::STRD:
1638 case ARM::STRD_PRE:
1639 case ARM::STRD_POST:
1640 case ARM::LDRD:
1641 case ARM::LDRD_PRE:
1642 case ARM::LDRD_POST:
1643 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1644 break;
1645 default:
1646 break;
1647 }
1648 switch (Inst.getOpcode()) {
1649 case ARM::STRD:
1650 case ARM::STRD_PRE:
1651 case ARM::STRD_POST:
1652 if (P == 0 && W == 1)
1653 S = MCDisassembler::SoftFail;
1654
1655 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1656 S = MCDisassembler::SoftFail;
1657 if (type && Rm == 15)
1658 S = MCDisassembler::SoftFail;
1659 if (Rt2 == 15)
1660 S = MCDisassembler::SoftFail;
1661 if (!type && fieldFromInstruction(Insn, 8, 4))
1662 S = MCDisassembler::SoftFail;
1663 break;
1664 case ARM::STRH:
1665 case ARM::STRH_PRE:
1666 case ARM::STRH_POST:
1667 if (Rt == 15)
1668 S = MCDisassembler::SoftFail;
1669 if (writeback && (Rn == 15 || Rn == Rt))
1670 S = MCDisassembler::SoftFail;
1671 if (!type && Rm == 15)
1672 S = MCDisassembler::SoftFail;
1673 break;
1674 case ARM::LDRD:
1675 case ARM::LDRD_PRE:
1676 case ARM::LDRD_POST:
1677 if (type && Rn == 15) {
1678 if (Rt2 == 15)
1679 S = MCDisassembler::SoftFail;
1680 break;
1681 }
1682 if (P == 0 && W == 1)
1683 S = MCDisassembler::SoftFail;
1684 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1685 S = MCDisassembler::SoftFail;
1686 if (!type && writeback && Rn == 15)
1687 S = MCDisassembler::SoftFail;
1688 if (writeback && (Rn == Rt || Rn == Rt2))
1689 S = MCDisassembler::SoftFail;
1690 break;
1691 case ARM::LDRH:
1692 case ARM::LDRH_PRE:
1693 case ARM::LDRH_POST:
1694 if (type && Rn == 15) {
1695 if (Rt == 15)
1696 S = MCDisassembler::SoftFail;
1697 break;
1698 }
1699 if (Rt == 15)
1700 S = MCDisassembler::SoftFail;
1701 if (!type && Rm == 15)
1702 S = MCDisassembler::SoftFail;
1703 if (!type && writeback && (Rn == 15 || Rn == Rt))
1704 S = MCDisassembler::SoftFail;
1705 break;
1706 case ARM::LDRSH:
1707 case ARM::LDRSH_PRE:
1708 case ARM::LDRSH_POST:
1709 case ARM::LDRSB:
1710 case ARM::LDRSB_PRE:
1711 case ARM::LDRSB_POST:
1712 if (type && Rn == 15) {
1713 if (Rt == 15)
1714 S = MCDisassembler::SoftFail;
1715 break;
1716 }
1717 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1718 S = MCDisassembler::SoftFail;
1719 if (!type && (Rt == 15 || Rm == 15))
1720 S = MCDisassembler::SoftFail;
1721 if (!type && writeback && (Rn == 15 || Rn == Rt))
1722 S = MCDisassembler::SoftFail;
1723 break;
1724 default:
1725 break;
1726 }
1727
1728 if (writeback) { // Writeback
1729 if (P)
1730 U |= ARMII::IndexModePre << 9;
1731 else
1732 U |= ARMII::IndexModePost << 9;
1733
1734 // On stores, the writeback operand precedes Rt.
1735 switch (Inst.getOpcode()) {
1736 case ARM::STRD:
1737 case ARM::STRD_PRE:
1738 case ARM::STRD_POST:
1739 case ARM::STRH:
1740 case ARM::STRH_PRE:
1741 case ARM::STRH_POST:
1742 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1743 return MCDisassembler::Fail;
1744 break;
1745 default:
1746 break;
1747 }
1748 }
1749
1750 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1751 return MCDisassembler::Fail;
1752 switch (Inst.getOpcode()) {
1753 case ARM::STRD:
1754 case ARM::STRD_PRE:
1755 case ARM::STRD_POST:
1756 case ARM::LDRD:
1757 case ARM::LDRD_PRE:
1758 case ARM::LDRD_POST:
1759 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1760 return MCDisassembler::Fail;
1761 break;
1762 default:
1763 break;
1764 }
1765
1766 if (writeback) {
1767 // On loads, the writeback operand comes after Rt.
1768 switch (Inst.getOpcode()) {
1769 case ARM::LDRD:
1770 case ARM::LDRD_PRE:
1771 case ARM::LDRD_POST:
1772 case ARM::LDRH:
1773 case ARM::LDRH_PRE:
1774 case ARM::LDRH_POST:
1775 case ARM::LDRSH:
1776 case ARM::LDRSH_PRE:
1777 case ARM::LDRSH_POST:
1778 case ARM::LDRSB:
1779 case ARM::LDRSB_PRE:
1780 case ARM::LDRSB_POST:
1781 case ARM::LDRHTr:
1782 case ARM::LDRSBTr:
1783 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1784 return MCDisassembler::Fail;
1785 break;
1786 default:
1787 break;
1788 }
1789 }
1790
1791 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1792 return MCDisassembler::Fail;
1793
1794 if (type) {
1795 Inst.addOperand(MCOperand::createReg(0));
1796 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
1797 } else {
1798 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1799 return MCDisassembler::Fail;
1800 Inst.addOperand(MCOperand::createImm(U));
1801 }
1802
1803 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1804 return MCDisassembler::Fail;
1805
1806 return S;
1807 }
1808
1809 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1810 uint64_t Address, const void *Decoder) {
1811 DecodeStatus S = MCDisassembler::Success;
1812
1813 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1814 unsigned mode = fieldFromInstruction(Insn, 23, 2);
1815
1816 switch (mode) {
1817 case 0:
1818 mode = ARM_AM::da;
1819 break;
1820 case 1:
1821 mode = ARM_AM::ia;
1822 break;
1823 case 2:
1824 mode = ARM_AM::db;
1825 break;
1826 case 3:
1827 mode = ARM_AM::ib;
1828 break;
1829 }
1830
1831 Inst.addOperand(MCOperand::createImm(mode));
1832 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1833 return MCDisassembler::Fail;
1834
1835 return S;
1836 }
1837
1838 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1839 uint64_t Address, const void *Decoder) {
1840 DecodeStatus S = MCDisassembler::Success;
1841
1842 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1843 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1844 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1845 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1846
1847 if (pred == 0xF)
1848 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1849
1850 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1851 return MCDisassembler::Fail;
1852 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1853 return MCDisassembler::Fail;
1854 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1855 return MCDisassembler::Fail;
1856 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1857 return MCDisassembler::Fail;
1858 return S;
1859 }
1860
1861 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
1862 unsigned Insn,
1863 uint64_t Address, const void *Decoder) {
1864 DecodeStatus S = MCDisassembler::Success;
1865
1866 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1867 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1868 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1869
1870 if (pred == 0xF) {
1871 // Ambiguous with RFE and SRS
1872 switch (Inst.getOpcode()) {
1873 case ARM::LDMDA:
1874 Inst.setOpcode(ARM::RFEDA);
1875 break;
1876 case ARM::LDMDA_UPD:
1877 Inst.setOpcode(ARM::RFEDA_UPD);
1878 break;
1879 case ARM::LDMDB:
1880 Inst.setOpcode(ARM::RFEDB);
1881 break;
1882 case ARM::LDMDB_UPD:
1883 Inst.setOpcode(ARM::RFEDB_UPD);
1884 break;
1885 case ARM::LDMIA:
1886 Inst.setOpcode(ARM::RFEIA);
1887 break;
1888 case ARM::LDMIA_UPD:
1889 Inst.setOpcode(ARM::RFEIA_UPD);
1890 break;
1891 case ARM::LDMIB:
1892 Inst.setOpcode(ARM::RFEIB);
1893 break;
1894 case ARM::LDMIB_UPD:
1895 Inst.setOpcode(ARM::RFEIB_UPD);
1896 break;
1897 case ARM::STMDA:
1898 Inst.setOpcode(ARM::SRSDA);
1899 break;
1900 case ARM::STMDA_UPD:
1901 Inst.setOpcode(ARM::SRSDA_UPD);
1902 break;
1903 case ARM::STMDB:
1904 Inst.setOpcode(ARM::SRSDB);
1905 break;
1906 case ARM::STMDB_UPD:
1907 Inst.setOpcode(ARM::SRSDB_UPD);
1908 break;
1909 case ARM::STMIA:
1910 Inst.setOpcode(ARM::SRSIA);
1911 break;
1912 case ARM::STMIA_UPD:
1913 Inst.setOpcode(ARM::SRSIA_UPD);
1914 break;
1915 case ARM::STMIB:
1916 Inst.setOpcode(ARM::SRSIB);
1917 break;
1918 case ARM::STMIB_UPD:
1919 Inst.setOpcode(ARM::SRSIB_UPD);
1920 break;
1921 default:
1922 return MCDisassembler::Fail;
1923 }
1924
1925 // For stores (which become SRS's, the only operand is the mode.
1926 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1927 // Check SRS encoding constraints
1928 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1929 fieldFromInstruction(Insn, 20, 1) == 0))
1930 return MCDisassembler::Fail;
1931
1932 Inst.addOperand(
1933 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
1934 return S;
1935 }
1936
1937 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1938 }
1939
1940 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1941 return MCDisassembler::Fail;
1942 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1943 return MCDisassembler::Fail; // Tied
1944 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1945 return MCDisassembler::Fail;
1946 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1947 return MCDisassembler::Fail;
1948
1949 return S;
1950 }
1951
1952 // Check for UNPREDICTABLE predicated ESB instruction
1953 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
1954 uint64_t Address, const void *Decoder) {
1955 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1956 unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
1957 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
1958 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
1959
1960 DecodeStatus S = MCDisassembler::Success;
1961
1962 Inst.addOperand(MCOperand::createImm(imm8));
1963
1964 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1965 return MCDisassembler::Fail;
1966
1967 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
1968 // so all predicates should be allowed.
1969 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
1970 S = MCDisassembler::SoftFail;
1971
1972 return S;
1973 }
1974
1975 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1976 uint64_t Address, const void *Decoder) {
1977 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1978 unsigned M = fieldFromInstruction(Insn, 17, 1);
1979 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1980 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1981
1982 DecodeStatus S = MCDisassembler::Success;
1983
1984 // This decoder is called from multiple location that do not check
1985 // the full encoding is valid before they do.
1986 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1987 fieldFromInstruction(Insn, 16, 1) != 0 ||
1988 fieldFromInstruction(Insn, 20, 8) != 0x10)
1989 return MCDisassembler::Fail;
1990
1991 // imod == '01' --> UNPREDICTABLE
1992 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1993 // return failure here. The '01' imod value is unprintable, so there's
1994 // nothing useful we could do even if we returned UNPREDICTABLE.
1995
1996 if (imod == 1) return MCDisassembler::Fail;
1997
1998 if (imod && M) {
1999 Inst.setOpcode(ARM::CPS3p);
2000 Inst.addOperand(MCOperand::createImm(imod));
2001 Inst.addOperand(MCOperand::createImm(iflags));
2002 Inst.addOperand(MCOperand::createImm(mode));
2003 } else if (imod && !M) {
2004 Inst.setOpcode(ARM::CPS2p);
2005 Inst.addOperand(MCOperand::createImm(imod));
2006 Inst.addOperand(MCOperand::createImm(iflags));
2007 if (mode) S = MCDisassembler::SoftFail;
2008 } else if (!imod && M) {
2009 Inst.setOpcode(ARM::CPS1p);
2010 Inst.addOperand(MCOperand::createImm(mode));
2011 if (iflags) S = MCDisassembler::SoftFail;
2012 } else {
2013 // imod == '00' && M == '0' --> UNPREDICTABLE
2014 Inst.setOpcode(ARM::CPS1p);
2015 Inst.addOperand(MCOperand::createImm(mode));
2016 S = MCDisassembler::SoftFail;
2017 }
2018
2019 return S;
2020 }
2021
2022 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
2023 uint64_t Address, const void *Decoder) {
2024 unsigned imod = fieldFromInstruction(Insn, 9, 2);
2025 unsigned M = fieldFromInstruction(Insn, 8, 1);
2026 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2027 unsigned mode = fieldFromInstruction(Insn, 0, 5);
2028
2029 DecodeStatus S = MCDisassembler::Success;
2030
2031 // imod == '01' --> UNPREDICTABLE
2032 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2033 // return failure here. The '01' imod value is unprintable, so there's
2034 // nothing useful we could do even if we returned UNPREDICTABLE.
2035
2036 if (imod == 1) return MCDisassembler::Fail;
2037
2038 if (imod && M) {
2039 Inst.setOpcode(ARM::t2CPS3p);
2040 Inst.addOperand(MCOperand::createImm(imod));
2041 Inst.addOperand(MCOperand::createImm(iflags));
2042 Inst.addOperand(MCOperand::createImm(mode));
2043 } else if (imod && !M) {
2044 Inst.setOpcode(ARM::t2CPS2p);
2045 Inst.addOperand(MCOperand::createImm(imod));
2046 Inst.addOperand(MCOperand::createImm(iflags));
2047 if (mode) S = MCDisassembler::SoftFail;
2048 } else if (!imod && M) {
2049 Inst.setOpcode(ARM::t2CPS1p);
2050 Inst.addOperand(MCOperand::createImm(mode));
2051 if (iflags) S = MCDisassembler::SoftFail;
2052 } else {
2053 // imod == '00' && M == '0' --> this is a HINT instruction
2054 int imm = fieldFromInstruction(Insn, 0, 8);
2055 // HINT are defined only for immediate in [0..4]
2056 if(imm > 4) return MCDisassembler::Fail;
2057 Inst.setOpcode(ARM::t2HINT);
2058 Inst.addOperand(MCOperand::createImm(imm));
2059 }
2060
2061 return S;
2062 }
2063
2064 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2065 uint64_t Address, const void *Decoder) {
2066 DecodeStatus S = MCDisassembler::Success;
2067
2068 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2069 unsigned imm = 0;
2070
2071 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2072 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2073 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2074 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2075
2076 if (Inst.getOpcode() == ARM::t2MOVTi16)
2077 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2078 return MCDisassembler::Fail;
2079 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2080 return MCDisassembler::Fail;
2081
2082 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2083 Inst.addOperand(MCOperand::createImm(imm));
2084
2085 return S;
2086 }
2087
2088 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2089 uint64_t Address, const void *Decoder) {
2090 DecodeStatus S = MCDisassembler::Success;
2091
2092 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2093 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2094 unsigned imm = 0;
2095
2096 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2097 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2098
2099 if (Inst.getOpcode() == ARM::MOVTi16)
2100 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2101 return MCDisassembler::Fail;
2102
2103 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2104 return MCDisassembler::Fail;
2105
2106 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2107 Inst.addOperand(MCOperand::createImm(imm));
2108
2109 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2110 return MCDisassembler::Fail;
2111
2112 return S;
2113 }
2114
2115 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2116 uint64_t Address, const void *Decoder) {
2117 DecodeStatus S = MCDisassembler::Success;
2118
2119 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2120 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2121 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2122 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2123 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2124
2125 if (pred == 0xF)
2126 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2127
2128 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2129 return MCDisassembler::Fail;
2130 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2131 return MCDisassembler::Fail;
2132 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2133 return MCDisassembler::Fail;
2134 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2135 return MCDisassembler::Fail;
2136
2137 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2138 return MCDisassembler::Fail;
2139
2140 return S;
2141 }
2142
2143 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
2144 uint64_t Address, const void *Decoder) {
2145 DecodeStatus S = MCDisassembler::Success;
2146
2147 unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2148 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2149 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2150
2151 if (Pred == 0xF)
2152 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
2153
2154 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2155 return MCDisassembler::Fail;
2156 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2157 return MCDisassembler::Fail;
2158 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
2159 return MCDisassembler::Fail;
2160
2161 return S;
2162 }
2163
2164 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
2165 uint64_t Address, const void *Decoder) {
2166 DecodeStatus S = MCDisassembler::Success;
2167
2168 unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2169
2170 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2171 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2172
2173 if (!FeatureBits[ARM::HasV8_1aOps] ||
2174 !FeatureBits[ARM::HasV8Ops])
2175 return MCDisassembler::Fail;
2176
2177 // Decoder can be called from DecodeTST, which does not check the full
2178 // encoding is valid.
2179 if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2180 fieldFromInstruction(Insn, 4,4) != 0)
2181 return MCDisassembler::Fail;
2182 if (fieldFromInstruction(Insn, 10,10) != 0 ||
2183 fieldFromInstruction(Insn, 0,4) != 0)
2184 S = MCDisassembler::SoftFail;
2185
2186 Inst.setOpcode(ARM::SETPAN);
2187 Inst.addOperand(MCOperand::createImm(Imm));
2188
2189 return S;
2190 }
2191
2192 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2193 uint64_t Address, const void *Decoder) {
2194 DecodeStatus S = MCDisassembler::Success;
2195
2196 unsigned add = fieldFromInstruction(Val, 12, 1);
2197 unsigned imm = fieldFromInstruction(Val, 0, 12);
2198 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2199
2200 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2201 return MCDisassembler::Fail;
2202
2203 if (!add) imm *= -1;
2204 if (imm == 0 && !add) imm = INT32_MIN;
2205 Inst.addOperand(MCOperand::createImm(imm));
2206 if (Rn == 15)
2207 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2208
2209 return S;
2210 }
2211
2212 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2213 uint64_t Address, const void *Decoder) {
2214 DecodeStatus S = MCDisassembler::Success;
2215
2216 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2217 // U == 1 to add imm, 0 to subtract it.
2218 unsigned U = fieldFromInstruction(Val, 8, 1);
2219 unsigned imm = fieldFromInstruction(Val, 0, 8);
2220
2221 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2222 return MCDisassembler::Fail;
2223
2224 if (U)
2225 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2226 else
2227 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2228
2229 return S;
2230 }
2231
2232 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
2233 uint64_t Address, const void *Decoder) {
2234 DecodeStatus S = MCDisassembler::Success;
2235
2236 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2237 // U == 1 to add imm, 0 to subtract it.
2238 unsigned U = fieldFromInstruction(Val, 8, 1);
2239 unsigned imm = fieldFromInstruction(Val, 0, 8);
2240
2241 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2242 return MCDisassembler::Fail;
2243
2244 if (U)
2245 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));
2246 else
2247 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm)));
2248
2249 return S;
2250 }
2251
2252 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2253 uint64_t Address, const void *Decoder) {
2254 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2255 }
2256
2257 static DecodeStatus
2258 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2259 uint64_t Address, const void *Decoder) {
2260 DecodeStatus Status = MCDisassembler::Success;
2261
2262 // Note the J1 and J2 values are from the encoded instruction. So here
2263 // change them to I1 and I2 values via as documented:
2264 // I1 = NOT(J1 EOR S);
2265 // I2 = NOT(J2 EOR S);
2266 // and build the imm32 with one trailing zero as documented:
2267 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2268 unsigned S = fieldFromInstruction(Insn, 26, 1);
2269 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2270 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2271 unsigned I1 = !(J1 ^ S);
2272 unsigned I2 = !(J2 ^ S);
2273 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2274 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2275 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2276 int imm32 = SignExtend32<25>(tmp << 1);
2277 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2278 true, 4, Inst, Decoder))
2279 Inst.addOperand(MCOperand::createImm(imm32));
2280
2281 return Status;
2282 }
2283
2284 static DecodeStatus
2285 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2286 uint64_t Address, const void *Decoder) {
2287 DecodeStatus S = MCDisassembler::Success;
2288
2289 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2290 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2291
2292 if (pred == 0xF) {
2293 Inst.setOpcode(ARM::BLXi);
2294 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2295 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2296 true, 4, Inst, Decoder))
2297 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2298 return S;
2299 }
2300
2301 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2302 true, 4, Inst, Decoder))
2303 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2304 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2305 return MCDisassembler::Fail;
2306
2307 return S;
2308 }
2309
2310 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2311 uint64_t Address, const void *Decoder) {
2312 DecodeStatus S = MCDisassembler::Success;
2313
2314 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2315 unsigned align = fieldFromInstruction(Val, 4, 2);
2316
2317 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2318 return MCDisassembler::Fail;
2319 if (!align)
2320 Inst.addOperand(MCOperand::createImm(0));
2321 else
2322 Inst.addOperand(MCOperand::createImm(4 << align));
2323
2324 return S;
2325 }
2326
2327 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2328 uint64_t Address, const void *Decoder) {
2329 DecodeStatus S = MCDisassembler::Success;
2330
2331 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2332 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2333 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2334 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2335 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2336 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2337
2338 // First output register
2339 switch (Inst.getOpcode()) {
2340 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2341 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2342 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2343 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2344 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2345 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2346 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2347 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2348 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2349 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2350 return MCDisassembler::Fail;
2351 break;
2352 case ARM::VLD2b16:
2353 case ARM::VLD2b32:
2354 case ARM::VLD2b8:
2355 case ARM::VLD2b16wb_fixed:
2356 case ARM::VLD2b16wb_register:
2357 case ARM::VLD2b32wb_fixed:
2358 case ARM::VLD2b32wb_register:
2359 case ARM::VLD2b8wb_fixed:
2360 case ARM::VLD2b8wb_register:
2361 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2362 return MCDisassembler::Fail;
2363 break;
2364 default:
2365 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2366 return MCDisassembler::Fail;
2367 }
2368
2369 // Second output register
2370 switch (Inst.getOpcode()) {
2371 case ARM::VLD3d8:
2372 case ARM::VLD3d16:
2373 case ARM::VLD3d32:
2374 case ARM::VLD3d8_UPD:
2375 case ARM::VLD3d16_UPD:
2376 case ARM::VLD3d32_UPD:
2377 case ARM::VLD4d8:
2378 case ARM::VLD4d16:
2379 case ARM::VLD4d32:
2380 case ARM::VLD4d8_UPD:
2381 case ARM::VLD4d16_UPD:
2382 case ARM::VLD4d32_UPD:
2383 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2384 return MCDisassembler::Fail;
2385 break;
2386 case ARM::VLD3q8:
2387 case ARM::VLD3q16:
2388 case ARM::VLD3q32:
2389 case ARM::VLD3q8_UPD:
2390 case ARM::VLD3q16_UPD:
2391 case ARM::VLD3q32_UPD:
2392 case ARM::VLD4q8:
2393 case ARM::VLD4q16:
2394 case ARM::VLD4q32:
2395 case ARM::VLD4q8_UPD:
2396 case ARM::VLD4q16_UPD:
2397 case ARM::VLD4q32_UPD:
2398 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2399 return MCDisassembler::Fail;
2400 break;
2401 default:
2402 break;
2403 }
2404
2405 // Third output register
2406 switch(Inst.getOpcode()) {
2407 case ARM::VLD3d8:
2408 case ARM::VLD3d16:
2409 case ARM::VLD3d32:
2410 case ARM::VLD3d8_UPD:
2411 case ARM::VLD3d16_UPD:
2412 case ARM::VLD3d32_UPD:
2413 case ARM::VLD4d8:
2414 case ARM::VLD4d16:
2415 case ARM::VLD4d32:
2416 case ARM::VLD4d8_UPD:
2417 case ARM::VLD4d16_UPD:
2418 case ARM::VLD4d32_UPD:
2419 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2420 return MCDisassembler::Fail;
2421 break;
2422 case ARM::VLD3q8:
2423 case ARM::VLD3q16:
2424 case ARM::VLD3q32:
2425 case ARM::VLD3q8_UPD:
2426 case ARM::VLD3q16_UPD:
2427 case ARM::VLD3q32_UPD:
2428 case ARM::VLD4q8:
2429 case ARM::VLD4q16:
2430 case ARM::VLD4q32:
2431 case ARM::VLD4q8_UPD:
2432 case ARM::VLD4q16_UPD:
2433 case ARM::VLD4q32_UPD:
2434 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2435 return MCDisassembler::Fail;
2436 break;
2437 default:
2438 break;
2439 }
2440
2441 // Fourth output register
2442 switch (Inst.getOpcode()) {
2443 case ARM::VLD4d8:
2444 case ARM::VLD4d16:
2445 case ARM::VLD4d32:
2446 case ARM::VLD4d8_UPD:
2447 case ARM::VLD4d16_UPD:
2448 case ARM::VLD4d32_UPD:
2449 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2450 return MCDisassembler::Fail;
2451 break;
2452 case ARM::VLD4q8:
2453 case ARM::VLD4q16:
2454 case ARM::VLD4q32:
2455 case ARM::VLD4q8_UPD:
2456 case ARM::VLD4q16_UPD:
2457 case ARM::VLD4q32_UPD:
2458 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2459 return MCDisassembler::Fail;
2460 break;
2461 default:
2462 break;
2463 }
2464
2465 // Writeback operand
2466 switch (Inst.getOpcode()) {
2467 case ARM::VLD1d8wb_fixed:
2468 case ARM::VLD1d16wb_fixed:
2469 case ARM::VLD1d32wb_fixed:
2470 case ARM::VLD1d64wb_fixed:
2471 case ARM::VLD1d8wb_register:
2472 case ARM::VLD1d16wb_register:
2473 case ARM::VLD1d32wb_register:
2474 case ARM::VLD1d64wb_register:
2475 case ARM::VLD1q8wb_fixed:
2476 case ARM::VLD1q16wb_fixed:
2477 case ARM::VLD1q32wb_fixed:
2478 case ARM::VLD1q64wb_fixed:
2479 case ARM::VLD1q8wb_register:
2480 case ARM::VLD1q16wb_register:
2481 case ARM::VLD1q32wb_register:
2482 case ARM::VLD1q64wb_register:
2483 case ARM::VLD1d8Twb_fixed:
2484 case ARM::VLD1d8Twb_register:
2485 case ARM::VLD1d16Twb_fixed:
2486 case ARM::VLD1d16Twb_register:
2487 case ARM::VLD1d32Twb_fixed:
2488 case ARM::VLD1d32Twb_register:
2489 case ARM::VLD1d64Twb_fixed:
2490 case ARM::VLD1d64Twb_register:
2491 case ARM::VLD1d8Qwb_fixed:
2492 case ARM::VLD1d8Qwb_register:
2493 case ARM::VLD1d16Qwb_fixed:
2494 case ARM::VLD1d16Qwb_register:
2495 case ARM::VLD1d32Qwb_fixed:
2496 case ARM::VLD1d32Qwb_register:
2497 case ARM::VLD1d64Qwb_fixed:
2498 case ARM::VLD1d64Qwb_register:
2499 case ARM::VLD2d8wb_fixed:
2500 case ARM::VLD2d16wb_fixed:
2501 case ARM::VLD2d32wb_fixed:
2502 case ARM::VLD2q8wb_fixed:
2503 case ARM::VLD2q16wb_fixed:
2504 case ARM::VLD2q32wb_fixed:
2505 case ARM::VLD2d8wb_register:
2506 case ARM::VLD2d16wb_register:
2507 case ARM::VLD2d32wb_register:
2508 case ARM::VLD2q8wb_register:
2509 case ARM::VLD2q16wb_register:
2510 case ARM::VLD2q32wb_register:
2511 case ARM::VLD2b8wb_fixed:
2512 case ARM::VLD2b16wb_fixed:
2513 case ARM::VLD2b32wb_fixed:
2514 case ARM::VLD2b8wb_register:
2515 case ARM::VLD2b16wb_register:
2516 case ARM::VLD2b32wb_register:
2517 Inst.addOperand(MCOperand::createImm(0));
2518 break;
2519 case ARM::VLD3d8_UPD:
2520 case ARM::VLD3d16_UPD:
2521 case ARM::VLD3d32_UPD:
2522 case ARM::VLD3q8_UPD:
2523 case ARM::VLD3q16_UPD:
2524 case ARM::VLD3q32_UPD:
2525 case ARM::VLD4d8_UPD:
2526 case ARM::VLD4d16_UPD:
2527 case ARM::VLD4d32_UPD:
2528 case ARM::VLD4q8_UPD:
2529 case ARM::VLD4q16_UPD:
2530 case ARM::VLD4q32_UPD:
2531 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2532 return MCDisassembler::Fail;
2533 break;
2534 default:
2535 break;
2536 }
2537
2538 // AddrMode6 Base (register+alignment)
2539 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2540 return MCDisassembler::Fail;
2541
2542 // AddrMode6 Offset (register)
2543 switch (Inst.getOpcode()) {
2544 default:
2545 // The below have been updated to have explicit am6offset split
2546 // between fixed and register offset. For those instructions not
2547 // yet updated, we need to add an additional reg0 operand for the
2548 // fixed variant.
2549 //
2550 // The fixed offset encodes as Rm == 0xd, so we check for that.
2551 if (Rm == 0xd) {
2552 Inst.addOperand(MCOperand::createReg(0));
2553 break;
2554 }
2555 // Fall through to handle the register offset variant.
2556 LLVM_FALLTHROUGH;
2557 case ARM::VLD1d8wb_fixed:
2558 case ARM::VLD1d16wb_fixed:
2559 case ARM::VLD1d32wb_fixed:
2560 case ARM::VLD1d64wb_fixed:
2561 case ARM::VLD1d8Twb_fixed:
2562 case ARM::VLD1d16Twb_fixed:
2563 case ARM::VLD1d32Twb_fixed:
2564 case ARM::VLD1d64Twb_fixed:
2565 case ARM::VLD1d8Qwb_fixed:
2566 case ARM::VLD1d16Qwb_fixed:
2567 case ARM::VLD1d32Qwb_fixed:
2568 case ARM::VLD1d64Qwb_fixed:
2569 case ARM::VLD1d8wb_register:
2570 case ARM::VLD1d16wb_register:
2571 case ARM::VLD1d32wb_register:
2572 case ARM::VLD1d64wb_register:
2573 case ARM::VLD1q8wb_fixed:
2574 case ARM::VLD1q16wb_fixed:
2575 case ARM::VLD1q32wb_fixed:
2576 case ARM::VLD1q64wb_fixed:
2577 case ARM::VLD1q8wb_register:
2578 case ARM::VLD1q16wb_register:
2579 case ARM::VLD1q32wb_register:
2580 case ARM::VLD1q64wb_register:
2581 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2582 // variant encodes Rm == 0xf. Anything else is a register offset post-
2583 // increment and we need to add the register operand to the instruction.
2584 if (Rm != 0xD && Rm != 0xF &&
2585 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2586 return MCDisassembler::Fail;
2587 break;
2588 case ARM::VLD2d8wb_fixed:
2589 case ARM::VLD2d16wb_fixed:
2590 case ARM::VLD2d32wb_fixed:
2591 case ARM::VLD2b8wb_fixed:
2592 case ARM::VLD2b16wb_fixed:
2593 case ARM::VLD2b32wb_fixed:
2594 case ARM::VLD2q8wb_fixed:
2595 case ARM::VLD2q16wb_fixed:
2596 case ARM::VLD2q32wb_fixed:
2597 break;
2598 }
2599
2600 return S;
2601 }
2602
2603 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2604 uint64_t Address, const void *Decoder) {
2605 unsigned type = fieldFromInstruction(Insn, 8, 4);
2606 unsigned align = fieldFromInstruction(Insn, 4, 2);
2607 if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2608 if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2609 if (type == 10 && align == 3) return MCDisassembler::Fail;
2610
2611 unsigned load = fieldFromInstruction(Insn, 21, 1);
2612 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2613 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2614 }
2615
2616 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2617 uint64_t Address, const void *Decoder) {
2618 unsigned size = fieldFromInstruction(Insn, 6, 2);
2619 if (size == 3) return MCDisassembler::Fail;
2620
2621 unsigned type = fieldFromInstruction(Insn, 8, 4);
2622 unsigned align = fieldFromInstruction(Insn, 4, 2);
2623 if (type == 8 && align == 3) return MCDisassembler::Fail;
2624 if (type == 9 && align == 3) return MCDisassembler::Fail;
2625
2626 unsigned load = fieldFromInstruction(Insn, 21, 1);
2627 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2628 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2629 }
2630
2631 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2632 uint64_t Address, const void *Decoder) {
2633 unsigned size = fieldFromInstruction(Insn, 6, 2);
2634 if (size == 3) return MCDisassembler::Fail;
2635
2636 unsigned align = fieldFromInstruction(Insn, 4, 2);
2637 if (align & 2) return MCDisassembler::Fail;
2638
2639 unsigned load = fieldFromInstruction(Insn, 21, 1);
2640 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2641 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2642 }
2643
2644 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2645 uint64_t Address, const void *Decoder) {
2646 unsigned size = fieldFromInstruction(Insn, 6, 2);
2647 if (size == 3) return MCDisassembler::Fail;
2648
2649 unsigned load = fieldFromInstruction(Insn, 21, 1);
2650 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2651 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2652 }
2653
2654 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2655 uint64_t Address, const void *Decoder) {
2656 DecodeStatus S = MCDisassembler::Success;
2657
2658 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2659 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2660 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2661 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2662 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2663 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2664
2665 // Writeback Operand
2666 switch (Inst.getOpcode()) {
2667 case ARM::VST1d8wb_fixed:
2668 case ARM::VST1d16wb_fixed:
2669 case ARM::VST1d32wb_fixed:
2670 case ARM::VST1d64wb_fixed:
2671 case ARM::VST1d8wb_register:
2672 case ARM::VST1d16wb_register:
2673 case ARM::VST1d32wb_register:
2674 case ARM::VST1d64wb_register:
2675 case ARM::VST1q8wb_fixed:
2676 case ARM::VST1q16wb_fixed:
2677 case ARM::VST1q32wb_fixed:
2678 case ARM::VST1q64wb_fixed:
2679 case ARM::VST1q8wb_register:
2680 case ARM::VST1q16wb_register:
2681 case ARM::VST1q32wb_register:
2682 case ARM::VST1q64wb_register:
2683 case ARM::VST1d8Twb_fixed:
2684 case ARM::VST1d16Twb_fixed:
2685 case ARM::VST1d32Twb_fixed:
2686 case ARM::VST1d64Twb_fixed:
2687 case ARM::VST1d8Twb_register:
2688 case ARM::VST1d16Twb_register:
2689 case ARM::VST1d32Twb_register:
2690 case ARM::VST1d64Twb_register:
2691 case ARM::VST1d8Qwb_fixed:
2692 case ARM::VST1d16Qwb_fixed:
2693 case ARM::VST1d32Qwb_fixed:
2694 case ARM::VST1d64Qwb_fixed:
2695 case ARM::VST1d8Qwb_register:
2696 case ARM::VST1d16Qwb_register:
2697 case ARM::VST1d32Qwb_register:
2698 case ARM::VST1d64Qwb_register:
2699 case ARM::VST2d8wb_fixed:
2700 case ARM::VST2d16wb_fixed:
2701 case ARM::VST2d32wb_fixed:
2702 case ARM::VST2d8wb_register:
2703 case ARM::VST2d16wb_register:
2704 case ARM::VST2d32wb_register:
2705 case ARM::VST2q8wb_fixed:
2706 case ARM::VST2q16wb_fixed:
2707 case ARM::VST2q32wb_fixed:
2708 case ARM::VST2q8wb_register:
2709 case ARM::VST2q16wb_register:
2710 case ARM::VST2q32wb_register:
2711 case ARM::VST2b8wb_fixed:
2712 case ARM::VST2b16wb_fixed:
2713 case ARM::VST2b32wb_fixed:
2714 case ARM::VST2b8wb_register:
2715 case ARM::VST2b16wb_register:
2716 case ARM::VST2b32wb_register:
2717 if (Rm == 0xF)
2718 return MCDisassembler::Fail;
2719 Inst.addOperand(MCOperand::createImm(0));
2720 break;
2721 case ARM::VST3d8_UPD:
2722 case ARM::VST3d16_UPD:
2723 case ARM::VST3d32_UPD:
2724 case ARM::VST3q8_UPD:
2725 case ARM::VST3q16_UPD:
2726 case ARM::VST3q32_UPD:
2727 case ARM::VST4d8_UPD:
2728 case ARM::VST4d16_UPD:
2729 case ARM::VST4d32_UPD:
2730 case ARM::VST4q8_UPD:
2731 case ARM::VST4q16_UPD:
2732 case ARM::VST4q32_UPD:
2733 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2734 return MCDisassembler::Fail;
2735 break;
2736 default:
2737 break;
2738 }
2739
2740 // AddrMode6 Base (register+alignment)
2741 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2742 return MCDisassembler::Fail;
2743
2744 // AddrMode6 Offset (register)
2745 switch (Inst.getOpcode()) {
2746 default:
2747 if (Rm == 0xD)
2748 Inst.addOperand(MCOperand::createReg(0));
2749 else if (Rm != 0xF) {
2750 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2751 return MCDisassembler::Fail;
2752 }
2753 break;
2754 case ARM::VST1d8wb_fixed:
2755 case ARM::VST1d16wb_fixed:
2756 case ARM::VST1d32wb_fixed:
2757 case ARM::VST1d64wb_fixed:
2758 case ARM::VST1q8wb_fixed:
2759 case ARM::VST1q16wb_fixed:
2760 case ARM::VST1q32wb_fixed:
2761 case ARM::VST1q64wb_fixed:
2762 case ARM::VST1d8Twb_fixed:
2763 case ARM::VST1d16Twb_fixed:
2764 case ARM::VST1d32Twb_fixed:
2765 case ARM::VST1d64Twb_fixed:
2766 case ARM::VST1d8Qwb_fixed:
2767 case ARM::VST1d16Qwb_fixed:
2768 case ARM::VST1d32Qwb_fixed:
2769 case ARM::VST1d64Qwb_fixed:
2770 case ARM::VST2d8wb_fixed:
2771 case ARM::VST2d16wb_fixed:
2772 case ARM::VST2d32wb_fixed:
2773 case ARM::VST2q8wb_fixed:
2774 case ARM::VST2q16wb_fixed:
2775 case ARM::VST2q32wb_fixed:
2776 case ARM::VST2b8wb_fixed:
2777 case ARM::VST2b16wb_fixed:
2778 case ARM::VST2b32wb_fixed:
2779 break;
2780 }
2781
2782 // First input register
2783 switch (Inst.getOpcode()) {
2784 case ARM::VST1q16:
2785 case ARM::VST1q32:
2786 case ARM::VST1q64:
2787 case ARM::VST1q8:
2788 case ARM::VST1q16wb_fixed:
2789 case ARM::VST1q16wb_register:
2790 case ARM::VST1q32wb_fixed:
2791 case ARM::VST1q32wb_register:
2792 case ARM::VST1q64wb_fixed:
2793 case ARM::VST1q64wb_register:
2794 case ARM::VST1q8wb_fixed:
2795 case ARM::VST1q8wb_register:
2796 case ARM::VST2d16:
2797 case ARM::VST2d32:
2798 case ARM::VST2d8:
2799 case ARM::VST2d16wb_fixed:
2800 case ARM::VST2d16wb_register:
2801 case ARM::VST2d32wb_fixed:
2802 case ARM::VST2d32wb_register:
2803 case ARM::VST2d8wb_fixed:
2804 case ARM::VST2d8wb_register:
2805 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2806 return MCDisassembler::Fail;
2807 break;
2808 case ARM::VST2b16:
2809 case ARM::VST2b32:
2810 case ARM::VST2b8:
2811 case ARM::VST2b16wb_fixed:
2812 case ARM::VST2b16wb_register:
2813 case ARM::VST2b32wb_fixed:
2814 case ARM::VST2b32wb_register:
2815 case ARM::VST2b8wb_fixed:
2816 case ARM::VST2b8wb_register:
2817 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2818 return MCDisassembler::Fail;
2819 break;
2820 default:
2821 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2822 return MCDisassembler::Fail;
2823 }
2824
2825 // Second input register
2826 switch (Inst.getOpcode()) {
2827 case ARM::VST3d8:
2828 case ARM::VST3d16:
2829 case ARM::VST3d32:
2830 case ARM::VST3d8_UPD:
2831 case ARM::VST3d16_UPD:
2832 case ARM::VST3d32_UPD:
2833 case ARM::VST4d8:
2834 case ARM::VST4d16:
2835 case ARM::VST4d32:
2836 case ARM::VST4d8_UPD:
2837 case ARM::VST4d16_UPD:
2838 case ARM::VST4d32_UPD:
2839 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2840 return MCDisassembler::Fail;
2841 break;
2842 case ARM::VST3q8:
2843 case ARM::VST3q16:
2844 case ARM::VST3q32:
2845 case ARM::VST3q8_UPD:
2846 case ARM::VST3q16_UPD:
2847 case ARM::VST3q32_UPD:
2848 case ARM::VST4q8:
2849 case ARM::VST4q16:
2850 case ARM::VST4q32:
2851 case ARM::VST4q8_UPD:
2852 case ARM::VST4q16_UPD:
2853 case ARM::VST4q32_UPD:
2854 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2855 return MCDisassembler::Fail;
2856 break;
2857 default:
2858 break;
2859 }
2860
2861 // Third input register
2862 switch (Inst.getOpcode()) {
2863 case ARM::VST3d8:
2864 case ARM::VST3d16:
2865 case ARM::VST3d32:
2866 case ARM::VST3d8_UPD:
2867 case ARM::VST3d16_UPD:
2868 case ARM::VST3d32_UPD:
2869 case ARM::VST4d8:
2870 case ARM::VST4d16:
2871 case ARM::VST4d32:
2872 case ARM::VST4d8_UPD:
2873 case ARM::VST4d16_UPD:
2874 case ARM::VST4d32_UPD:
2875 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2876 return MCDisassembler::Fail;
2877 break;
2878 case ARM::VST3q8:
2879 case ARM::VST3q16:
2880 case ARM::VST3q32:
2881 case ARM::VST3q8_UPD:
2882 case ARM::VST3q16_UPD:
2883 case ARM::VST3q32_UPD:
2884 case ARM::VST4q8:
2885 case ARM::VST4q16:
2886 case ARM::VST4q32:
2887 case ARM::VST4q8_UPD:
2888 case ARM::VST4q16_UPD:
2889 case ARM::VST4q32_UPD:
2890 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2891 return MCDisassembler::Fail;
2892 break;
2893 default:
2894 break;
2895 }
2896
2897 // Fourth input register
2898 switch (Inst.getOpcode()) {
2899 case ARM::VST4d8:
2900 case ARM::VST4d16:
2901 case ARM::VST4d32:
2902 case ARM::VST4d8_UPD:
2903 case ARM::VST4d16_UPD:
2904 case ARM::VST4d32_UPD:
2905 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2906 return MCDisassembler::Fail;
2907 break;
2908 case ARM::VST4q8:
2909 case ARM::VST4q16:
2910 case ARM::VST4q32:
2911 case ARM::VST4q8_UPD:
2912 case ARM::VST4q16_UPD:
2913 case ARM::VST4q32_UPD:
2914 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2915 return MCDisassembler::Fail;
2916 break;
2917 default:
2918 break;
2919 }
2920
2921 return S;
2922 }
2923
2924 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2925 uint64_t Address, const void *Decoder) {
2926 DecodeStatus S = MCDisassembler::Success;
2927
2928 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2929 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2930 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2931 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2932 unsigned align = fieldFromInstruction(Insn, 4, 1);
2933 unsigned size = fieldFromInstruction(Insn, 6, 2);
2934
2935 if (size == 0 && align == 1)
2936 return MCDisassembler::Fail;
2937 align *= (1 << size);
2938
2939 switch (Inst.getOpcode()) {
2940 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2941 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2942 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2943 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2944 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2945 return MCDisassembler::Fail;
2946 break;
2947 default:
2948 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2949 return MCDisassembler::Fail;
2950 break;
2951 }
2952 if (Rm != 0xF) {
2953 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2954 return MCDisassembler::Fail;
2955 }
2956
2957 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2958 return MCDisassembler::Fail;
2959 Inst.addOperand(MCOperand::createImm(align));
2960
2961 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2962 // variant encodes Rm == 0xf. Anything else is a register offset post-
2963 // increment and we need to add the register operand to the instruction.
2964 if (Rm != 0xD && Rm != 0xF &&
2965 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2966 return MCDisassembler::Fail;
2967
2968 return S;
2969 }
2970
2971 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2972 uint64_t Address, const void *Decoder) {
2973 DecodeStatus S = MCDisassembler::Success;
2974
2975 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2976 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2977 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2978 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2979 unsigned align = fieldFromInstruction(Insn, 4, 1);
2980 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2981 align *= 2*size;
2982
2983 switch (Inst.getOpcode()) {
2984 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2985 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2986 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2987 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2988 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2989 return MCDisassembler::Fail;
2990 break;
2991 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2992 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2993 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2994 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2995 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2996 return MCDisassembler::Fail;
2997 break;
2998 default:
2999 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3000 return MCDisassembler::Fail;
3001 break;
3002 }
3003
3004 if (Rm != 0xF)
3005 Inst.addOperand(MCOperand::createImm(0));
3006
3007 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3008 return MCDisassembler::Fail;
3009 Inst.addOperand(MCOperand::createImm(align));
3010
3011 if (Rm != 0xD && Rm != 0xF) {
3012 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3013 return MCDisassembler::Fail;
3014 }
3015
3016 return S;
3017 }
3018
3019 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
3020 uint64_t Address, const void *Decoder) {
3021 DecodeStatus S = MCDisassembler::Success;
3022
3023 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3024 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3025 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3026 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3027 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3028
3029 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3030 return MCDisassembler::Fail;
3031 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3032 return MCDisassembler::Fail;
3033 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3034 return MCDisassembler::Fail;
3035 if (Rm != 0xF) {
3036 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3037 return MCDisassembler::Fail;
3038 }
3039
3040 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3041 return MCDisassembler::Fail;
3042 Inst.addOperand(MCOperand::createImm(0));
3043
3044 if (Rm == 0xD)
3045 Inst.addOperand(MCOperand::createReg(0));
3046 else if (Rm != 0xF) {
3047 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3048 return MCDisassembler::Fail;
3049 }
3050
3051 return S;
3052 }
3053
3054 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
3055 uint64_t Address, const void *Decoder) {
3056 DecodeStatus S = MCDisassembler::Success;
3057
3058 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3059 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3060 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3061 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3062 unsigned size = fieldFromInstruction(Insn, 6, 2);
3063 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3064 unsigned align = fieldFromInstruction(Insn, 4, 1);
3065
3066 if (size == 0x3) {
3067 if (align == 0)
3068 return MCDisassembler::Fail;
3069 align = 16;
3070 } else {
3071 if (size == 2) {
3072 align *= 8;
3073 } else {
3074 size = 1 << size;
3075 align *= 4*size;
3076 }
3077 }
3078
3079 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3080 return MCDisassembler::Fail;
3081 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3082 return MCDisassembler::Fail;
3083 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3084 return MCDisassembler::Fail;
3085 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3086 return MCDisassembler::Fail;
3087 if (Rm != 0xF) {
3088 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3089 return MCDisassembler::Fail;
3090 }
3091
3092 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3093 return MCDisassembler::Fail;
3094 Inst.addOperand(MCOperand::createImm(align));
3095
3096 if (Rm == 0xD)
3097 Inst.addOperand(MCOperand::createReg(0));
3098 else if (Rm != 0xF) {
3099 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3100 return MCDisassembler::Fail;
3101 }
3102
3103 return S;
3104 }
3105
3106 static DecodeStatus
3107 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
3108 uint64_t Address, const void *Decoder) {
3109 DecodeStatus S = MCDisassembler::Success;
3110
3111 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3112 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3113 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3114 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3115 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3116 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3117 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3118 unsigned Q = fieldFromInstruction(Insn, 6, 1);
3119
3120 if (Q) {
3121 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3122 return MCDisassembler::Fail;
3123 } else {
3124 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3125 return MCDisassembler::Fail;
3126 }
3127
3128 Inst.addOperand(MCOperand::createImm(imm));
3129
3130 switch (Inst.getOpcode()) {
3131 case ARM::VORRiv4i16:
3132 case ARM::VORRiv2i32:
3133 case ARM::VBICiv4i16:
3134 case ARM::VBICiv2i32:
3135 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3136 return MCDisassembler::Fail;
3137 break;
3138 case ARM::VORRiv8i16:
3139 case ARM::VORRiv4i32:
3140 case ARM::VBICiv8i16:
3141 case ARM::VBICiv4i32:
3142 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3143 return MCDisassembler::Fail;
3144 break;
3145 default:
3146 break;
3147 }
3148
3149 return S;
3150 }
3151
3152 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3153 uint64_t Address, const void *Decoder) {
3154 DecodeStatus S = MCDisassembler::Success;
3155
3156 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3157 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3158 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3159 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3160 unsigned size = fieldFromInstruction(Insn, 18, 2);
3161
3162 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3163 return MCDisassembler::Fail;
3164 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3165 return MCDisassembler::Fail;
3166 Inst.addOperand(MCOperand::createImm(8 << size));
3167
3168 return S;
3169 }
3170
3171 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3172 uint64_t Address, const void *Decoder) {
3173 Inst.addOperand(MCOperand::createImm(8 - Val));
3174 return MCDisassembler::Success;
3175 }
3176
3177 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3178 uint64_t Address, const void *Decoder) {
3179 Inst.addOperand(MCOperand::createImm(16 - Val));
3180 return MCDisassembler::Success;
3181 }
3182
3183 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3184 uint64_t Address, const void *Decoder) {
3185 Inst.addOperand(MCOperand::createImm(32 - Val));
3186 return MCDisassembler::Success;
3187 }
3188
3189 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3190 uint64_t Address, const void *Decoder) {
3191 Inst.addOperand(MCOperand::createImm(64 - Val));
3192 return MCDisassembler::Success;
3193 }
3194
3195 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3196 uint64_t Address, const void *Decoder) {
3197 DecodeStatus S = MCDisassembler::Success;
3198
3199 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3200 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3201 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3202 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3203 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3204 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3205 unsigned op = fieldFromInstruction(Insn, 6, 1);
3206
3207 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3208 return MCDisassembler::Fail;
3209 if (op) {
3210 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3211 return MCDisassembler::Fail; // Writeback
3212 }
3213
3214 switch (Inst.getOpcode()) {
3215 case ARM::VTBL2:
3216 case ARM::VTBX2:
3217 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3218 return MCDisassembler::Fail;
3219 break;
3220 default:
3221 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3222 return MCDisassembler::Fail;
3223 }
3224
3225 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3226 return MCDisassembler::Fail;
3227
3228 return S;
3229 }
3230
3231 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3232 uint64_t Address, const void *Decoder) {
3233 DecodeStatus S = MCDisassembler::Success;
3234
3235 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3236 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3237
3238 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3239 return MCDisassembler::Fail;
3240
3241 switch(Inst.getOpcode()) {
3242 default:
3243 return MCDisassembler::Fail;
3244 case ARM::tADR:
3245 break; // tADR does not explicitly represent the PC as an operand.
3246 case ARM::tADDrSPi:
3247 Inst.addOperand(MCOperand::createReg(ARM::SP));
3248 break;
3249 }
3250
3251 Inst.addOperand(MCOperand::createImm(imm));
3252 return S;
3253 }
3254
3255 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3256 uint64_t Address, const void *Decoder) {
3257 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3258 true, 2, Inst, Decoder))
3259 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
3260 return MCDisassembler::Success;
3261 }
3262
3263 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3264 uint64_t Address, const void *Decoder) {
3265 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3266 true, 4, Inst, Decoder))
3267 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
3268 return MCDisassembler::Success;
3269 }
3270
3271 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3272 uint64_t Address, const void *Decoder) {
3273 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3274 true, 2, Inst, Decoder))
3275 Inst.addOperand(MCOperand::createImm(Val << 1));
3276 return MCDisassembler::Success;
3277 }
3278
3279 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3280 uint64_t Address, const void *Decoder) {
3281 DecodeStatus S = MCDisassembler::Success;
3282
3283 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3284 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3285
3286 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3287 return MCDisassembler::Fail;
3288 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3289 return MCDisassembler::Fail;
3290
3291 return S;
3292 }
3293
3294 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3295 uint64_t Address, const void *Decoder) {
3296 DecodeStatus S = MCDisassembler::Success;
3297
3298 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3299 unsigned imm = fieldFromInstruction(Val, 3, 5);
3300
3301 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3302 return MCDisassembler::Fail;
3303 Inst.addOperand(MCOperand::createImm(imm));
3304
3305 return S;
3306 }
3307
3308 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3309 uint64_t Address, const void *Decoder) {
3310 unsigned imm = Val << 2;
3311
3312 Inst.addOperand(MCOperand::createImm(imm));
3313 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3314
3315 return MCDisassembler::Success;
3316 }
3317
3318 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3319 uint64_t Address, const void *Decoder) {
3320 Inst.addOperand(MCOperand::createReg(ARM::SP));
3321 Inst.addOperand(MCOperand::createImm(Val));
3322
3323 return MCDisassembler::Success;
3324 }
3325
3326 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3327 uint64_t Address, const void *Decoder) {
3328 DecodeStatus S = MCDisassembler::Success;
3329
3330 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3331 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3332 unsigned imm = fieldFromInstruction(Val, 0, 2);
3333
3334 // Thumb stores cannot use PC as dest register.
3335 switch (Inst.getOpcode()) {
3336 case ARM::t2STRHs:
3337 case ARM::t2STRBs:
3338 case ARM::t2STRs:
3339 if (Rn == 15)
3340 return MCDisassembler::Fail;
3341 break;
3342 default:
3343 break;
3344 }
3345
3346 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3347 return MCDisassembler::Fail;
3348 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3349 return MCDisassembler::Fail;
3350 Inst.addOperand(MCOperand::createImm(imm));
3351
3352 return S;
3353 }
3354
3355 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3356 uint64_t Address, const void *Decoder) {
3357 DecodeStatus S = MCDisassembler::Success;
3358
3359 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3360 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3361
3362 const FeatureBitset &featureBits =
3363 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3364
3365 bool hasMP = featureBits[ARM::FeatureMP];
3366 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3367
3368 if (Rn == 15) {
3369 switch (Inst.getOpcode()) {
3370 case ARM::t2LDRBs:
3371 Inst.setOpcode(ARM::t2LDRBpci);
3372 break;
3373 case ARM::t2LDRHs:
3374 Inst.setOpcode(ARM::t2LDRHpci);
3375 break;
3376 case ARM::t2LDRSHs:
3377 Inst.setOpcode(ARM::t2LDRSHpci);
3378 break;
3379 case ARM::t2LDRSBs:
3380 Inst.setOpcode(ARM::t2LDRSBpci);
3381 break;
3382 case ARM::t2LDRs:
3383 Inst.setOpcode(ARM::t2LDRpci);
3384 break;
3385 case ARM::t2PLDs:
3386 Inst.setOpcode(ARM::t2PLDpci);
3387 break;
3388 case ARM::t2PLIs:
3389 Inst.setOpcode(ARM::t2PLIpci);
3390 break;
3391 default:
3392 return MCDisassembler::Fail;
3393 }
3394
3395 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3396 }
3397
3398 if (Rt == 15) {
3399 switch (Inst.getOpcode()) {
3400 case ARM::t2LDRSHs:
3401 return MCDisassembler::Fail;
3402 case ARM::t2LDRHs:
3403 Inst.setOpcode(ARM::t2PLDWs);
3404 break;
3405 case ARM::t2LDRSBs:
3406 Inst.setOpcode(ARM::t2PLIs);
3407 break;
3408 default:
3409 break;
3410 }
3411 }
3412
3413 switch (Inst.getOpcode()) {
3414 case ARM::t2PLDs:
3415 break;
3416 case ARM::t2PLIs:
3417 if (!hasV7Ops)
3418 return MCDisassembler::Fail;
3419 break;
3420 case ARM::t2PLDWs:
3421 if (!hasV7Ops || !hasMP)
3422 return MCDisassembler::Fail;
3423 break;
3424 default:
3425 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3426 return MCDisassembler::Fail;
3427 }
3428
3429 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3430 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3431 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3432 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3433 return MCDisassembler::Fail;
3434
3435 return S;
3436 }
3437
3438 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3439 uint64_t Address, const void* Decoder) {
3440 DecodeStatus S = MCDisassembler::Success;
3441
3442 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3443 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3444 unsigned U = fieldFromInstruction(Insn, 9, 1);
3445 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3446 imm |= (U << 8);
3447 imm |= (Rn << 9);
3448 unsigned add = fieldFromInstruction(Insn, 9, 1);
3449
3450 const FeatureBitset &featureBits =
3451 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3452
3453 bool hasMP = featureBits[ARM::FeatureMP];
3454 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3455
3456 if (Rn == 15) {
3457 switch (Inst.getOpcode()) {
3458 case ARM::t2LDRi8:
3459 Inst.setOpcode(ARM::t2LDRpci);
3460 break;
3461 case ARM::t2LDRBi8:
3462 Inst.setOpcode(ARM::t2LDRBpci);
3463 break;
3464 case ARM::t2LDRSBi8:
3465 Inst.setOpcode(ARM::t2LDRSBpci);
3466 break;
3467 case ARM::t2LDRHi8:
3468 Inst.setOpcode(ARM::t2LDRHpci);
3469 break;
3470 case ARM::t2LDRSHi8:
3471 Inst.setOpcode(ARM::t2LDRSHpci);
3472 break;
3473 case ARM::t2PLDi8:
3474 Inst.setOpcode(ARM::t2PLDpci);
3475 break;
3476 case ARM::t2PLIi8:
3477 Inst.setOpcode(ARM::t2PLIpci);
3478 break;
3479 default:
3480 return MCDisassembler::Fail;
3481 }
3482 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3483 }
3484
3485 if (Rt == 15) {
3486 switch (Inst.getOpcode()) {
3487 case ARM::t2LDRSHi8:
3488 return MCDisassembler::Fail;
3489 case ARM::t2LDRHi8:
3490 if (!add)
3491 Inst.setOpcode(ARM::t2PLDWi8);
3492 break;
3493 case ARM::t2LDRSBi8:
3494 Inst.setOpcode(ARM::t2PLIi8);
3495 break;
3496 default:
3497 break;
3498 }
3499 }
3500
3501 switch (Inst.getOpcode()) {
3502 case ARM::t2PLDi8:
3503 break;
3504 case ARM::t2PLIi8:
3505 if (!hasV7Ops)
3506 return MCDisassembler::Fail;
3507 break;
3508 case ARM::t2PLDWi8:
3509 if (!hasV7Ops || !hasMP)
3510 return MCDisassembler::Fail;
3511 break;
3512 default:
3513 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3514 return MCDisassembler::Fail;
3515 }
3516
3517 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3518 return MCDisassembler::Fail;
3519 return S;
3520 }
3521
3522 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3523 uint64_t Address, const void* Decoder) {
3524 DecodeStatus S = MCDisassembler::Success;
3525
3526 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3527 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3528 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3529 imm |= (Rn << 13);
3530
3531 const FeatureBitset &featureBits =
3532 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3533
3534 bool hasMP = featureBits[ARM::FeatureMP];
3535 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3536
3537 if (Rn == 15) {
3538 switch (Inst.getOpcode()) {
3539 case ARM::t2LDRi12:
3540 Inst.setOpcode(ARM::t2LDRpci);
3541 break;
3542 case ARM::t2LDRHi12:
3543 Inst.setOpcode(ARM::t2LDRHpci);
3544 break;
3545 case ARM::t2LDRSHi12:
3546 Inst.setOpcode(ARM::t2LDRSHpci);
3547 break;
3548 case ARM::t2LDRBi12:
3549 Inst.setOpcode(ARM::t2LDRBpci);
3550 break;
3551 case ARM::t2LDRSBi12:
3552 Inst.setOpcode(ARM::t2LDRSBpci);
3553 break;
3554 case ARM::t2PLDi12:
3555 Inst.setOpcode(ARM::t2PLDpci);
3556 break;
3557 case ARM::t2PLIi12:
3558 Inst.setOpcode(ARM::t2PLIpci);
3559 break;
3560 default:
3561 return MCDisassembler::Fail;
3562 }
3563 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3564 }
3565
3566 if (Rt == 15) {
3567 switch (Inst.getOpcode()) {
3568 case ARM::t2LDRSHi12:
3569 return MCDisassembler::Fail;
3570 case ARM::t2LDRHi12:
3571 Inst.setOpcode(ARM::t2PLDWi12);
3572 break;
3573 case ARM::t2LDRSBi12:
3574 Inst.setOpcode(ARM::t2PLIi12);
3575 break;
3576 default:
3577 break;
3578 }
3579 }
3580
3581 switch (Inst.getOpcode()) {
3582 case ARM::t2PLDi12:
3583 break;
3584 case ARM::t2PLIi12:
3585 if (!hasV7Ops)
3586 return MCDisassembler::Fail;
3587 break;
3588 case ARM::t2PLDWi12:
3589 if (!hasV7Ops || !hasMP)
3590 return MCDisassembler::Fail;
3591 break;
3592 default:
3593 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3594 return MCDisassembler::Fail;
3595 }
3596
3597 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3598 return MCDisassembler::Fail;
3599 return S;
3600 }
3601
3602 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
3603 uint64_t Address, const void* Decoder) {
3604 DecodeStatus S = MCDisassembler::Success;
3605
3606 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3607 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3608 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3609 imm |= (Rn << 9);
3610
3611 if (Rn == 15) {
3612 switch (Inst.getOpcode()) {
3613 case ARM::t2LDRT:
3614 Inst.setOpcode(ARM::t2LDRpci);
3615 break;
3616 case ARM::t2LDRBT:
3617 Inst.setOpcode(ARM::t2LDRBpci);
3618 break;
3619 case ARM::t2LDRHT:
3620 Inst.setOpcode(ARM::t2LDRHpci);
3621 break;
3622 case ARM::t2LDRSBT:
3623 Inst.setOpcode(ARM::t2LDRSBpci);
3624 break;
3625 case ARM::t2LDRSHT:
3626 Inst.setOpcode(ARM::t2LDRSHpci);
3627 break;
3628 default:
3629 return MCDisassembler::Fail;
3630 }
3631 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3632 }
3633
3634 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3635 return MCDisassembler::Fail;
3636 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3637 return MCDisassembler::Fail;
3638 return S;
3639 }
3640
3641 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
3642 uint64_t Address, const void* Decoder) {
3643 DecodeStatus S = MCDisassembler::Success;
3644
3645 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3646 unsigned U = fieldFromInstruction(Insn, 23, 1);
3647 int imm = fieldFromInstruction(Insn, 0, 12);
3648
3649 const FeatureBitset &featureBits =
3650 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3651
3652 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3653
3654 if (Rt == 15) {
3655 switch (Inst.getOpcode()) {
3656 case ARM::t2LDRBpci:
3657 case ARM::t2LDRHpci:
3658 Inst.setOpcode(ARM::t2PLDpci);
3659 break;
3660 case ARM::t2LDRSBpci:
3661 Inst.setOpcode(ARM::t2PLIpci);
3662 break;
3663 case ARM::t2LDRSHpci:
3664 return MCDisassembler::Fail;
3665 default:
3666 break;
3667 }
3668 }
3669
3670 switch(Inst.getOpcode()) {
3671 case ARM::t2PLDpci:
3672 break;
3673 case ARM::t2PLIpci:
3674 if (!hasV7Ops)
3675 return MCDisassembler::Fail;
3676 break;
3677 default:
3678 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3679 return MCDisassembler::Fail;
3680 }
3681
3682 if (!U) {
3683 // Special case for #-0.
3684 if (imm == 0)
3685 imm = INT32_MIN;
3686 else
3687 imm = -imm;
3688 }
3689 Inst.addOperand(MCOperand::createImm(imm));
3690
3691 return S;
3692 }
3693
3694 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3695 uint64_t Address, const void *Decoder) {
3696 if (Val == 0)
3697 Inst.addOperand(MCOperand::createImm(INT32_MIN));
3698 else {
3699 int imm = Val & 0xFF;
3700
3701 if (!(Val & 0x100)) imm *= -1;
3702 Inst.addOperand(MCOperand::createImm(imm * 4));
3703 }
3704
3705 return MCDisassembler::Success;
3706 }
3707
3708 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3709 uint64_t Address, const void *Decoder) {
3710 DecodeStatus S = MCDisassembler::Success;
3711
3712 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3713 unsigned imm = fieldFromInstruction(Val, 0, 9);
3714
3715 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3716 return MCDisassembler::Fail;
3717 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3718 return MCDisassembler::Fail;
3719
3720 return S;
3721 }
3722
3723 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
3724 uint64_t Address, const void *Decoder) {
3725 DecodeStatus S = MCDisassembler::Success;
3726
3727 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3728 unsigned imm = fieldFromInstruction(Val, 0, 8);
3729
3730 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3731 return MCDisassembler::Fail;
3732
3733 Inst.addOperand(MCOperand::createImm(imm));
3734
3735 return S;
3736 }
3737
3738 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3739 uint64_t Address, const void *Decoder) {
3740 int imm = Val & 0xFF;
3741 if (Val == 0)
3742 imm = INT32_MIN;
3743 else if (!(Val & 0x100))
3744 imm *= -1;
3745 Inst.addOperand(MCOperand::createImm(imm));
3746
3747 return MCDisassembler::Success;
3748 }
3749
3750 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3751 uint64_t Address, const void *Decoder) {
3752 DecodeStatus S = MCDisassembler::Success;
3753
3754 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3755 unsigned imm = fieldFromInstruction(Val, 0, 9);
3756
3757 // Thumb stores cannot use PC as dest register.
3758 switch (Inst.getOpcode()) {
3759 case ARM::t2STRT:
3760 case ARM::t2STRBT:
3761 case ARM::t2STRHT:
3762 case ARM::t2STRi8:
3763 case ARM::t2STRHi8:
3764 case ARM::t2STRBi8:
3765 if (Rn == 15)
3766 return MCDisassembler::Fail;
3767 break;
3768 default:
3769 break;
3770 }
3771
3772 // Some instructions always use an additive offset.
3773 switch (Inst.getOpcode()) {
3774 case ARM::t2LDRT:
3775 case ARM::t2LDRBT:
3776 case ARM::t2LDRHT:
3777 case ARM::t2LDRSBT:
3778 case ARM::t2LDRSHT:
3779 case ARM::t2STRT:
3780 case ARM::t2STRBT:
3781 case ARM::t2STRHT:
3782 imm |= 0x100;
3783 break;
3784 default:
3785 break;
3786 }
3787
3788 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3789 return MCDisassembler::Fail;
3790 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3791 return MCDisassembler::Fail;
3792
3793 return S;
3794 }
3795
3796 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3797 uint64_t Address, const void *Decoder) {
3798 DecodeStatus S = MCDisassembler::Success;
3799
3800 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3801 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3802 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3803 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3804 addr |= Rn << 9;
3805 unsigned load = fieldFromInstruction(Insn, 20, 1);
3806
3807 if (Rn == 15) {
3808 switch (Inst.getOpcode()) {
3809 case ARM::t2LDR_PRE:
3810 case ARM::t2LDR_POST:
3811 Inst.setOpcode(ARM::t2LDRpci);
3812 break;
3813 case ARM::t2LDRB_PRE:
3814 case ARM::t2LDRB_POST:
3815 Inst.setOpcode(ARM::t2LDRBpci);
3816 break;
3817 case ARM::t2LDRH_PRE:
3818 case ARM::t2LDRH_POST:
3819 Inst.setOpcode(ARM::t2LDRHpci);
3820 break;
3821 case ARM::t2LDRSB_PRE:
3822 case ARM::t2LDRSB_POST:
3823 if (Rt == 15)
3824 Inst.setOpcode(ARM::t2PLIpci);
3825 else
3826 Inst.setOpcode(ARM::t2LDRSBpci);
3827 break;
3828 case ARM::t2LDRSH_PRE:
3829 case ARM::t2LDRSH_POST:
3830 Inst.setOpcode(ARM::t2LDRSHpci);
3831 break;
3832 default:
3833 return MCDisassembler::Fail;
3834 }
3835 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3836 }
3837
3838 if (!load) {
3839 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3840 return MCDisassembler::Fail;
3841 }
3842
3843 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3844 return MCDisassembler::Fail;
3845
3846 if (load) {
3847 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3848 return MCDisassembler::Fail;
3849 }
3850
3851 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3852 return MCDisassembler::Fail;
3853
3854 return S;
3855 }
3856
3857 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3858 uint64_t Address, const void *Decoder) {
3859 DecodeStatus S = MCDisassembler::Success;
3860
3861 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3862 unsigned imm = fieldFromInstruction(Val, 0, 12);
3863
3864 // Thumb stores cannot use PC as dest register.
3865 switch (Inst.getOpcode()) {
3866 case ARM::t2STRi12:
3867 case ARM::t2STRBi12:
3868 case ARM::t2STRHi12:
3869 if (Rn == 15)
3870 return MCDisassembler::Fail;
3871 break;
3872 default:
3873 break;
3874 }
3875
3876 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3877 return MCDisassembler::Fail;
3878 Inst.addOperand(MCOperand::createImm(imm));
3879
3880 return S;
3881 }
3882
3883 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3884 uint64_t Address, const void *Decoder) {
3885 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3886
3887 Inst.addOperand(MCOperand::createReg(ARM::SP));
3888 Inst.addOperand(MCOperand::createReg(ARM::SP));
3889 Inst.addOperand(MCOperand::createImm(imm));
3890
3891 return MCDisassembler::Success;
3892 }
3893
3894 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3895 uint64_t Address, const void *Decoder) {
3896 DecodeStatus S = MCDisassembler::Success;
3897
3898 if (Inst.getOpcode() == ARM::tADDrSP) {
3899 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3900 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3901
3902 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3903 return MCDisassembler::Fail;
3904 Inst.addOperand(MCOperand::createReg(ARM::SP));
3905 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3906 return MCDisassembler::Fail;
3907 } else if (Inst.getOpcode() == ARM::tADDspr) {
3908 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3909
3910 Inst.addOperand(MCOperand::createReg(ARM::SP));
3911 Inst.addOperand(MCOperand::createReg(ARM::SP));
3912 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3913 return MCDisassembler::Fail;
3914 }
3915
3916 return S;
3917 }
3918
3919 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3920 uint64_t Address, const void *Decoder) {
3921 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3922 unsigned flags = fieldFromInstruction(Insn, 0, 3);
3923
3924 Inst.addOperand(MCOperand::createImm(imod));
3925 Inst.addOperand(MCOperand::createImm(flags));
3926
3927 return MCDisassembler::Success;
3928 }
3929
3930 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3931 uint64_t Address, const void *Decoder) {
3932 DecodeStatus S = MCDisassembler::Success;
3933 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3934 unsigned add = fieldFromInstruction(Insn, 4, 1);
3935
3936 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3937 return MCDisassembler::Fail;
3938 Inst.addOperand(MCOperand::createImm(add));
3939
3940 return S;
3941 }
3942
3943 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3944 uint64_t Address, const void *Decoder) {
3945 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3946 // Note only one trailing zero not two. Also the J1 and J2 values are from
3947 // the encoded instruction. So here change to I1 and I2 values via:
3948 // I1 = NOT(J1 EOR S);
3949 // I2 = NOT(J2 EOR S);
3950 // and build the imm32 with two trailing zeros as documented:
3951 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3952 unsigned S = (Val >> 23) & 1;
3953 unsigned J1 = (Val >> 22) & 1;
3954 unsigned J2 = (Val >> 21) & 1;
3955 unsigned I1 = !(J1 ^ S);
3956 unsigned I2 = !(J2 ^ S);
3957 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3958 int imm32 = SignExtend32<25>(tmp << 1);
3959
3960 if (!tryAddingSymbolicOperand(Address,
3961 (Address & ~2u) + imm32 + 4,
3962 true, 4, Inst, Decoder))
3963 Inst.addOperand(MCOperand::createImm(imm32));
3964 return MCDisassembler::Success;
3965 }
3966
3967 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3968 uint64_t Address, const void *Decoder) {
3969 if (Val == 0xA || Val == 0xB)
3970 return MCDisassembler::Fail;
3971
3972 const FeatureBitset &featureBits =
3973 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3974
3975 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
3976 return MCDisassembler::Fail;
3977
3978 Inst.addOperand(MCOperand::createImm(Val));
3979 return MCDisassembler::Success;
3980 }
3981
3982 static DecodeStatus
3983 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3984 uint64_t Address, const void *Decoder) {
3985 DecodeStatus S = MCDisassembler::Success;
3986
3987 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3988 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3989
3990 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3991 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3992 return MCDisassembler::Fail;
3993 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3994 return MCDisassembler::Fail;
3995 return S;
3996 }
3997
3998 static DecodeStatus
3999 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
4000 uint64_t Address, const void *Decoder) {
4001 DecodeStatus S = MCDisassembler::Success;
4002
4003 unsigned pred = fieldFromInstruction(Insn, 22, 4);
4004 if (pred == 0xE || pred == 0xF) {
4005 unsigned opc = fieldFromInstruction(Insn, 4, 28);
4006 switch (opc) {
4007 default:
4008 return MCDisassembler::Fail;
4009 case 0xf3bf8f4:
4010 Inst.setOpcode(ARM::t2DSB);
4011 break;
4012 case 0xf3bf8f5:
4013 Inst.setOpcode(ARM::t2DMB);
4014 break;
4015 case 0xf3bf8f6:
4016 Inst.setOpcode(ARM::t2ISB);
4017 break;
4018 }
4019
4020 unsigned imm = fieldFromInstruction(Insn, 0, 4);
4021 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
4022 }
4023
4024 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
4025 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
4026 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
4027 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
4028 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
4029
4030 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
4031 return MCDisassembler::Fail;
4032 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4033 return MCDisassembler::Fail;
4034
4035 return S;
4036 }
4037
4038 // Decode a shifted immediate operand. These basically consist
4039 // of an 8-bit value, and a 4-bit directive that specifies either
4040 // a splat operation or a rotation.
4041 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
4042 uint64_t Address, const void *Decoder) {
4043 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
4044 if (ctrl == 0) {
4045 unsigned byte = fieldFromInstruction(Val, 8, 2);
4046 unsigned imm = fieldFromInstruction(Val, 0, 8);
4047 switch (byte) {
4048 case 0:
4049 Inst.addOperand(MCOperand::createImm(imm));
4050 break;
4051 case 1:
4052 Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
4053 break;
4054 case 2:
4055 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
4056 break;
4057 case 3:
4058 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
4059 (imm << 8) | imm));
4060 break;
4061 }
4062 } else {
4063 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
4064 unsigned rot = fieldFromInstruction(Val, 7, 5);
4065 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
4066 Inst.addOperand(MCOperand::createImm(imm));
4067 }
4068
4069 return MCDisassembler::Success;
4070 }
4071
4072 static DecodeStatus
4073 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
4074 uint64_t Address, const void *Decoder) {
4075 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
4076 true, 2, Inst, Decoder))
4077 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
4078 return MCDisassembler::Success;
4079 }
4080
4081 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
4082 uint64_t Address,
4083 const void *Decoder) {
4084 // Val is passed in as S:J1:J2:imm10:imm11
4085 // Note no trailing zero after imm11. Also the J1 and J2 values are from
4086 // the encoded instruction. So here change to I1 and I2 values via:
4087 // I1 = NOT(J1 EOR S);
4088 // I2 = NOT(J2 EOR S);
4089 // and build the imm32 with one trailing zero as documented:
4090 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
4091 unsigned S = (Val >> 23) & 1;
4092 unsigned J1 = (Val >> 22) & 1;
4093 unsigned J2 = (Val >> 21) & 1;
4094 unsigned I1 = !(J1 ^ S);
4095 unsigned I2 = !(J2 ^ S);
4096 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4097 int imm32 = SignExtend32<25>(tmp << 1);
4098
4099 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
4100 true, 4, Inst, Decoder))
4101 Inst.addOperand(MCOperand::createImm(imm32));
4102 return MCDisassembler::Success;
4103 }
4104
4105 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
4106 uint64_t Address, const void *Decoder) {
4107 if (Val & ~0xf)
4108 return MCDisassembler::Fail;
4109
4110 Inst.addOperand(MCOperand::createImm(Val));
4111 return MCDisassembler::Success;
4112 }
4113
4114 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
4115 uint64_t Address, const void *Decoder) {
4116 if (Val & ~0xf)
4117 return MCDisassembler::Fail;
4118
4119 Inst.addOperand(MCOperand::createImm(Val));
4120 return MCDisassembler::Success;
4121 }
4122
4123 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
4124 uint64_t Address, const void *Decoder) {
4125 DecodeStatus S = MCDisassembler::Success;
4126 const FeatureBitset &FeatureBits =
4127 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4128
4129 if (FeatureBits[ARM::FeatureMClass]) {
4130 unsigned ValLow = Val & 0xff;
4131
4132 // Validate the SYSm value first.
4133 switch (ValLow) {
4134 case 0: // apsr
4135 case 1: // iapsr
4136 case 2: // eapsr
4137 case 3: // xpsr
4138 case 5: // ipsr
4139 case 6: // epsr
4140 case 7: // iepsr
4141 case 8: // msp
4142 case 9: // psp
4143 case 16: // primask
4144 case 20: // control
4145 break;
4146 case 17: // basepri
4147 case 18: // basepri_max
4148 case 19: // faultmask
4149 if (!(FeatureBits[ARM::HasV7Ops]))
4150 // Values basepri, basepri_max and faultmask are only valid for v7m.
4151 return MCDisassembler::Fail;
4152 break;
4153 case 0x8a: // msplim_ns
4154 case 0x8b: // psplim_ns
4155 case 0x91: // basepri_ns
4156 case 0x93: // faultmask_ns
4157 if (!(FeatureBits[ARM::HasV8MMainlineOps]))
4158 return MCDisassembler::Fail;
4159 LLVM_FALLTHROUGH;
4160 case 10: // msplim
4161 case 11: // psplim
4162 case 0x88: // msp_ns
4163 case 0x89: // psp_ns
4164 case 0x90: // primask_ns
4165 case 0x94: // control_ns
4166 case 0x98: // sp_ns
4167 if (!(FeatureBits[ARM::Feature8MSecExt]))
4168 return MCDisassembler::Fail;
4169 break;
4170 default:
4171 // Architecturally defined as unpredictable
4172 S = MCDisassembler::SoftFail;
4173 break;
4174 }
4175
4176 if (Inst.getOpcode() == ARM::t2MSR_M) {
4177 unsigned Mask = fieldFromInstruction(Val, 10, 2);
4178 if (!(FeatureBits[ARM::HasV7Ops])) {
4179 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4180 // unpredictable.
4181 if (Mask != 2)
4182 S = MCDisassembler::SoftFail;
4183 }
4184 else {
4185 // The ARMv7-M architecture stores an additional 2-bit mask value in
4186 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4187 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4188 // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4189 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4190 // only if the processor includes the DSP extension.
4191 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4192 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
4193 S = MCDisassembler::SoftFail;
4194 }
4195 }
4196 } else {
4197 // A/R class
4198 if (Val == 0)
4199 return MCDisassembler::Fail;
4200 }
4201 Inst.addOperand(MCOperand::createImm(Val));
4202 return S;
4203 }
4204
4205 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4206 uint64_t Address, const void *Decoder) {
4207 unsigned R = fieldFromInstruction(Val, 5, 1);
4208 unsigned SysM = fieldFromInstruction(Val, 0, 5);
4209
4210 // The table of encodings for these banked registers comes from B9.2.3 of the
4211 // ARM ARM. There are patterns, but nothing regular enough to make this logic
4212 // neater. So by fiat, these values are UNPREDICTABLE:
4213 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM))
4214 return MCDisassembler::Fail;
4215
4216 Inst.addOperand(MCOperand::createImm(Val));
4217 return MCDisassembler::Success;
4218 }
4219
4220 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
4221 uint64_t Address, const void *Decoder) {
4222 DecodeStatus S = MCDisassembler::Success;
4223
4224 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4225 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4226 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4227
4228 if (Rn == 0xF)
4229 S = MCDisassembler::SoftFail;
4230
4231 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4232 return MCDisassembler::Fail;
4233 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4234 return MCDisassembler::Fail;
4235 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4236 return MCDisassembler::Fail;
4237
4238 return S;
4239 }
4240
4241 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4242 uint64_t Address,
4243 const void *Decoder) {
4244 DecodeStatus S = MCDisassembler::Success;
4245
4246 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4247 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4248 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4249 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4250
4251 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4252 return MCDisassembler::Fail;
4253
4254 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4255 S = MCDisassembler::SoftFail;
4256
4257 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4258 return MCDisassembler::Fail;
4259 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4260 return MCDisassembler::Fail;
4261 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4262 return MCDisassembler::Fail;
4263
4264 return S;
4265 }
4266
4267 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4268 uint64_t Address, const void *Decoder) {
4269 DecodeStatus S = MCDisassembler::Success;
4270
4271 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4272 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4273 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4274 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4275 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4276 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4277
4278 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4279
4280 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4281 return MCDisassembler::Fail;
4282 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4283 return MCDisassembler::Fail;
4284 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4285 return MCDisassembler::Fail;
4286 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4287 return MCDisassembler::Fail;
4288
4289 return S;
4290 }
4291
4292 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4293 uint64_t Address, const void *Decoder) {
4294 DecodeStatus S = MCDisassembler::Success;
4295
4296 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4297 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4298 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4299 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4300 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4301 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4302 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4303
4304 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4305 if (Rm == 0xF) S = MCDisassembler::SoftFail;
4306
4307 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4308 return MCDisassembler::Fail;
4309 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4310 return MCDisassembler::Fail;
4311 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4312 return MCDisassembler::Fail;
4313 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4314 return MCDisassembler::Fail;
4315
4316 return S;
4317 }
4318
4319 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4320 uint64_t Address, const void *Decoder) {
4321 DecodeStatus S = MCDisassembler::Success;
4322
4323 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4324 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4325 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4326 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4327 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4328 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4329
4330 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4331
4332 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4333 return MCDisassembler::Fail;
4334 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4335 return MCDisassembler::Fail;
4336 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4337 return MCDisassembler::Fail;
4338 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4339 return MCDisassembler::Fail;
4340
4341 return S;
4342 }
4343
4344 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4345 uint64_t Address, const void *Decoder) {
4346 DecodeStatus S = MCDisassembler::Success;
4347
4348 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4349 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4350 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4351 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4352 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4353 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4354
4355 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4356
4357 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4358 return MCDisassembler::Fail;
4359 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4360 return MCDisassembler::Fail;
4361 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4362 return MCDisassembler::Fail;
4363 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4364 return MCDisassembler::Fail;
4365
4366 return S;
4367 }
4368
4369 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4370 uint64_t Address, const void *Decoder) {
4371 DecodeStatus S = MCDisassembler::Success;
4372
4373 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4374 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4375 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4376 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4377 unsigned size = fieldFromInstruction(Insn, 10, 2);
4378
4379 unsigned align = 0;
4380 unsigned index = 0;
4381 switch (size) {
4382 default:
4383 return MCDisassembler::Fail;
4384 case 0:
4385 if (fieldFromInstruction(Insn, 4, 1))
4386 return MCDisassembler::Fail; // UNDEFINED
4387 index = fieldFromInstruction(Insn, 5, 3);
4388 break;
4389 case 1:
4390 if (fieldFromInstruction(Insn, 5, 1))
4391 return MCDisassembler::Fail; // UNDEFINED
4392 index = fieldFromInstruction(Insn, 6, 2);
4393 if (fieldFromInstruction(Insn, 4, 1))
4394 align = 2;
4395 break;
4396 case 2:
4397 if (fieldFromInstruction(Insn, 6, 1))
4398 return MCDisassembler::Fail; // UNDEFINED
4399 index = fieldFromInstruction(Insn, 7, 1);
4400
4401 switch (fieldFromInstruction(Insn, 4, 2)) {
4402 case 0 :
4403 align = 0; break;
4404 case 3:
4405 align = 4; break;
4406 default:
4407 return MCDisassembler::Fail;
4408 }
4409 break;
4410 }
4411
4412 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4413 return MCDisassembler::Fail;
4414 if (Rm != 0xF) { // Writeback
4415 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4416 return MCDisassembler::Fail;
4417 }
4418 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4419 return MCDisassembler::Fail;
4420 Inst.addOperand(MCOperand::createImm(align));
4421 if (Rm != 0xF) {
4422 if (Rm != 0xD) {
4423 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4424 return MCDisassembler::Fail;
4425 } else
4426 Inst.addOperand(MCOperand::createReg(0));
4427 }
4428
4429 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4430 return MCDisassembler::Fail;
4431 Inst.addOperand(MCOperand::createImm(index));
4432
4433 return S;
4434 }
4435
4436 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
4437 uint64_t Address, const void *Decoder) {
4438 DecodeStatus S = MCDisassembler::Success;
4439
4440 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4441 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4442 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4443 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4444 unsigned size = fieldFromInstruction(Insn, 10, 2);
4445
4446 unsigned align = 0;
4447 unsigned index = 0;
4448 switch (size) {
4449 default:
4450 return MCDisassembler::Fail;
4451 case 0:
4452 if (fieldFromInstruction(Insn, 4, 1))
4453 return MCDisassembler::Fail; // UNDEFINED
4454 index = fieldFromInstruction(Insn, 5, 3);
4455 break;
4456 case 1:
4457 if (fieldFromInstruction(Insn, 5, 1))
4458 return MCDisassembler::Fail; // UNDEFINED
4459 index = fieldFromInstruction(Insn, 6, 2);
4460 if (fieldFromInstruction(Insn, 4, 1))
4461 align = 2;
4462 break;
4463 case 2:
4464 if (fieldFromInstruction(Insn, 6, 1))
4465 return MCDisassembler::Fail; // UNDEFINED
4466 index = fieldFromInstruction(Insn, 7, 1);
4467
4468 switch (fieldFromInstruction(Insn, 4, 2)) {
4469 case 0:
4470 align = 0; break;
4471 case 3:
4472 align = 4; break;
4473 default:
4474 return MCDisassembler::Fail;
4475 }
4476 break;
4477 }
4478
4479 if (Rm != 0xF) { // Writeback
4480 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4481 return MCDisassembler::Fail;
4482 }
4483 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4484 return MCDisassembler::Fail;
4485 Inst.addOperand(MCOperand::createImm(align));
4486 if (Rm != 0xF) {
4487 if (Rm != 0xD) {
4488 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4489 return MCDisassembler::Fail;
4490 } else
4491 Inst.addOperand(MCOperand::createReg(0));
4492 }
4493
4494 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4495 return MCDisassembler::Fail;
4496 Inst.addOperand(MCOperand::createImm(index));
4497
4498 return S;
4499 }
4500
4501 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
4502 uint64_t Address, const void *Decoder) {
4503 DecodeStatus S = MCDisassembler::Success;
4504
4505 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4506 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4507 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4508 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4509 unsigned size = fieldFromInstruction(Insn, 10, 2);
4510
4511 unsigned align = 0;
4512 unsigned index = 0;
4513 unsigned inc = 1;
4514 switch (size) {
4515 default:
4516 return MCDisassembler::Fail;
4517 case 0:
4518 index = fieldFromInstruction(Insn, 5, 3);
4519 if (fieldFromInstruction(Insn, 4, 1))
4520 align = 2;
4521 break;
4522 case 1:
4523 index = fieldFromInstruction(Insn, 6, 2);
4524 if (fieldFromInstruction(Insn, 4, 1))
4525 align = 4;
4526 if (fieldFromInstruction(Insn, 5, 1))
4527 inc = 2;
4528 break;
4529 case 2:
4530 if (fieldFromInstruction(Insn, 5, 1))
4531 return MCDisassembler::Fail; // UNDEFINED
4532 index = fieldFromInstruction(Insn, 7, 1);
4533 if (fieldFromInstruction(Insn, 4, 1) != 0)
4534 align = 8;
4535 if (fieldFromInstruction(Insn, 6, 1))
4536 inc = 2;
4537 break;
4538 }
4539
4540 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4541 return MCDisassembler::Fail;
4542 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4543 return MCDisassembler::Fail;
4544 if (Rm != 0xF) { // Writeback
4545 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4546 return MCDisassembler::Fail;
4547 }
4548 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4549 return MCDisassembler::Fail;
4550 Inst.addOperand(MCOperand::createImm(align));
4551 if (Rm != 0xF) {
4552 if (Rm != 0xD) {
4553 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4554 return MCDisassembler::Fail;
4555 } else
4556 Inst.addOperand(MCOperand::createReg(0));
4557 }
4558
4559 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4560 return MCDisassembler::Fail;
4561 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4562 return MCDisassembler::Fail;
4563 Inst.addOperand(MCOperand::createImm(index));
4564
4565 return S;
4566 }
4567
4568 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
4569 uint64_t Address, const void *Decoder) {
4570 DecodeStatus S = MCDisassembler::Success;
4571
4572 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4573 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4574 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4575 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4576 unsigned size = fieldFromInstruction(Insn, 10, 2);
4577
4578 unsigned align = 0;
4579 unsigned index = 0;
4580 unsigned inc = 1;
4581 switch (size) {
4582 default:
4583 return MCDisassembler::Fail;
4584 case 0:
4585 index = fieldFromInstruction(Insn, 5, 3);
4586 if (fieldFromInstruction(Insn, 4, 1))
4587 align = 2;
4588 break;
4589 case 1:
4590 index = fieldFromInstruction(Insn, 6, 2);
4591 if (fieldFromInstruction(Insn, 4, 1))
4592 align = 4;
4593 if (fieldFromInstruction(Insn, 5, 1))
4594 inc = 2;
4595 break;
4596 case 2:
4597 if (fieldFromInstruction(Insn, 5, 1))
4598 return MCDisassembler::Fail; // UNDEFINED
4599 index = fieldFromInstruction(Insn, 7, 1);
4600 if (fieldFromInstruction(Insn, 4, 1) != 0)
4601 align = 8;
4602 if (fieldFromInstruction(Insn, 6, 1))
4603 inc = 2;
4604 break;
4605 }
4606
4607 if (Rm != 0xF) { // Writeback
4608 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4609 return MCDisassembler::Fail;
4610 }
4611 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4612 return MCDisassembler::Fail;
4613 Inst.addOperand(MCOperand::createImm(align));
4614 if (Rm != 0xF) {
4615 if (Rm != 0xD) {
4616 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4617 return MCDisassembler::Fail;
4618 } else
4619 Inst.addOperand(MCOperand::createReg(0));
4620 }
4621
4622 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4623 return MCDisassembler::Fail;
4624 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4625 return MCDisassembler::Fail;
4626 Inst.addOperand(MCOperand::createImm(index));
4627
4628 return S;
4629 }
4630
4631 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
4632 uint64_t Address, const void *Decoder) {
4633 DecodeStatus S = MCDisassembler::Success;
4634
4635 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4636 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4637 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4638 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4639 unsigned size = fieldFromInstruction(Insn, 10, 2);
4640
4641 unsigned align = 0;
4642 unsigned index = 0;
4643 unsigned inc = 1;
4644 switch (size) {
4645 default:
4646 return MCDisassembler::Fail;
4647 case 0:
4648 if (fieldFromInstruction(Insn, 4, 1))
4649 return MCDisassembler::Fail; // UNDEFINED
4650 index = fieldFromInstruction(Insn, 5, 3);
4651 break;
4652 case 1:
4653 if (fieldFromInstruction(Insn, 4, 1))
4654 return MCDisassembler::Fail; // UNDEFINED
4655 index = fieldFromInstruction(Insn, 6, 2);
4656 if (fieldFromInstruction(Insn, 5, 1))
4657 inc = 2;
4658 break;
4659 case 2:
4660 if (fieldFromInstruction(Insn, 4, 2))
4661 return MCDisassembler::Fail; // UNDEFINED
4662 index = fieldFromInstruction(Insn, 7, 1);
4663 if (fieldFromInstruction(Insn, 6, 1))
4664 inc = 2;
4665 break;
4666 }
4667
4668 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4669 return MCDisassembler::Fail;
4670 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4671 return MCDisassembler::Fail;
4672 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4673 return MCDisassembler::Fail;
4674
4675 if (Rm != 0xF) { // Writeback
4676 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4677 return MCDisassembler::Fail;
4678 }
4679 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4680 return MCDisassembler::Fail;
4681 Inst.addOperand(MCOperand::createImm(align));
4682 if (Rm != 0xF) {
4683 if (Rm != 0xD) {
4684 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4685 return MCDisassembler::Fail;
4686 } else
4687 Inst.addOperand(MCOperand::createReg(0));
4688 }
4689
4690 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4691 return MCDisassembler::Fail;
4692 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4693 return MCDisassembler::Fail;
4694 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4695 return MCDisassembler::Fail;
4696 Inst.addOperand(MCOperand::createImm(index));
4697
4698 return S;
4699 }
4700
4701 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
4702 uint64_t Address, const void *Decoder) {
4703 DecodeStatus S = MCDisassembler::Success;
4704
4705 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4706 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4707 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4708 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4709 unsigned size = fieldFromInstruction(Insn, 10, 2);
4710
4711 unsigned align = 0;
4712 unsigned index = 0;
4713 unsigned inc = 1;
4714 switch (size) {
4715 default:
4716 return MCDisassembler::Fail;
4717 case 0:
4718 if (fieldFromInstruction(Insn, 4, 1))
4719 return MCDisassembler::Fail; // UNDEFINED
4720 index = fieldFromInstruction(Insn, 5, 3);
4721 break;
4722 case 1:
4723 if (fieldFromInstruction(Insn, 4, 1))
4724 return MCDisassembler::Fail; // UNDEFINED
4725 index = fieldFromInstruction(Insn, 6, 2);
4726 if (fieldFromInstruction(Insn, 5, 1))
4727 inc = 2;
4728 break;
4729 case 2:
4730 if (fieldFromInstruction(Insn, 4, 2))
4731 return MCDisassembler::Fail; // UNDEFINED
4732 index = fieldFromInstruction(Insn, 7, 1);
4733 if (fieldFromInstruction(Insn, 6, 1))
4734 inc = 2;
4735 break;
4736 }
4737
4738 if (Rm != 0xF) { // Writeback
4739 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4740 return MCDisassembler::Fail;
4741 }
4742 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4743 return MCDisassembler::Fail;
4744 Inst.addOperand(MCOperand::createImm(align));
4745 if (Rm != 0xF) {
4746 if (Rm != 0xD) {
4747 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4748 return MCDisassembler::Fail;
4749 } else
4750 Inst.addOperand(MCOperand::createReg(0));
4751 }
4752
4753 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4754 return MCDisassembler::Fail;
4755 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4756 return MCDisassembler::Fail;
4757 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4758 return MCDisassembler::Fail;
4759 Inst.addOperand(MCOperand::createImm(index));
4760
4761 return S;
4762 }
4763
4764 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4765 uint64_t Address, const void *Decoder) {
4766 DecodeStatus S = MCDisassembler::Success;
4767
4768 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4769 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4770 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4771 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4772 unsigned size = fieldFromInstruction(Insn, 10, 2);
4773
4774 unsigned align = 0;
4775 unsigned index = 0;
4776 unsigned inc = 1;
4777 switch (size) {
4778 default:
4779 return MCDisassembler::Fail;
4780 case 0:
4781 if (fieldFromInstruction(Insn, 4, 1))
4782 align = 4;
4783 index = fieldFromInstruction(Insn, 5, 3);
4784 break;
4785 case 1:
4786 if (fieldFromInstruction(Insn, 4, 1))
4787 align = 8;
4788 index = fieldFromInstruction(Insn, 6, 2);
4789 if (fieldFromInstruction(Insn, 5, 1))
4790 inc = 2;
4791 break;
4792 case 2:
4793 switch (fieldFromInstruction(Insn, 4, 2)) {
4794 case 0:
4795 align = 0; break;
4796 case 3:
4797 return MCDisassembler::Fail;
4798 default:
4799 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4800 }
4801
4802 index = fieldFromInstruction(Insn, 7, 1);
4803 if (fieldFromInstruction(Insn, 6, 1))
4804 inc = 2;
4805 break;
4806 }
4807
4808 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4809 return MCDisassembler::Fail;
4810 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4811 return MCDisassembler::Fail;
4812 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4813 return MCDisassembler::Fail;
4814 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4815 return MCDisassembler::Fail;
4816
4817 if (Rm != 0xF) { // Writeback
4818 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4819 return MCDisassembler::Fail;
4820 }
4821 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4822 return MCDisassembler::Fail;
4823 Inst.addOperand(MCOperand::createImm(align));
4824 if (Rm != 0xF) {
4825 if (Rm != 0xD) {
4826 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4827 return MCDisassembler::Fail;
4828 } else
4829 Inst.addOperand(MCOperand::createReg(0));
4830 }
4831
4832 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4833 return MCDisassembler::Fail;
4834 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4835 return MCDisassembler::Fail;
4836 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4837 return MCDisassembler::Fail;
4838 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4839 return MCDisassembler::Fail;
4840 Inst.addOperand(MCOperand::createImm(index));
4841
4842 return S;
4843 }
4844
4845 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4846 uint64_t Address, const void *Decoder) {
4847 DecodeStatus S = MCDisassembler::Success;
4848
4849 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4850 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4851 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4852 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4853 unsigned size = fieldFromInstruction(Insn, 10, 2);
4854
4855 unsigned align = 0;
4856 unsigned index = 0;
4857 unsigned inc = 1;
4858 switch (size) {
4859 default:
4860 return MCDisassembler::Fail;
4861 case 0:
4862 if (fieldFromInstruction(Insn, 4, 1))
4863 align = 4;
4864 index = fieldFromInstruction(Insn, 5, 3);
4865 break;
4866 case 1:
4867 if (fieldFromInstruction(Insn, 4, 1))
4868 align = 8;
4869 index = fieldFromInstruction(Insn, 6, 2);
4870 if (fieldFromInstruction(Insn, 5, 1))
4871 inc = 2;
4872 break;
4873 case 2:
4874 switch (fieldFromInstruction(Insn, 4, 2)) {
4875 case 0:
4876 align = 0; break;
4877 case 3:
4878 return MCDisassembler::Fail;
4879 default:
4880 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4881 }
4882
4883 index = fieldFromInstruction(Insn, 7, 1);
4884 if (fieldFromInstruction(Insn, 6, 1))
4885 inc = 2;
4886 break;
4887 }
4888
4889 if (Rm != 0xF) { // Writeback
4890 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4891 return MCDisassembler::Fail;
4892 }
4893 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4894 return MCDisassembler::Fail;
4895 Inst.addOperand(MCOperand::createImm(align));
4896 if (Rm != 0xF) {
4897 if (Rm != 0xD) {
4898 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4899 return MCDisassembler::Fail;
4900 } else
4901 Inst.addOperand(MCOperand::createReg(0));
4902 }
4903
4904 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4905 return MCDisassembler::Fail;
4906 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4907 return MCDisassembler::Fail;
4908 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4909 return MCDisassembler::Fail;
4910 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4911 return MCDisassembler::Fail;
4912 Inst.addOperand(MCOperand::createImm(index));
4913
4914 return S;
4915 }
4916
4917 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4918 uint64_t Address, const void *Decoder) {
4919 DecodeStatus S = MCDisassembler::Success;
4920 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4921 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4922 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4923 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4924 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4925
4926 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4927 S = MCDisassembler::SoftFail;
4928
4929 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4930 return MCDisassembler::Fail;
4931 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4932 return MCDisassembler::Fail;
4933 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4934 return MCDisassembler::Fail;
4935 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4936 return MCDisassembler::Fail;
4937 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4938 return MCDisassembler::Fail;
4939
4940 return S;
4941 }
4942
4943 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4944 uint64_t Address, const void *Decoder) {
4945 DecodeStatus S = MCDisassembler::Success;
4946 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4947 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4948 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4949 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4950 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4951
4952 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4953 S = MCDisassembler::SoftFail;
4954
4955 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4956 return MCDisassembler::Fail;
4957 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4958 return MCDisassembler::Fail;
4959 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4960 return MCDisassembler::Fail;
4961 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4962 return MCDisassembler::Fail;
4963 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4964 return MCDisassembler::Fail;
4965
4966 return S;
4967 }
4968
4969 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4970 uint64_t Address, const void *Decoder) {
4971 DecodeStatus S = MCDisassembler::Success;
4972 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4973 unsigned mask = fieldFromInstruction(Insn, 0, 4);
4974
4975 if (pred == 0xF) {
4976 pred = 0xE;
4977 S = MCDisassembler::SoftFail;
4978 }
4979
4980 if (mask == 0x0)
4981 return MCDisassembler::Fail;
4982
4983 Inst.addOperand(MCOperand::createImm(pred));
4984 Inst.addOperand(MCOperand::createImm(mask));
4985 return S;
4986 }
4987
4988 static DecodeStatus
4989 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4990 uint64_t Address, const void *Decoder) {
4991 DecodeStatus S = MCDisassembler::Success;
4992
4993 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4994 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4995 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4996 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4997 unsigned W = fieldFromInstruction(Insn, 21, 1);
4998 unsigned U = fieldFromInstruction(Insn, 23, 1);
4999 unsigned P = fieldFromInstruction(Insn, 24, 1);
5000 bool writeback = (W == 1) | (P == 0);
5001
5002 addr |= (U << 8) | (Rn << 9);
5003
5004 if (writeback && (Rn == Rt || Rn == Rt2))
5005 Check(S, MCDisassembler::SoftFail);
5006 if (Rt == Rt2)
5007 Check(S, MCDisassembler::SoftFail);
5008
5009 // Rt
5010 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5011 return MCDisassembler::Fail;
5012 // Rt2
5013 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5014 return MCDisassembler::Fail;
5015 // Writeback operand
5016 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5017 return MCDisassembler::Fail;
5018 // addr
5019 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5020 return MCDisassembler::Fail;
5021
5022 return S;
5023 }
5024
5025 static DecodeStatus
5026 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
5027 uint64_t Address, const void *Decoder) {
5028 DecodeStatus S = MCDisassembler::Success;
5029
5030 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5031 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
5032 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5033 unsigned addr = fieldFromInstruction(Insn, 0, 8);
5034 unsigned W = fieldFromInstruction(Insn, 21, 1);
5035 unsigned U = fieldFromInstruction(Insn, 23, 1);
5036 unsigned P = fieldFromInstruction(Insn, 24, 1);
5037 bool writeback = (W == 1) | (P == 0);
5038
5039 addr |= (U << 8) | (Rn << 9);
5040
5041 if (writeback && (Rn == Rt || Rn == Rt2))
5042 Check(S, MCDisassembler::SoftFail);
5043
5044 // Writeback operand
5045 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5046 return MCDisassembler::Fail;
5047 // Rt
5048 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5049 return MCDisassembler::Fail;
5050 // Rt2
5051 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5052 return MCDisassembler::Fail;
5053 // addr
5054 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5055 return MCDisassembler::Fail;
5056
5057 return S;
5058 }
5059
5060 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
5061 uint64_t Address, const void *Decoder) {
5062 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
5063 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
5064 if (sign1 != sign2) return MCDisassembler::Fail;
5065
5066 unsigned Val = fieldFromInstruction(Insn, 0, 8);
5067 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
5068 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
5069 Val |= sign1 << 12;
5070 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val)));
5071
5072 return MCDisassembler::Success;
5073 }
5074
5075 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
5076 uint64_t Address,
5077 const void *Decoder) {
5078 DecodeStatus S = MCDisassembler::Success;
5079
5080 // Shift of "asr #32" is not allowed in Thumb2 mode.
5081 if (Val == 0x20) S = MCDisassembler::Fail;
5082 Inst.addOperand(MCOperand::createImm(Val));
5083 return S;
5084 }
5085
5086 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
5087 uint64_t Address, const void *Decoder) {
5088 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5089 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
5090 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5091 unsigned pred = fieldFromInstruction(Insn, 28, 4);
5092
5093 if (pred == 0xF)
5094 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
5095
5096 DecodeStatus S = MCDisassembler::Success;
5097
5098 if (Rt == Rn || Rn == Rt2)
5099 S = MCDisassembler::SoftFail;
5100
5101 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5102 return MCDisassembler::Fail;
5103 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5104 return MCDisassembler::Fail;
5105 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5106 return MCDisassembler::Fail;
5107 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5108 return MCDisassembler::Fail;
5109
5110 return S;
5111 }
5112
5113 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
5114 uint64_t Address, const void *Decoder) {
5115 const FeatureBitset &featureBits =
5116 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5117 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5118
5119 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5120 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5121 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5122 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5123 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5124 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5125 unsigned op = fieldFromInstruction(Insn, 5, 1);
5126
5127 DecodeStatus S = MCDisassembler::Success;
5128
5129 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5130 if (!(imm & 0x38)) {
5131 if (cmode == 0xF) {
5132 if (op == 1) return MCDisassembler::Fail;
5133 Inst.setOpcode(ARM::VMOVv2f32);
5134 }
5135 if (hasFullFP16) {
5136 if (cmode == 0xE) {
5137 if (op == 1) {
5138 Inst.setOpcode(ARM::VMOVv1i64);
5139 } else {
5140 Inst.setOpcode(ARM::VMOVv8i8);
5141 }
5142 }
5143 if (cmode == 0xD) {
5144 if (op == 1) {
5145 Inst.setOpcode(ARM::VMVNv2i32);
5146 } else {
5147 Inst.setOpcode(ARM::VMOVv2i32);
5148 }
5149 }
5150 if (cmode == 0xC) {
5151 if (op == 1) {
5152 Inst.setOpcode(ARM::VMVNv2i32);
5153 } else {
5154 Inst.setOpcode(ARM::VMOVv2i32);
5155 }
5156 }
5157 }
5158 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5159 }
5160
5161 if (!(imm & 0x20)) return MCDisassembler::Fail;
5162
5163 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
5164 return MCDisassembler::Fail;
5165 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5166 return MCDisassembler::Fail;
5167 Inst.addOperand(MCOperand::createImm(64 - imm));
5168
5169 return S;
5170 }
5171
5172 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
5173 uint64_t Address, const void *Decoder) {
5174 const FeatureBitset &featureBits =
5175 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5176 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5177
5178 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5179 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5180 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5181 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5182 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5183 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5184 unsigned op = fieldFromInstruction(Insn, 5, 1);
5185
5186 DecodeStatus S = MCDisassembler::Success;
5187
5188 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5189 if (!(imm & 0x38)) {
5190 if (cmode == 0xF) {
5191 if (op == 1) return MCDisassembler::Fail;
5192 Inst.setOpcode(ARM::VMOVv4f32);
5193 }
5194 if (hasFullFP16) {
5195 if (cmode == 0xE) {
5196 if (op == 1) {
5197 Inst.setOpcode(ARM::VMOVv2i64);
5198 } else {
5199 Inst.setOpcode(ARM::VMOVv16i8);
5200 }
5201 }
5202 if (cmode == 0xD) {
5203 if (op == 1) {
5204 Inst.setOpcode(ARM::VMVNv4i32);
5205 } else {
5206 Inst.setOpcode(ARM::VMOVv4i32);
5207 }
5208 }
5209 if (cmode == 0xC) {
5210 if (op == 1) {
5211 Inst.setOpcode(ARM::VMVNv4i32);
5212 } else {
5213 Inst.setOpcode(ARM::VMOVv4i32);
5214 }
5215 }
5216 }
5217 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5218 }
5219
5220 if (!(imm & 0x20)) return MCDisassembler::Fail;
5221
5222 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
5223 return MCDisassembler::Fail;
5224 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
5225 return MCDisassembler::Fail;
5226 Inst.addOperand(MCOperand::createImm(64 - imm));
5227
5228 return S;
5229 }
5230
5231 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
5232 unsigned Insn,
5233 uint64_t Address,
5234 const void *Decoder) {
5235 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5236 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5237 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0);
5238 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4);
5239 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5240 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5241 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0);
5242 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0);
5243
5244 DecodeStatus S = MCDisassembler::Success;
5245
5246 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass;
5247
5248 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
5249 return MCDisassembler::Fail;
5250 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
5251 return MCDisassembler::Fail;
5252 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder)))
5253 return MCDisassembler::Fail;
5254 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5255 return MCDisassembler::Fail;
5256 // The lane index does not have any bits in the encoding, because it can only
5257 // be 0.
5258 Inst.addOperand(MCOperand::createImm(0));
5259 Inst.addOperand(MCOperand::createImm(rotate));
5260
5261 return S;
5262 }
5263
5264 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
5265 uint64_t Address, const void *Decoder) {
5266 DecodeStatus S = MCDisassembler::Success;
5267
5268 unsigned Rn = fieldFromInstruction(Val, 16, 4);
5269 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5270 unsigned Rm = fieldFromInstruction(Val, 0, 4);
5271 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
5272 unsigned Cond = fieldFromInstruction(Val, 28, 4);
5273
5274 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
5275 S = MCDisassembler::SoftFail;
5276
5277 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5278 return MCDisassembler::Fail;
5279 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5280 return MCDisassembler::Fail;
5281 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
5282 return MCDisassembler::Fail;
5283 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
5284 return MCDisassembler::Fail;
5285 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
5286 return MCDisassembler::Fail;
5287
5288 return S;
5289 }
5290
5291 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
5292 uint64_t Address, const void *Decoder) {
5293 DecodeStatus S = MCDisassembler::Success;
5294
5295 unsigned CRm = fieldFromInstruction(Val, 0, 4);
5296 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
5297 unsigned cop = fieldFromInstruction(Val, 8, 4);
5298 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5299 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
5300
5301 if ((cop & ~0x1) == 0xa)
5302 return MCDisassembler::Fail;
5303
5304 if (Rt == Rt2)
5305 S = MCDisassembler::SoftFail;
5306
5307 // We have to check if the instruction is MRRC2
5308 // or MCRR2 when constructing the operands for
5309 // Inst. Reason is because MRRC2 stores to two
5310 // registers so it's tablegen desc has has two
5311 // outputs whereas MCRR doesn't store to any
5312 // registers so all of it's operands are listed
5313 // as inputs, therefore the operand order for
5314 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
5315 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
5316
5317 if (Inst.getOpcode() == ARM::MRRC2) {
5318 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5319 return MCDisassembler::Fail;
5320 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5321 return MCDisassembler::Fail;
5322 }
5323 Inst.addOperand(MCOperand::createImm(cop));
5324 Inst.addOperand(MCOperand::createImm(opc1));
5325 if (Inst.getOpcode() == ARM::MCRR2) {
5326 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5327 return MCDisassembler::Fail;
5328 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5329 return MCDisassembler::Fail;
5330 }
5331 Inst.addOperand(MCOperand::createImm(CRm));
5332
5333 return S;
5334 }
5335
5336 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
5337 uint64_t Address,
5338 const void *Decoder) {
5339 const FeatureBitset &featureBits =
5340 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5341 DecodeStatus S = MCDisassembler::Success;
5342
5343 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5344
5345 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
5346 if (Rt == 13 || Rt == 15)
5347 S = MCDisassembler::SoftFail;
5348 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
5349 } else
5350 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
5351
5352 if (featureBits[ARM::ModeThumb]) {
5353 Inst.addOperand(MCOperand::createImm(ARMCC::AL));
5354 Inst.addOperand(MCOperand::createReg(0));
5355 } else {
5356 unsigned pred = fieldFromInstruction(Val, 28, 4);
5357 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5358 return MCDisassembler::Fail;
5359 }
5360
5361 return S;
5362 }
The low level virtual machine