lib/Target/ARM/Utils/ARMBaseInfo.h

   1 //===-- ARMBaseInfo.h - Top level definitions for ARM ---*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains small standalone helper functions and enum definitions for
  10 // the ARM target useful for the compiler back-end and the MC libraries.
  11 // As such, it deliberately does not include references to LLVM core
  12 // code gen types, passes, etc..
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #ifndef LLVM_LIB_TARGET_ARM_UTILS_ARMBASEINFO_H
  17 #define LLVM_LIB_TARGET_ARM_UTILS_ARMBASEINFO_H
  18
  19 #include "llvm/ADT/StringSwitch.h"
  20 #include "llvm/Support/ErrorHandling.h"
  21 #include "llvm/MC/SubtargetFeature.h"
  22 #include "MCTargetDesc/ARMMCTargetDesc.h"
  23
  24 namespace llvm {
  25
  26 // Enums corresponding to ARM condition codes
  27 namespace ARMCC {
  28 // The CondCodes constants map directly to the 4-bit encoding of the
  29 // condition field for predicated instructions.
  30 enum CondCodes { // Meaning (integer)          Meaning (floating-point)
  31   EQ,            // Equal                      Equal
  32   NE,            // Not equal                  Not equal, or unordered
  33   HS,            // Carry set                  >, ==, or unordered
  34   LO,            // Carry clear                Less than
  35   MI,            // Minus, negative            Less than
  36   PL,            // Plus, positive or zero     >, ==, or unordered
  37   VS,            // Overflow                   Unordered
  38   VC,            // No overflow                Not unordered
  39   HI,            // Unsigned higher            Greater than, or unordered
  40   LS,            // Unsigned lower or same     Less than or equal
  41   GE,            // Greater than or equal      Greater than or equal
  42   LT,            // Less than                  Less than, or unordered
  43   GT,            // Greater than               Greater than
  44   LE,            // Less than or equal         <, ==, or unordered
  45   AL             // Always (unconditional)     Always (unconditional)
  46 };
  47
  48 inline static CondCodes getOppositeCondition(CondCodes CC) {
  49   switch (CC) {
  50   default: llvm_unreachable("Unknown condition code");
  51   case EQ: return NE;
  52   case NE: return EQ;
  53   case HS: return LO;
  54   case LO: return HS;
  55   case MI: return PL;
  56   case PL: return MI;
  57   case VS: return VC;
  58   case VC: return VS;
  59   case HI: return LS;
  60   case LS: return HI;
  61   case GE: return LT;
  62   case LT: return GE;
  63   case GT: return LE;
  64   case LE: return GT;
  65   }
  66 }
  67 } // end namespace ARMCC
  68
  69 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
  70   switch (CC) {
  71   case ARMCC::EQ:  return "eq";
  72   case ARMCC::NE:  return "ne";
  73   case ARMCC::HS:  return "hs";
  74   case ARMCC::LO:  return "lo";
  75   case ARMCC::MI:  return "mi";
  76   case ARMCC::PL:  return "pl";
  77   case ARMCC::VS:  return "vs";
  78   case ARMCC::VC:  return "vc";
  79   case ARMCC::HI:  return "hi";
  80   case ARMCC::LS:  return "ls";
  81   case ARMCC::GE:  return "ge";
  82   case ARMCC::LT:  return "lt";
  83   case ARMCC::GT:  return "gt";
  84   case ARMCC::LE:  return "le";
  85   case ARMCC::AL:  return "al";
  86   }
  87   llvm_unreachable("Unknown condition code");
  88 }
  89
  90 inline static unsigned ARMCondCodeFromString(StringRef CC) {
  91   return StringSwitch<unsigned>(CC.lower())
  92     .Case("eq", ARMCC::EQ)
  93     .Case("ne", ARMCC::NE)
  94     .Case("hs", ARMCC::HS)
  95     .Case("cs", ARMCC::HS)
  96     .Case("lo", ARMCC::LO)
  97     .Case("cc", ARMCC::LO)
  98     .Case("mi", ARMCC::MI)
  99     .Case("pl", ARMCC::PL)
 100     .Case("vs", ARMCC::VS)
 101     .Case("vc", ARMCC::VC)
 102     .Case("hi", ARMCC::HI)
 103     .Case("ls", ARMCC::LS)
 104     .Case("ge", ARMCC::GE)
 105     .Case("lt", ARMCC::LT)
 106     .Case("gt", ARMCC::GT)
 107     .Case("le", ARMCC::LE)
 108     .Case("al", ARMCC::AL)
 109     .Default(~0U);
 110 }
 111
 112 // System Registers
 113 namespace ARMSysReg {
 114   struct MClassSysReg {
 115     const char *Name;
 116     uint16_t M1Encoding12;
 117     uint16_t M2M3Encoding8;
 118     uint16_t Encoding;
 119     FeatureBitset FeaturesRequired;
 120
 121     // return true if FeaturesRequired are all present in ActiveFeatures
 122     bool hasRequiredFeatures(FeatureBitset ActiveFeatures) const {
 123       return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
 124     }
 125
 126     // returns true if TestFeatures are all present in FeaturesRequired
 127     bool isInRequiredFeatures(FeatureBitset TestFeatures) const {
 128       return (FeaturesRequired & TestFeatures) == TestFeatures;
 129     }
 130   };
 131
 132   #define GET_MCLASSSYSREG_DECL
 133   #include "ARMGenSystemRegister.inc"
 134
 135   // lookup system register using 12-bit SYSm value.
 136   // Note: the search is uniqued using M1 mask
 137   const MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm);
 138
 139   // returns APSR with _<bits> qualifier.
 140   // Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
 141   const MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm);
 142
 143   // lookup system registers using 8-bit SYSm value
 144   const MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm);
 145
 146 } // end namespace ARMSysReg
 147
 148 // Banked Registers
 149 namespace ARMBankedReg {
 150   struct BankedReg {
 151     const char *Name;
 152     uint16_t Encoding;
 153   };
 154   #define GET_BANKEDREG_DECL
 155   #include "ARMGenSystemRegister.inc"
 156 } // end namespace ARMBankedReg
 157
 158 } // end namespace llvm
 159
 160 #endif // LLVM_LIB_TARGET_ARM_UTILS_ARMBASEINFO_H