lib/Target/Hexagon/HexagonAsmPrinter.cpp

   1 //===- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly ---===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains a printer that converts from our internal representation
  10 // of machine-dependent LLVM code to Hexagon assembly language. This printer is
  11 // the output mechanism used by `llc'.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "HexagonAsmPrinter.h"
  16 #include "Hexagon.h"
  17 #include "HexagonInstrInfo.h"
  18 #include "HexagonRegisterInfo.h"
  19 #include "HexagonSubtarget.h"
  20 #include "MCTargetDesc/HexagonInstPrinter.h"
  21 #include "MCTargetDesc/HexagonMCExpr.h"
  22 #include "MCTargetDesc/HexagonMCInstrInfo.h"
  23 #include "MCTargetDesc/HexagonMCTargetDesc.h"
  24 #include "llvm/ADT/StringExtras.h"
  25 #include "llvm/ADT/StringRef.h"
  26 #include "llvm/ADT/Twine.h"
  27 #include "llvm/BinaryFormat/ELF.h"
  28 #include "llvm/CodeGen/AsmPrinter.h"
  29 #include "llvm/CodeGen/MachineBasicBlock.h"
  30 #include "llvm/CodeGen/MachineFunction.h"
  31 #include "llvm/CodeGen/MachineInstr.h"
  32 #include "llvm/CodeGen/MachineOperand.h"
  33 #include "llvm/CodeGen/TargetRegisterInfo.h"
  34 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  35 #include "llvm/MC/MCContext.h"
  36 #include "llvm/MC/MCDirectives.h"
  37 #include "llvm/MC/MCExpr.h"
  38 #include "llvm/MC/MCInst.h"
  39 #include "llvm/MC/MCRegisterInfo.h"
  40 #include "llvm/MC/MCSectionELF.h"
  41 #include "llvm/MC/MCStreamer.h"
  42 #include "llvm/MC/MCSymbol.h"
  43 #include "llvm/Support/Casting.h"
  44 #include "llvm/Support/CommandLine.h"
  45 #include "llvm/Support/ErrorHandling.h"
  46 #include "llvm/Support/TargetRegistry.h"
  47 #include "llvm/Support/raw_ostream.h"
  48 #include <algorithm>
  49 #include <cassert>
  50 #include <cstdint>
  51 #include <string>
  52
  53 using namespace llvm;
  54
  55 namespace llvm {
  56
  57 void HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI,
  58                       MCInst &MCB, HexagonAsmPrinter &AP);
  59
  60 } // end namespace llvm
  61
  62 #define DEBUG_TYPE "asm-printer"
  63
  64 // Given a scalar register return its pair.
  65 inline static unsigned getHexagonRegisterPair(unsigned Reg,
  66       const MCRegisterInfo *RI) {
  67   assert(Hexagon::IntRegsRegClass.contains(Reg));
  68   MCSuperRegIterator SR(Reg, RI, false);
  69   unsigned Pair = *SR;
  70   assert(Hexagon::DoubleRegsRegClass.contains(Pair));
  71   return Pair;
  72 }
  73
  74 void HexagonAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
  75                                      raw_ostream &O) {
  76   const MachineOperand &MO = MI->getOperand(OpNo);
  77
  78   switch (MO.getType()) {
  79   default:
  80     llvm_unreachable ("<unknown operand type>");
  81   case MachineOperand::MO_Register:
  82     O << HexagonInstPrinter::getRegisterName(MO.getReg());
  83     return;
  84   case MachineOperand::MO_Immediate:
  85     O << MO.getImm();
  86     return;
  87   case MachineOperand::MO_MachineBasicBlock:
  88     MO.getMBB()->getSymbol()->print(O, MAI);
  89     return;
  90   case MachineOperand::MO_ConstantPoolIndex:
  91     GetCPISymbol(MO.getIndex())->print(O, MAI);
  92     return;
  93   case MachineOperand::MO_GlobalAddress:
  94     // Computing the address of a global symbol, not calling it.
  95     getSymbol(MO.getGlobal())->print(O, MAI);
  96     printOffset(MO.getOffset(), O);
  97     return;
  98   }
  99 }
 100
 101 // isBlockOnlyReachableByFallthrough - We need to override this since the
 102 // default AsmPrinter does not print labels for any basic block that
 103 // is only reachable by a fall through. That works for all cases except
 104 // for the case in which the basic block is reachable by a fall through but
 105 // through an indirect from a jump table. In this case, the jump table
 106 // will contain a label not defined by AsmPrinter.
 107 bool HexagonAsmPrinter::isBlockOnlyReachableByFallthrough(
 108       const MachineBasicBlock *MBB) const {
 109   if (MBB->hasAddressTaken())
 110     return false;
 111   return AsmPrinter::isBlockOnlyReachableByFallthrough(MBB);
 112 }
 113
 114 /// PrintAsmOperand - Print out an operand for an inline asm expression.
 115 bool HexagonAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
 116                                         unsigned AsmVariant,
 117                                         const char *ExtraCode,
 118                                         raw_ostream &OS) {
 119   // Does this asm operand have a single letter operand modifier?
 120   if (ExtraCode && ExtraCode[0]) {
 121     if (ExtraCode[1] != 0)
 122       return true; // Unknown modifier.
 123
 124     switch (ExtraCode[0]) {
 125     default:
 126       // See if this is a generic print operand
 127       return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, OS);
 128     case 'c': // Don't print "$" before a global var name or constant.
 129       // Hexagon never has a prefix.
 130       printOperand(MI, OpNo, OS);
 131       return false;
 132     case 'L':
 133     case 'H': { // The highest-numbered register of a pair.
 134       const MachineOperand &MO = MI->getOperand(OpNo);
 135       const MachineFunction &MF = *MI->getParent()->getParent();
 136       const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
 137       if (!MO.isReg())
 138         return true;
 139       unsigned RegNumber = MO.getReg();
 140       // This should be an assert in the frontend.
 141       if (Hexagon::DoubleRegsRegClass.contains(RegNumber))
 142         RegNumber = TRI->getSubReg(RegNumber, ExtraCode[0] == 'L' ?
 143                                               Hexagon::isub_lo :
 144                                               Hexagon::isub_hi);
 145       OS << HexagonInstPrinter::getRegisterName(RegNumber);
 146       return false;
 147     }
 148     case 'I':
 149       // Write 'i' if an integer constant, otherwise nothing.  Used to print
 150       // addi vs add, etc.
 151       if (MI->getOperand(OpNo).isImm())
 152         OS << "i";
 153       return false;
 154     }
 155   }
 156
 157   printOperand(MI, OpNo, OS);
 158   return false;
 159 }
 160
 161 bool HexagonAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
 162                                               unsigned OpNo,
 163                                               unsigned AsmVariant,
 164                                               const char *ExtraCode,
 165                                               raw_ostream &O) {
 166   if (ExtraCode && ExtraCode[0])
 167     return true; // Unknown modifier.
 168
 169   const MachineOperand &Base  = MI->getOperand(OpNo);
 170   const MachineOperand &Offset = MI->getOperand(OpNo+1);
 171
 172   if (Base.isReg())
 173     printOperand(MI, OpNo, O);
 174   else
 175     llvm_unreachable("Unimplemented");
 176
 177   if (Offset.isImm()) {
 178     if (Offset.getImm())
 179       O << "+#" << Offset.getImm();
 180   } else {
 181     llvm_unreachable("Unimplemented");
 182   }
 183
 184   return false;
 185 }
 186
 187 static MCSymbol *smallData(AsmPrinter &AP, const MachineInstr &MI,
 188                            MCStreamer &OutStreamer, const MCOperand &Imm,
 189                            int AlignSize) {
 190   MCSymbol *Sym;
 191   int64_t Value;
 192   if (Imm.getExpr()->evaluateAsAbsolute(Value)) {
 193     StringRef sectionPrefix;
 194     std::string ImmString;
 195     StringRef Name;
 196     if (AlignSize == 8) {
 197        Name = ".CONST_0000000000000000";
 198        sectionPrefix = ".gnu.linkonce.l8";
 199        ImmString = utohexstr(Value);
 200     } else {
 201        Name = ".CONST_00000000";
 202        sectionPrefix = ".gnu.linkonce.l4";
 203        ImmString = utohexstr(static_cast<uint32_t>(Value));
 204     }
 205
 206     std::string symbolName =   // Yes, leading zeros are kept.
 207       Name.drop_back(ImmString.size()).str() + ImmString;
 208     std::string sectionName = sectionPrefix.str() + symbolName;
 209
 210     MCSectionELF *Section = OutStreamer.getContext().getELFSection(
 211         sectionName, ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC);
 212     OutStreamer.SwitchSection(Section);
 213
 214     Sym = AP.OutContext.getOrCreateSymbol(Twine(symbolName));
 215     if (Sym->isUndefined()) {
 216       OutStreamer.EmitLabel(Sym);
 217       OutStreamer.EmitSymbolAttribute(Sym, MCSA_Global);
 218       OutStreamer.EmitIntValue(Value, AlignSize);
 219       OutStreamer.EmitCodeAlignment(AlignSize);
 220     }
 221   } else {
 222     assert(Imm.isExpr() && "Expected expression and found none");
 223     const MachineOperand &MO = MI.getOperand(1);
 224     assert(MO.isGlobal() || MO.isCPI() || MO.isJTI());
 225     MCSymbol *MOSymbol = nullptr;
 226     if (MO.isGlobal())
 227       MOSymbol = AP.getSymbol(MO.getGlobal());
 228     else if (MO.isCPI())
 229       MOSymbol = AP.GetCPISymbol(MO.getIndex());
 230     else if (MO.isJTI())
 231       MOSymbol = AP.GetJTISymbol(MO.getIndex());
 232     else
 233       llvm_unreachable("Unknown operand type!");
 234
 235     StringRef SymbolName = MOSymbol->getName();
 236     std::string LitaName = ".CONST_" + SymbolName.str();
 237
 238     MCSectionELF *Section = OutStreamer.getContext().getELFSection(
 239         ".lita", ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC);
 240
 241     OutStreamer.SwitchSection(Section);
 242     Sym = AP.OutContext.getOrCreateSymbol(Twine(LitaName));
 243     if (Sym->isUndefined()) {
 244       OutStreamer.EmitLabel(Sym);
 245       OutStreamer.EmitSymbolAttribute(Sym, MCSA_Local);
 246       OutStreamer.EmitValue(Imm.getExpr(), AlignSize);
 247       OutStreamer.EmitCodeAlignment(AlignSize);
 248     }
 249   }
 250   return Sym;
 251 }
 252
 253 static MCInst ScaleVectorOffset(MCInst &Inst, unsigned OpNo,
 254                                 unsigned VectorSize, MCContext &Ctx) {
 255   MCInst T;
 256   T.setOpcode(Inst.getOpcode());
 257   for (unsigned i = 0, n = Inst.getNumOperands(); i != n; ++i) {
 258     if (i != OpNo) {
 259       T.addOperand(Inst.getOperand(i));
 260       continue;
 261     }
 262     MCOperand &ImmOp = Inst.getOperand(i);
 263     const auto *HE = static_cast<const HexagonMCExpr*>(ImmOp.getExpr());
 264     int32_t V = cast<MCConstantExpr>(HE->getExpr())->getValue();
 265     auto *NewCE = MCConstantExpr::create(V / int32_t(VectorSize), Ctx);
 266     auto *NewHE = HexagonMCExpr::create(NewCE, Ctx);
 267     T.addOperand(MCOperand::createExpr(NewHE));
 268   }
 269   return T;
 270 }
 271
 272 void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
 273                                                   const MachineInstr &MI) {
 274   MCInst &MappedInst = static_cast <MCInst &>(Inst);
 275   const MCRegisterInfo *RI = OutStreamer->getContext().getRegisterInfo();
 276   const MachineFunction &MF = *MI.getParent()->getParent();
 277   auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
 278   unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8;
 279
 280   switch (Inst.getOpcode()) {
 281   default:
 282     return;
 283
 284   case Hexagon::A2_iconst: {
 285     Inst.setOpcode(Hexagon::A2_addi);
 286     MCOperand Reg = Inst.getOperand(0);
 287     MCOperand S16 = Inst.getOperand(1);
 288     HexagonMCInstrInfo::setMustNotExtend(*S16.getExpr());
 289     HexagonMCInstrInfo::setS27_2_reloc(*S16.getExpr());
 290     Inst.clear();
 291     Inst.addOperand(Reg);
 292     Inst.addOperand(MCOperand::createReg(Hexagon::R0));
 293     Inst.addOperand(S16);
 294     break;
 295   }
 296
 297   case Hexagon::A2_tfrf: {
 298     const MCConstantExpr *Zero = MCConstantExpr::create(0, OutContext);
 299     Inst.setOpcode(Hexagon::A2_paddif);
 300     Inst.addOperand(MCOperand::createExpr(Zero));
 301     break;
 302   }
 303
 304   case Hexagon::A2_tfrt: {
 305     const MCConstantExpr *Zero = MCConstantExpr::create(0, OutContext);
 306     Inst.setOpcode(Hexagon::A2_paddit);
 307     Inst.addOperand(MCOperand::createExpr(Zero));
 308     break;
 309   }
 310
 311   case Hexagon::A2_tfrfnew: {
 312     const MCConstantExpr *Zero = MCConstantExpr::create(0, OutContext);
 313     Inst.setOpcode(Hexagon::A2_paddifnew);
 314     Inst.addOperand(MCOperand::createExpr(Zero));
 315     break;
 316   }
 317
 318   case Hexagon::A2_tfrtnew: {
 319     const MCConstantExpr *Zero = MCConstantExpr::create(0, OutContext);
 320     Inst.setOpcode(Hexagon::A2_padditnew);
 321     Inst.addOperand(MCOperand::createExpr(Zero));
 322     break;
 323   }
 324
 325   case Hexagon::A2_zxtb: {
 326     const MCConstantExpr *C255 = MCConstantExpr::create(255, OutContext);
 327     Inst.setOpcode(Hexagon::A2_andir);
 328     Inst.addOperand(MCOperand::createExpr(C255));
 329     break;
 330   }
 331
 332   // "$dst = CONST64(#$src1)",
 333   case Hexagon::CONST64:
 334     if (!OutStreamer->hasRawTextSupport()) {
 335       const MCOperand &Imm = MappedInst.getOperand(1);
 336       MCSectionSubPair Current = OutStreamer->getCurrentSection();
 337
 338       MCSymbol *Sym = smallData(*this, MI, *OutStreamer, Imm, 8);
 339
 340       OutStreamer->SwitchSection(Current.first, Current.second);
 341       MCInst TmpInst;
 342       MCOperand &Reg = MappedInst.getOperand(0);
 343       TmpInst.setOpcode(Hexagon::L2_loadrdgp);
 344       TmpInst.addOperand(Reg);
 345       TmpInst.addOperand(MCOperand::createExpr(
 346                          MCSymbolRefExpr::create(Sym, OutContext)));
 347       MappedInst = TmpInst;
 348
 349     }
 350     break;
 351   case Hexagon::CONST32:
 352     if (!OutStreamer->hasRawTextSupport()) {
 353       MCOperand &Imm = MappedInst.getOperand(1);
 354       MCSectionSubPair Current = OutStreamer->getCurrentSection();
 355       MCSymbol *Sym = smallData(*this, MI, *OutStreamer, Imm, 4);
 356       OutStreamer->SwitchSection(Current.first, Current.second);
 357       MCInst TmpInst;
 358       MCOperand &Reg = MappedInst.getOperand(0);
 359       TmpInst.setOpcode(Hexagon::L2_loadrigp);
 360       TmpInst.addOperand(Reg);
 361       TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(
 362           MCSymbolRefExpr::create(Sym, OutContext), OutContext)));
 363       MappedInst = TmpInst;
 364     }
 365     break;
 366
 367   // C2_pxfer_map maps to C2_or instruction. Though, it's possible to use
 368   // C2_or during instruction selection itself but it results
 369   // into suboptimal code.
 370   case Hexagon::C2_pxfer_map: {
 371     MCOperand &Ps = Inst.getOperand(1);
 372     MappedInst.setOpcode(Hexagon::C2_or);
 373     MappedInst.addOperand(Ps);
 374     return;
 375   }
 376
 377   // Vector reduce complex multiply by scalar, Rt & 1 map to :hi else :lo
 378   // The insn is mapped from the 4 operand to the 3 operand raw form taking
 379   // 3 register pairs.
 380   case Hexagon::M2_vrcmpys_acc_s1: {
 381     MCOperand &Rt = Inst.getOperand(3);
 382     assert(Rt.isReg() && "Expected register and none was found");
 383     unsigned Reg = RI->getEncodingValue(Rt.getReg());
 384     if (Reg & 1)
 385       MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h);
 386     else
 387       MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l);
 388     Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
 389     return;
 390   }
 391   case Hexagon::M2_vrcmpys_s1: {
 392     MCOperand &Rt = Inst.getOperand(2);
 393     assert(Rt.isReg() && "Expected register and none was found");
 394     unsigned Reg = RI->getEncodingValue(Rt.getReg());
 395     if (Reg & 1)
 396       MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_h);
 397     else
 398       MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_l);
 399     Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
 400     return;
 401   }
 402
 403   case Hexagon::M2_vrcmpys_s1rp: {
 404     MCOperand &Rt = Inst.getOperand(2);
 405     assert(Rt.isReg() && "Expected register and none was found");
 406     unsigned Reg = RI->getEncodingValue(Rt.getReg());
 407     if (Reg & 1)
 408       MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h);
 409     else
 410       MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l);
 411     Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
 412     return;
 413   }
 414
 415   case Hexagon::A4_boundscheck: {
 416     MCOperand &Rs = Inst.getOperand(1);
 417     assert(Rs.isReg() && "Expected register and none was found");
 418     unsigned Reg = RI->getEncodingValue(Rs.getReg());
 419     if (Reg & 1) // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2
 420       MappedInst.setOpcode(Hexagon::A4_boundscheck_hi);
 421     else         // raw:lo
 422       MappedInst.setOpcode(Hexagon::A4_boundscheck_lo);
 423     Rs.setReg(getHexagonRegisterPair(Rs.getReg(), RI));
 424     return;
 425   }
 426
 427   case Hexagon::PS_call_nr:
 428     Inst.setOpcode(Hexagon::J2_call);
 429     break;
 430
 431   case Hexagon::S5_asrhub_rnd_sat_goodsyntax: {
 432     MCOperand &MO = MappedInst.getOperand(2);
 433     int64_t Imm;
 434     MCExpr const *Expr = MO.getExpr();
 435     bool Success = Expr->evaluateAsAbsolute(Imm);
 436     assert(Success && "Expected immediate and none was found");
 437     (void)Success;
 438     MCInst TmpInst;
 439     if (Imm == 0) {
 440       TmpInst.setOpcode(Hexagon::S2_vsathub);
 441       TmpInst.addOperand(MappedInst.getOperand(0));
 442       TmpInst.addOperand(MappedInst.getOperand(1));
 443       MappedInst = TmpInst;
 444       return;
 445     }
 446     TmpInst.setOpcode(Hexagon::S5_asrhub_rnd_sat);
 447     TmpInst.addOperand(MappedInst.getOperand(0));
 448     TmpInst.addOperand(MappedInst.getOperand(1));
 449     const MCExpr *One = MCConstantExpr::create(1, OutContext);
 450     const MCExpr *Sub = MCBinaryExpr::createSub(Expr, One, OutContext);
 451     TmpInst.addOperand(
 452         MCOperand::createExpr(HexagonMCExpr::create(Sub, OutContext)));
 453     MappedInst = TmpInst;
 454     return;
 455   }
 456
 457   case Hexagon::S5_vasrhrnd_goodsyntax:
 458   case Hexagon::S2_asr_i_p_rnd_goodsyntax: {
 459     MCOperand &MO2 = MappedInst.getOperand(2);
 460     MCExpr const *Expr = MO2.getExpr();
 461     int64_t Imm;
 462     bool Success = Expr->evaluateAsAbsolute(Imm);
 463     assert(Success && "Expected immediate and none was found");
 464     (void)Success;
 465     MCInst TmpInst;
 466     if (Imm == 0) {
 467       TmpInst.setOpcode(Hexagon::A2_combinew);
 468       TmpInst.addOperand(MappedInst.getOperand(0));
 469       MCOperand &MO1 = MappedInst.getOperand(1);
 470       unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi);
 471       unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo);
 472       // Add a new operand for the second register in the pair.
 473       TmpInst.addOperand(MCOperand::createReg(High));
 474       TmpInst.addOperand(MCOperand::createReg(Low));
 475       MappedInst = TmpInst;
 476       return;
 477     }
 478
 479     if (Inst.getOpcode() == Hexagon::S2_asr_i_p_rnd_goodsyntax)
 480       TmpInst.setOpcode(Hexagon::S2_asr_i_p_rnd);
 481     else
 482       TmpInst.setOpcode(Hexagon::S5_vasrhrnd);
 483     TmpInst.addOperand(MappedInst.getOperand(0));
 484     TmpInst.addOperand(MappedInst.getOperand(1));
 485     const MCExpr *One = MCConstantExpr::create(1, OutContext);
 486     const MCExpr *Sub = MCBinaryExpr::createSub(Expr, One, OutContext);
 487     TmpInst.addOperand(
 488         MCOperand::createExpr(HexagonMCExpr::create(Sub, OutContext)));
 489     MappedInst = TmpInst;
 490     return;
 491   }
 492
 493   // if ("#u5==0") Assembler mapped to: "Rd=Rs"; else Rd=asr(Rs,#u5-1):rnd
 494   case Hexagon::S2_asr_i_r_rnd_goodsyntax: {
 495     MCOperand &MO = Inst.getOperand(2);
 496     MCExpr const *Expr = MO.getExpr();
 497     int64_t Imm;
 498     bool Success = Expr->evaluateAsAbsolute(Imm);
 499     assert(Success && "Expected immediate and none was found");
 500     (void)Success;
 501     MCInst TmpInst;
 502     if (Imm == 0) {
 503       TmpInst.setOpcode(Hexagon::A2_tfr);
 504       TmpInst.addOperand(MappedInst.getOperand(0));
 505       TmpInst.addOperand(MappedInst.getOperand(1));
 506       MappedInst = TmpInst;
 507       return;
 508     }
 509     TmpInst.setOpcode(Hexagon::S2_asr_i_r_rnd);
 510     TmpInst.addOperand(MappedInst.getOperand(0));
 511     TmpInst.addOperand(MappedInst.getOperand(1));
 512     const MCExpr *One = MCConstantExpr::create(1, OutContext);
 513     const MCExpr *Sub = MCBinaryExpr::createSub(Expr, One, OutContext);
 514     TmpInst.addOperand(
 515         MCOperand::createExpr(HexagonMCExpr::create(Sub, OutContext)));
 516     MappedInst = TmpInst;
 517     return;
 518   }
 519
 520   // Translate a "$Rdd = #imm" to "$Rdd = combine(#[-1,0], #imm)"
 521   case Hexagon::A2_tfrpi: {
 522     MCInst TmpInst;
 523     MCOperand &Rdd = MappedInst.getOperand(0);
 524     MCOperand &MO = MappedInst.getOperand(1);
 525
 526     TmpInst.setOpcode(Hexagon::A2_combineii);
 527     TmpInst.addOperand(Rdd);
 528     int64_t Imm;
 529     bool Success = MO.getExpr()->evaluateAsAbsolute(Imm);
 530     if (Success && Imm < 0) {
 531       const MCExpr *MOne = MCConstantExpr::create(-1, OutContext);
 532       const HexagonMCExpr *E = HexagonMCExpr::create(MOne, OutContext);
 533       TmpInst.addOperand(MCOperand::createExpr(E));
 534     } else {
 535       const MCExpr *Zero = MCConstantExpr::create(0, OutContext);
 536       const HexagonMCExpr *E = HexagonMCExpr::create(Zero, OutContext);
 537       TmpInst.addOperand(MCOperand::createExpr(E));
 538     }
 539     TmpInst.addOperand(MO);
 540     MappedInst = TmpInst;
 541     return;
 542   }
 543
 544   // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
 545   case Hexagon::A2_tfrp: {
 546     MCOperand &MO = MappedInst.getOperand(1);
 547     unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
 548     unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
 549     MO.setReg(High);
 550     // Add a new operand for the second register in the pair.
 551     MappedInst.addOperand(MCOperand::createReg(Low));
 552     MappedInst.setOpcode(Hexagon::A2_combinew);
 553     return;
 554   }
 555
 556   case Hexagon::A2_tfrpt:
 557   case Hexagon::A2_tfrpf: {
 558     MCOperand &MO = MappedInst.getOperand(2);
 559     unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
 560     unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
 561     MO.setReg(High);
 562     // Add a new operand for the second register in the pair.
 563     MappedInst.addOperand(MCOperand::createReg(Low));
 564     MappedInst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt)
 565                           ? Hexagon::C2_ccombinewt
 566                           : Hexagon::C2_ccombinewf);
 567     return;
 568   }
 569
 570   case Hexagon::A2_tfrptnew:
 571   case Hexagon::A2_tfrpfnew: {
 572     MCOperand &MO = MappedInst.getOperand(2);
 573     unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
 574     unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
 575     MO.setReg(High);
 576     // Add a new operand for the second register in the pair.
 577     MappedInst.addOperand(MCOperand::createReg(Low));
 578     MappedInst.setOpcode(Inst.getOpcode() == Hexagon::A2_tfrptnew
 579                             ? Hexagon::C2_ccombinewnewt
 580                             : Hexagon::C2_ccombinewnewf);
 581     return;
 582   }
 583
 584   case Hexagon::M2_mpysmi: {
 585     MCOperand &Imm = MappedInst.getOperand(2);
 586     MCExpr const *Expr = Imm.getExpr();
 587     int64_t Value;
 588     bool Success = Expr->evaluateAsAbsolute(Value);
 589     assert(Success);
 590     (void)Success;
 591     if (Value < 0 && Value > -256) {
 592       MappedInst.setOpcode(Hexagon::M2_mpysin);
 593       Imm.setExpr(HexagonMCExpr::create(
 594           MCUnaryExpr::createMinus(Expr, OutContext), OutContext));
 595     } else
 596       MappedInst.setOpcode(Hexagon::M2_mpysip);
 597     return;
 598   }
 599
 600   case Hexagon::A2_addsp: {
 601     MCOperand &Rt = Inst.getOperand(1);
 602     assert(Rt.isReg() && "Expected register and none was found");
 603     unsigned Reg = RI->getEncodingValue(Rt.getReg());
 604     if (Reg & 1)
 605       MappedInst.setOpcode(Hexagon::A2_addsph);
 606     else
 607       MappedInst.setOpcode(Hexagon::A2_addspl);
 608     Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
 609     return;
 610   }
 611
 612   case Hexagon::V6_vd0: {
 613     MCInst TmpInst;
 614     assert(Inst.getOperand(0).isReg() &&
 615            "Expected register and none was found");
 616
 617     TmpInst.setOpcode(Hexagon::V6_vxor);
 618     TmpInst.addOperand(Inst.getOperand(0));
 619     TmpInst.addOperand(Inst.getOperand(0));
 620     TmpInst.addOperand(Inst.getOperand(0));
 621     MappedInst = TmpInst;
 622     return;
 623   }
 624
 625   case Hexagon::V6_vdd0: {
 626     MCInst TmpInst;
 627     assert (Inst.getOperand(0).isReg() &&
 628             "Expected register and none was found");
 629
 630     TmpInst.setOpcode(Hexagon::V6_vsubw_dv);
 631     TmpInst.addOperand(Inst.getOperand(0));
 632     TmpInst.addOperand(Inst.getOperand(0));
 633     TmpInst.addOperand(Inst.getOperand(0));
 634     MappedInst = TmpInst;
 635     return;
 636   }
 637
 638   case Hexagon::V6_vL32Ub_pi:
 639   case Hexagon::V6_vL32b_cur_pi:
 640   case Hexagon::V6_vL32b_nt_cur_pi:
 641   case Hexagon::V6_vL32b_pi:
 642   case Hexagon::V6_vL32b_nt_pi:
 643   case Hexagon::V6_vL32b_nt_tmp_pi:
 644   case Hexagon::V6_vL32b_tmp_pi:
 645     MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
 646     return;
 647
 648   case Hexagon::V6_vL32Ub_ai:
 649   case Hexagon::V6_vL32b_ai:
 650   case Hexagon::V6_vL32b_cur_ai:
 651   case Hexagon::V6_vL32b_nt_ai:
 652   case Hexagon::V6_vL32b_nt_cur_ai:
 653   case Hexagon::V6_vL32b_nt_tmp_ai:
 654   case Hexagon::V6_vL32b_tmp_ai:
 655     MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
 656     return;
 657
 658   case Hexagon::V6_vS32Ub_pi:
 659   case Hexagon::V6_vS32b_new_pi:
 660   case Hexagon::V6_vS32b_nt_new_pi:
 661   case Hexagon::V6_vS32b_nt_pi:
 662   case Hexagon::V6_vS32b_pi:
 663     MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
 664     return;
 665
 666   case Hexagon::V6_vS32Ub_ai:
 667   case Hexagon::V6_vS32b_ai:
 668   case Hexagon::V6_vS32b_new_ai:
 669   case Hexagon::V6_vS32b_nt_ai:
 670   case Hexagon::V6_vS32b_nt_new_ai:
 671     MappedInst = ScaleVectorOffset(Inst, 1, VectorSize, OutContext);
 672     return;
 673
 674   case Hexagon::V6_vL32b_cur_npred_pi:
 675   case Hexagon::V6_vL32b_cur_pred_pi:
 676   case Hexagon::V6_vL32b_npred_pi:
 677   case Hexagon::V6_vL32b_nt_cur_npred_pi:
 678   case Hexagon::V6_vL32b_nt_cur_pred_pi:
 679   case Hexagon::V6_vL32b_nt_npred_pi:
 680   case Hexagon::V6_vL32b_nt_pred_pi:
 681   case Hexagon::V6_vL32b_nt_tmp_npred_pi:
 682   case Hexagon::V6_vL32b_nt_tmp_pred_pi:
 683   case Hexagon::V6_vL32b_pred_pi:
 684   case Hexagon::V6_vL32b_tmp_npred_pi:
 685   case Hexagon::V6_vL32b_tmp_pred_pi:
 686     MappedInst = ScaleVectorOffset(Inst, 4, VectorSize, OutContext);
 687     return;
 688
 689   case Hexagon::V6_vL32b_cur_npred_ai:
 690   case Hexagon::V6_vL32b_cur_pred_ai:
 691   case Hexagon::V6_vL32b_npred_ai:
 692   case Hexagon::V6_vL32b_nt_cur_npred_ai:
 693   case Hexagon::V6_vL32b_nt_cur_pred_ai:
 694   case Hexagon::V6_vL32b_nt_npred_ai:
 695   case Hexagon::V6_vL32b_nt_pred_ai:
 696   case Hexagon::V6_vL32b_nt_tmp_npred_ai:
 697   case Hexagon::V6_vL32b_nt_tmp_pred_ai:
 698   case Hexagon::V6_vL32b_pred_ai:
 699   case Hexagon::V6_vL32b_tmp_npred_ai:
 700   case Hexagon::V6_vL32b_tmp_pred_ai:
 701     MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
 702     return;
 703
 704   case Hexagon::V6_vS32Ub_npred_pi:
 705   case Hexagon::V6_vS32Ub_pred_pi:
 706   case Hexagon::V6_vS32b_new_npred_pi:
 707   case Hexagon::V6_vS32b_new_pred_pi:
 708   case Hexagon::V6_vS32b_npred_pi:
 709   case Hexagon::V6_vS32b_nqpred_pi:
 710   case Hexagon::V6_vS32b_nt_new_npred_pi:
 711   case Hexagon::V6_vS32b_nt_new_pred_pi:
 712   case Hexagon::V6_vS32b_nt_npred_pi:
 713   case Hexagon::V6_vS32b_nt_nqpred_pi:
 714   case Hexagon::V6_vS32b_nt_pred_pi:
 715   case Hexagon::V6_vS32b_nt_qpred_pi:
 716   case Hexagon::V6_vS32b_pred_pi:
 717   case Hexagon::V6_vS32b_qpred_pi:
 718     MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
 719     return;
 720
 721   case Hexagon::V6_vS32Ub_npred_ai:
 722   case Hexagon::V6_vS32Ub_pred_ai:
 723   case Hexagon::V6_vS32b_new_npred_ai:
 724   case Hexagon::V6_vS32b_new_pred_ai:
 725   case Hexagon::V6_vS32b_npred_ai:
 726   case Hexagon::V6_vS32b_nqpred_ai:
 727   case Hexagon::V6_vS32b_nt_new_npred_ai:
 728   case Hexagon::V6_vS32b_nt_new_pred_ai:
 729   case Hexagon::V6_vS32b_nt_npred_ai:
 730   case Hexagon::V6_vS32b_nt_nqpred_ai:
 731   case Hexagon::V6_vS32b_nt_pred_ai:
 732   case Hexagon::V6_vS32b_nt_qpred_ai:
 733   case Hexagon::V6_vS32b_pred_ai:
 734   case Hexagon::V6_vS32b_qpred_ai:
 735     MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
 736     return;
 737
 738   // V65+
 739   case Hexagon::V6_vS32b_srls_ai:
 740     MappedInst = ScaleVectorOffset(Inst, 1, VectorSize, OutContext);
 741     return;
 742
 743   case Hexagon::V6_vS32b_srls_pi:
 744     MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
 745     return;
 746   }
 747 }
 748
 749 /// Print out a single Hexagon MI to the current output stream.
 750 void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) {
 751   MCInst MCB;
 752   MCB.setOpcode(Hexagon::BUNDLE);
 753   MCB.addOperand(MCOperand::createImm(0));
 754   const MCInstrInfo &MCII = *Subtarget->getInstrInfo();
 755
 756   if (MI->isBundle()) {
 757     const MachineBasicBlock* MBB = MI->getParent();
 758     MachineBasicBlock::const_instr_iterator MII = MI->getIterator();
 759
 760     for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
 761       if (!MII->isDebugInstr() && !MII->isImplicitDef())
 762         HexagonLowerToMC(MCII, &*MII, MCB, *this);
 763   } else {
 764     HexagonLowerToMC(MCII, MI, MCB, *this);
 765   }
 766
 767   const MachineFunction &MF = *MI->getParent()->getParent();
 768   const auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
 769   if (MI->isBundle() && HII.getBundleNoShuf(*MI))
 770     HexagonMCInstrInfo::setMemReorderDisabled(MCB);
 771
 772   MCContext &Ctx = OutStreamer->getContext();
 773   bool Ok = HexagonMCInstrInfo::canonicalizePacket(MCII, *Subtarget, Ctx,
 774                                                    MCB, nullptr);
 775   assert(Ok); (void)Ok;
 776   if (HexagonMCInstrInfo::bundleSize(MCB) == 0)
 777     return;
 778   OutStreamer->EmitInstruction(MCB, getSubtargetInfo());
 779 }
 780
 781 extern "C" void LLVMInitializeHexagonAsmPrinter() {
 782   RegisterAsmPrinter<HexagonAsmPrinter> X(getTheHexagonTarget());
 783 }