lib/Target/Hexagon/HexagonSubtarget.cpp

   1 //===- HexagonSubtarget.cpp - Hexagon Subtarget Information ---------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements the Hexagon specific subclass of TargetSubtarget.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "Hexagon.h"
  14 #include "HexagonInstrInfo.h"
  15 #include "HexagonRegisterInfo.h"
  16 #include "HexagonSubtarget.h"
  17 #include "MCTargetDesc/HexagonMCTargetDesc.h"
  18 #include "llvm/ADT/STLExtras.h"
  19 #include "llvm/ADT/SmallSet.h"
  20 #include "llvm/ADT/SmallVector.h"
  21 #include "llvm/ADT/StringRef.h"
  22 #include "llvm/CodeGen/MachineInstr.h"
  23 #include "llvm/CodeGen/MachineOperand.h"
  24 #include "llvm/CodeGen/MachineScheduler.h"
  25 #include "llvm/CodeGen/ScheduleDAG.h"
  26 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
  27 #include "llvm/Support/CommandLine.h"
  28 #include "llvm/Support/ErrorHandling.h"
  29 #include <algorithm>
  30 #include <cassert>
  31 #include <map>
  32
  33 using namespace llvm;
  34
  35 #define DEBUG_TYPE "hexagon-subtarget"
  36
  37 #define GET_SUBTARGETINFO_CTOR
  38 #define GET_SUBTARGETINFO_TARGET_DESC
  39 #include "HexagonGenSubtargetInfo.inc"
  40
  41
  42 static cl::opt<bool> EnableBSBSched("enable-bsb-sched",
  43   cl::Hidden, cl::ZeroOrMore, cl::init(true));
  44
  45 static cl::opt<bool> EnableTCLatencySched("enable-tc-latency-sched",
  46   cl::Hidden, cl::ZeroOrMore, cl::init(false));
  47
  48 static cl::opt<bool> EnableDotCurSched("enable-cur-sched",
  49   cl::Hidden, cl::ZeroOrMore, cl::init(true),
  50   cl::desc("Enable the scheduler to generate .cur"));
  51
  52 static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched",
  53   cl::Hidden, cl::ZeroOrMore, cl::init(false),
  54   cl::desc("Disable Hexagon MI Scheduling"));
  55
  56 static cl::opt<bool> EnableSubregLiveness("hexagon-subreg-liveness",
  57   cl::Hidden, cl::ZeroOrMore, cl::init(true),
  58   cl::desc("Enable subregister liveness tracking for Hexagon"));
  59
  60 static cl::opt<bool> OverrideLongCalls("hexagon-long-calls",
  61   cl::Hidden, cl::ZeroOrMore, cl::init(false),
  62   cl::desc("If present, forces/disables the use of long calls"));
  63
  64 static cl::opt<bool> EnablePredicatedCalls("hexagon-pred-calls",
  65   cl::Hidden, cl::ZeroOrMore, cl::init(false),
  66   cl::desc("Consider calls to be predicable"));
  67
  68 static cl::opt<bool> SchedPredsCloser("sched-preds-closer",
  69   cl::Hidden, cl::ZeroOrMore, cl::init(true));
  70
  71 static cl::opt<bool> SchedRetvalOptimization("sched-retval-optimization",
  72   cl::Hidden, cl::ZeroOrMore, cl::init(true));
  73
  74 static cl::opt<bool> EnableCheckBankConflict("hexagon-check-bank-conflict",
  75   cl::Hidden, cl::ZeroOrMore, cl::init(true),
  76   cl::desc("Enable checking for cache bank conflicts"));
  77
  78
  79 HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
  80                                    StringRef FS, const TargetMachine &TM)
  81     : HexagonGenSubtargetInfo(TT, CPU, FS), OptLevel(TM.getOptLevel()),
  82       CPUString(Hexagon_MC::selectHexagonCPU(CPU)),
  83       InstrInfo(initializeSubtargetDependencies(CPU, FS)),
  84       RegInfo(getHwMode()), TLInfo(TM, *this),
  85       InstrItins(getInstrItineraryForCPU(CPUString)) {
  86   // Beware of the default constructor of InstrItineraryData: it will
  87   // reset all members to 0.
  88   assert(InstrItins.Itineraries != nullptr && "InstrItins not initialized");
  89 }
  90
  91 HexagonSubtarget &
  92 HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
  93   static std::map<StringRef, Hexagon::ArchEnum> CpuTable{
  94       {"generic", Hexagon::ArchEnum::V60},
  95       {"hexagonv5", Hexagon::ArchEnum::V5},
  96       {"hexagonv55", Hexagon::ArchEnum::V55},
  97       {"hexagonv60", Hexagon::ArchEnum::V60},
  98       {"hexagonv62", Hexagon::ArchEnum::V62},
  99       {"hexagonv65", Hexagon::ArchEnum::V65},
 100       {"hexagonv66", Hexagon::ArchEnum::V66},
 101   };
 102
 103   auto FoundIt = CpuTable.find(CPUString);
 104   if (FoundIt != CpuTable.end())
 105     HexagonArchVersion = FoundIt->second;
 106   else
 107     llvm_unreachable("Unrecognized Hexagon processor version");
 108
 109   UseHVX128BOps = false;
 110   UseHVX64BOps = false;
 111   UseLongCalls = false;
 112
 113   UseBSBScheduling = hasV60Ops() && EnableBSBSched;
 114
 115   ParseSubtargetFeatures(CPUString, FS);
 116
 117   if (OverrideLongCalls.getPosition())
 118     UseLongCalls = OverrideLongCalls;
 119
 120   FeatureBitset Features = getFeatureBits();
 121   if (HexagonDisableDuplex)
 122     setFeatureBits(Features.set(Hexagon::FeatureDuplex, false));
 123   setFeatureBits(Hexagon_MC::completeHVXFeatures(Features));
 124
 125   return *this;
 126 }
 127
 128 void HexagonSubtarget::UsrOverflowMutation::apply(ScheduleDAGInstrs *DAG) {
 129   for (SUnit &SU : DAG->SUnits) {
 130     if (!SU.isInstr())
 131       continue;
 132     SmallVector<SDep, 4> Erase;
 133     for (auto &D : SU.Preds)
 134       if (D.getKind() == SDep::Output && D.getReg() == Hexagon::USR_OVF)
 135         Erase.push_back(D);
 136     for (auto &E : Erase)
 137       SU.removePred(E);
 138   }
 139 }
 140
 141 void HexagonSubtarget::HVXMemLatencyMutation::apply(ScheduleDAGInstrs *DAG) {
 142   for (SUnit &SU : DAG->SUnits) {
 143     // Update the latency of chain edges between v60 vector load or store
 144     // instructions to be 1. These instruction cannot be scheduled in the
 145     // same packet.
 146     MachineInstr &MI1 = *SU.getInstr();
 147     auto *QII = static_cast<const HexagonInstrInfo*>(DAG->TII);
 148     bool IsStoreMI1 = MI1.mayStore();
 149     bool IsLoadMI1 = MI1.mayLoad();
 150     if (!QII->isHVXVec(MI1) || !(IsStoreMI1 || IsLoadMI1))
 151       continue;
 152     for (SDep &SI : SU.Succs) {
 153       if (SI.getKind() != SDep::Order || SI.getLatency() != 0)
 154         continue;
 155       MachineInstr &MI2 = *SI.getSUnit()->getInstr();
 156       if (!QII->isHVXVec(MI2))
 157         continue;
 158       if ((IsStoreMI1 && MI2.mayStore()) || (IsLoadMI1 && MI2.mayLoad())) {
 159         SI.setLatency(1);
 160         SU.setHeightDirty();
 161         // Change the dependence in the opposite direction too.
 162         for (SDep &PI : SI.getSUnit()->Preds) {
 163           if (PI.getSUnit() != &SU || PI.getKind() != SDep::Order)
 164             continue;
 165           PI.setLatency(1);
 166           SI.getSUnit()->setDepthDirty();
 167         }
 168       }
 169     }
 170   }
 171 }
 172
 173 // Check if a call and subsequent A2_tfrpi instructions should maintain
 174 // scheduling affinity. We are looking for the TFRI to be consumed in
 175 // the next instruction. This should help reduce the instances of
 176 // double register pairs being allocated and scheduled before a call
 177 // when not used until after the call. This situation is exacerbated
 178 // by the fact that we allocate the pair from the callee saves list,
 179 // leading to excess spills and restores.
 180 bool HexagonSubtarget::CallMutation::shouldTFRICallBind(
 181       const HexagonInstrInfo &HII, const SUnit &Inst1,
 182       const SUnit &Inst2) const {
 183   if (Inst1.getInstr()->getOpcode() != Hexagon::A2_tfrpi)
 184     return false;
 185
 186   // TypeXTYPE are 64 bit operations.
 187   unsigned Type = HII.getType(*Inst2.getInstr());
 188   return Type == HexagonII::TypeS_2op || Type == HexagonII::TypeS_3op ||
 189          Type == HexagonII::TypeALU64 || Type == HexagonII::TypeM;
 190 }
 191
 192 void HexagonSubtarget::CallMutation::apply(ScheduleDAGInstrs *DAGInstrs) {
 193   ScheduleDAGMI *DAG = static_cast<ScheduleDAGMI*>(DAGInstrs);
 194   SUnit* LastSequentialCall = nullptr;
 195   // Map from virtual register to physical register from the copy.
 196   DenseMap<unsigned, unsigned> VRegHoldingReg;
 197   // Map from the physical register to the instruction that uses virtual
 198   // register. This is used to create the barrier edge.
 199   DenseMap<unsigned, SUnit *> LastVRegUse;
 200   auto &TRI = *DAG->MF.getSubtarget().getRegisterInfo();
 201   auto &HII = *DAG->MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
 202
 203   // Currently we only catch the situation when compare gets scheduled
 204   // before preceding call.
 205   for (unsigned su = 0, e = DAG->SUnits.size(); su != e; ++su) {
 206     // Remember the call.
 207     if (DAG->SUnits[su].getInstr()->isCall())
 208       LastSequentialCall = &DAG->SUnits[su];
 209     // Look for a compare that defines a predicate.
 210     else if (DAG->SUnits[su].getInstr()->isCompare() && LastSequentialCall)
 211       DAG->addEdge(&DAG->SUnits[su], SDep(LastSequentialCall, SDep::Barrier));
 212     // Look for call and tfri* instructions.
 213     else if (SchedPredsCloser && LastSequentialCall && su > 1 && su < e-1 &&
 214              shouldTFRICallBind(HII, DAG->SUnits[su], DAG->SUnits[su+1]))
 215       DAG->addEdge(&DAG->SUnits[su], SDep(&DAG->SUnits[su-1], SDep::Barrier));
 216     // Prevent redundant register copies due to reads and writes of physical
 217     // registers. The original motivation for this was the code generated
 218     // between two calls, which are caused both the return value and the
 219     // argument for the next call being in %r0.
 220     // Example:
 221     //   1: <call1>
 222     //   2: %vreg = COPY %r0
 223     //   3: <use of %vreg>
 224     //   4: %r0 = ...
 225     //   5: <call2>
 226     // The scheduler would often swap 3 and 4, so an additional register is
 227     // needed. This code inserts a Barrier dependence between 3 & 4 to prevent
 228     // this.
 229     // The code below checks for all the physical registers, not just R0/D0/V0.
 230     else if (SchedRetvalOptimization) {
 231       const MachineInstr *MI = DAG->SUnits[su].getInstr();
 232       if (MI->isCopy() &&
 233           TargetRegisterInfo::isPhysicalRegister(MI->getOperand(1).getReg())) {
 234         // %vregX = COPY %r0
 235         VRegHoldingReg[MI->getOperand(0).getReg()] = MI->getOperand(1).getReg();
 236         LastVRegUse.erase(MI->getOperand(1).getReg());
 237       } else {
 238         for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
 239           const MachineOperand &MO = MI->getOperand(i);
 240           if (!MO.isReg())
 241             continue;
 242           if (MO.isUse() && !MI->isCopy() &&
 243               VRegHoldingReg.count(MO.getReg())) {
 244             // <use of %vregX>
 245             LastVRegUse[VRegHoldingReg[MO.getReg()]] = &DAG->SUnits[su];
 246           } else if (MO.isDef() &&
 247                      TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
 248             for (MCRegAliasIterator AI(MO.getReg(), &TRI, true); AI.isValid();
 249                  ++AI) {
 250               if (LastVRegUse.count(*AI) &&
 251                   LastVRegUse[*AI] != &DAG->SUnits[su])
 252                 // %r0 = ...
 253                 DAG->addEdge(&DAG->SUnits[su], SDep(LastVRegUse[*AI], SDep::Barrier));
 254               LastVRegUse.erase(*AI);
 255             }
 256           }
 257         }
 258       }
 259     }
 260   }
 261 }
 262
 263 void HexagonSubtarget::BankConflictMutation::apply(ScheduleDAGInstrs *DAG) {
 264   if (!EnableCheckBankConflict)
 265     return;
 266
 267   const auto &HII = static_cast<const HexagonInstrInfo&>(*DAG->TII);
 268
 269   // Create artificial edges between loads that could likely cause a bank
 270   // conflict. Since such loads would normally not have any dependency
 271   // between them, we cannot rely on existing edges.
 272   for (unsigned i = 0, e = DAG->SUnits.size(); i != e; ++i) {
 273     SUnit &S0 = DAG->SUnits[i];
 274     MachineInstr &L0 = *S0.getInstr();
 275     if (!L0.mayLoad() || L0.mayStore() ||
 276         HII.getAddrMode(L0) != HexagonII::BaseImmOffset)
 277       continue;
 278     int64_t Offset0;
 279     unsigned Size0;
 280     MachineOperand *BaseOp0 = HII.getBaseAndOffset(L0, Offset0, Size0);
 281     // Is the access size is longer than the L1 cache line, skip the check.
 282     if (BaseOp0 == nullptr || !BaseOp0->isReg() || Size0 >= 32)
 283       continue;
 284     // Scan only up to 32 instructions ahead (to avoid n^2 complexity).
 285     for (unsigned j = i+1, m = std::min(i+32, e); j != m; ++j) {
 286       SUnit &S1 = DAG->SUnits[j];
 287       MachineInstr &L1 = *S1.getInstr();
 288       if (!L1.mayLoad() || L1.mayStore() ||
 289           HII.getAddrMode(L1) != HexagonII::BaseImmOffset)
 290         continue;
 291       int64_t Offset1;
 292       unsigned Size1;
 293       MachineOperand *BaseOp1 = HII.getBaseAndOffset(L1, Offset1, Size1);
 294       if (BaseOp1 == nullptr || !BaseOp1->isReg() || Size1 >= 32 ||
 295           BaseOp0->getReg() != BaseOp1->getReg())
 296         continue;
 297       // Check bits 3 and 4 of the offset: if they differ, a bank conflict
 298       // is unlikely.
 299       if (((Offset0 ^ Offset1) & 0x18) != 0)
 300         continue;
 301       // Bits 3 and 4 are the same, add an artificial edge and set extra
 302       // latency.
 303       SDep A(&S0, SDep::Artificial);
 304       A.setLatency(1);
 305       S1.addPred(A, true);
 306     }
 307   }
 308 }
 309
 310 /// Enable use of alias analysis during code generation (during MI
 311 /// scheduling, DAGCombine, etc.).
 312 bool HexagonSubtarget::useAA() const {
 313   if (OptLevel != CodeGenOpt::None)
 314     return true;
 315   return false;
 316 }
 317
 318 /// Perform target specific adjustments to the latency of a schedule
 319 /// dependency.
 320 void HexagonSubtarget::adjustSchedDependency(SUnit *Src, SUnit *Dst,
 321                                              SDep &Dep) const {
 322   MachineInstr *SrcInst = Src->getInstr();
 323   MachineInstr *DstInst = Dst->getInstr();
 324   if (!Src->isInstr() || !Dst->isInstr())
 325     return;
 326
 327   const HexagonInstrInfo *QII = getInstrInfo();
 328
 329   // Instructions with .new operands have zero latency.
 330   SmallSet<SUnit *, 4> ExclSrc;
 331   SmallSet<SUnit *, 4> ExclDst;
 332   if (QII->canExecuteInBundle(*SrcInst, *DstInst) &&
 333       isBestZeroLatency(Src, Dst, QII, ExclSrc, ExclDst)) {
 334     Dep.setLatency(0);
 335     return;
 336   }
 337
 338   if (!hasV60Ops())
 339     return;
 340
 341   // Set the latency for a copy to zero since we hope that is will get removed.
 342   if (DstInst->isCopy())
 343     Dep.setLatency(0);
 344
 345   // If it's a REG_SEQUENCE/COPY, use its destination instruction to determine
 346   // the correct latency.
 347   if ((DstInst->isRegSequence() || DstInst->isCopy()) && Dst->NumSuccs == 1) {
 348     unsigned DReg = DstInst->getOperand(0).getReg();
 349     MachineInstr *DDst = Dst->Succs[0].getSUnit()->getInstr();
 350     unsigned UseIdx = -1;
 351     for (unsigned OpNum = 0; OpNum < DDst->getNumOperands(); OpNum++) {
 352       const MachineOperand &MO = DDst->getOperand(OpNum);
 353       if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == DReg) {
 354         UseIdx = OpNum;
 355         break;
 356       }
 357     }
 358     int DLatency = (InstrInfo.getOperandLatency(&InstrItins, *SrcInst,
 359                                                 0, *DDst, UseIdx));
 360     DLatency = std::max(DLatency, 0);
 361     Dep.setLatency((unsigned)DLatency);
 362   }
 363
 364   // Try to schedule uses near definitions to generate .cur.
 365   ExclSrc.clear();
 366   ExclDst.clear();
 367   if (EnableDotCurSched && QII->isToBeScheduledASAP(*SrcInst, *DstInst) &&
 368       isBestZeroLatency(Src, Dst, QII, ExclSrc, ExclDst)) {
 369     Dep.setLatency(0);
 370     return;
 371   }
 372
 373   updateLatency(*SrcInst, *DstInst, Dep);
 374 }
 375
 376 void HexagonSubtarget::getPostRAMutations(
 377     std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
 378   Mutations.push_back(llvm::make_unique<UsrOverflowMutation>());
 379   Mutations.push_back(llvm::make_unique<HVXMemLatencyMutation>());
 380   Mutations.push_back(llvm::make_unique<BankConflictMutation>());
 381 }
 382
 383 void HexagonSubtarget::getSMSMutations(
 384     std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
 385   Mutations.push_back(llvm::make_unique<UsrOverflowMutation>());
 386   Mutations.push_back(llvm::make_unique<HVXMemLatencyMutation>());
 387 }
 388
 389 // Pin the vtable to this file.
 390 void HexagonSubtarget::anchor() {}
 391
 392 bool HexagonSubtarget::enableMachineScheduler() const {
 393   if (DisableHexagonMISched.getNumOccurrences())
 394     return !DisableHexagonMISched;
 395   return true;
 396 }
 397
 398 bool HexagonSubtarget::usePredicatedCalls() const {
 399   return EnablePredicatedCalls;
 400 }
 401
 402 void HexagonSubtarget::updateLatency(MachineInstr &SrcInst,
 403       MachineInstr &DstInst, SDep &Dep) const {
 404   if (Dep.isArtificial()) {
 405     Dep.setLatency(1);
 406     return;
 407   }
 408
 409   if (!hasV60Ops())
 410     return;
 411
 412   auto &QII = static_cast<const HexagonInstrInfo&>(*getInstrInfo());
 413
 414   // BSB scheduling.
 415   if (QII.isHVXVec(SrcInst) || useBSBScheduling())
 416     Dep.setLatency((Dep.getLatency() + 1) >> 1);
 417 }
 418
 419 void HexagonSubtarget::restoreLatency(SUnit *Src, SUnit *Dst) const {
 420   MachineInstr *SrcI = Src->getInstr();
 421   for (auto &I : Src->Succs) {
 422     if (!I.isAssignedRegDep() || I.getSUnit() != Dst)
 423       continue;
 424     unsigned DepR = I.getReg();
 425     int DefIdx = -1;
 426     for (unsigned OpNum = 0; OpNum < SrcI->getNumOperands(); OpNum++) {
 427       const MachineOperand &MO = SrcI->getOperand(OpNum);
 428       if (MO.isReg() && MO.isDef() && MO.getReg() == DepR)
 429         DefIdx = OpNum;
 430     }
 431     assert(DefIdx >= 0 && "Def Reg not found in Src MI");
 432     MachineInstr *DstI = Dst->getInstr();
 433     SDep T = I;
 434     for (unsigned OpNum = 0; OpNum < DstI->getNumOperands(); OpNum++) {
 435       const MachineOperand &MO = DstI->getOperand(OpNum);
 436       if (MO.isReg() && MO.isUse() && MO.getReg() == DepR) {
 437         int Latency = (InstrInfo.getOperandLatency(&InstrItins, *SrcI,
 438                                                    DefIdx, *DstI, OpNum));
 439
 440         // For some instructions (ex: COPY), we might end up with < 0 latency
 441         // as they don't have any Itinerary class associated with them.
 442         Latency = std::max(Latency, 0);
 443
 444         I.setLatency(Latency);
 445         updateLatency(*SrcI, *DstI, I);
 446       }
 447     }
 448
 449     // Update the latency of opposite edge too.
 450     T.setSUnit(Src);
 451     auto F = std::find(Dst->Preds.begin(), Dst->Preds.end(), T);
 452     assert(F != Dst->Preds.end());
 453     F->setLatency(I.getLatency());
 454   }
 455 }
 456
 457 /// Change the latency between the two SUnits.
 458 void HexagonSubtarget::changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat)
 459       const {
 460   for (auto &I : Src->Succs) {
 461     if (!I.isAssignedRegDep() || I.getSUnit() != Dst)
 462       continue;
 463     SDep T = I;
 464     I.setLatency(Lat);
 465
 466     // Update the latency of opposite edge too.
 467     T.setSUnit(Src);
 468     auto F = std::find(Dst->Preds.begin(), Dst->Preds.end(), T);
 469     assert(F != Dst->Preds.end());
 470     F->setLatency(Lat);
 471   }
 472 }
 473
 474 /// If the SUnit has a zero latency edge, return the other SUnit.
 475 static SUnit *getZeroLatency(SUnit *N, SmallVector<SDep, 4> &Deps) {
 476   for (auto &I : Deps)
 477     if (I.isAssignedRegDep() && I.getLatency() == 0 &&
 478         !I.getSUnit()->getInstr()->isPseudo())
 479       return I.getSUnit();
 480   return nullptr;
 481 }
 482
 483 // Return true if these are the best two instructions to schedule
 484 // together with a zero latency. Only one dependence should have a zero
 485 // latency. If there are multiple choices, choose the best, and change
 486 // the others, if needed.
 487 bool HexagonSubtarget::isBestZeroLatency(SUnit *Src, SUnit *Dst,
 488       const HexagonInstrInfo *TII, SmallSet<SUnit*, 4> &ExclSrc,
 489       SmallSet<SUnit*, 4> &ExclDst) const {
 490   MachineInstr &SrcInst = *Src->getInstr();
 491   MachineInstr &DstInst = *Dst->getInstr();
 492
 493   // Ignore Boundary SU nodes as these have null instructions.
 494   if (Dst->isBoundaryNode())
 495     return false;
 496
 497   if (SrcInst.isPHI() || DstInst.isPHI())
 498     return false;
 499
 500   if (!TII->isToBeScheduledASAP(SrcInst, DstInst) &&
 501       !TII->canExecuteInBundle(SrcInst, DstInst))
 502     return false;
 503
 504   // The architecture doesn't allow three dependent instructions in the same
 505   // packet. So, if the destination has a zero latency successor, then it's
 506   // not a candidate for a zero latency predecessor.
 507   if (getZeroLatency(Dst, Dst->Succs) != nullptr)
 508     return false;
 509
 510   // Check if the Dst instruction is the best candidate first.
 511   SUnit *Best = nullptr;
 512   SUnit *DstBest = nullptr;
 513   SUnit *SrcBest = getZeroLatency(Dst, Dst->Preds);
 514   if (SrcBest == nullptr || Src->NodeNum >= SrcBest->NodeNum) {
 515     // Check that Src doesn't have a better candidate.
 516     DstBest = getZeroLatency(Src, Src->Succs);
 517     if (DstBest == nullptr || Dst->NodeNum <= DstBest->NodeNum)
 518       Best = Dst;
 519   }
 520   if (Best != Dst)
 521     return false;
 522
 523   // The caller frequently adds the same dependence twice. If so, then
 524   // return true for this case too.
 525   if ((Src == SrcBest && Dst == DstBest ) ||
 526       (SrcBest == nullptr && Dst == DstBest) ||
 527       (Src == SrcBest && Dst == nullptr))
 528     return true;
 529
 530   // Reassign the latency for the previous bests, which requires setting
 531   // the dependence edge in both directions.
 532   if (SrcBest != nullptr) {
 533     if (!hasV60Ops())
 534       changeLatency(SrcBest, Dst, 1);
 535     else
 536       restoreLatency(SrcBest, Dst);
 537   }
 538   if (DstBest != nullptr) {
 539     if (!hasV60Ops())
 540       changeLatency(Src, DstBest, 1);
 541     else
 542       restoreLatency(Src, DstBest);
 543   }
 544
 545   // Attempt to find another opprotunity for zero latency in a different
 546   // dependence.
 547   if (SrcBest && DstBest)
 548     // If there is an edge from SrcBest to DstBst, then try to change that
 549     // to 0 now.
 550     changeLatency(SrcBest, DstBest, 0);
 551   else if (DstBest) {
 552     // Check if the previous best destination instruction has a new zero
 553     // latency dependence opportunity.
 554     ExclSrc.insert(Src);
 555     for (auto &I : DstBest->Preds)
 556       if (ExclSrc.count(I.getSUnit()) == 0 &&
 557           isBestZeroLatency(I.getSUnit(), DstBest, TII, ExclSrc, ExclDst))
 558         changeLatency(I.getSUnit(), DstBest, 0);
 559   } else if (SrcBest) {
 560     // Check if previous best source instruction has a new zero latency
 561     // dependence opportunity.
 562     ExclDst.insert(Dst);
 563     for (auto &I : SrcBest->Succs)
 564       if (ExclDst.count(I.getSUnit()) == 0 &&
 565           isBestZeroLatency(SrcBest, I.getSUnit(), TII, ExclSrc, ExclDst))
 566         changeLatency(SrcBest, I.getSUnit(), 0);
 567   }
 568
 569   return true;
 570 }
 571
 572 unsigned HexagonSubtarget::getL1CacheLineSize() const {
 573   return 32;
 574 }
 575
 576 unsigned HexagonSubtarget::getL1PrefetchDistance() const {
 577   return 32;
 578 }
 579
 580 bool HexagonSubtarget::enableSubRegLiveness() const {
 581   return EnableSubregLiveness;
 582 }